events revision cc2ee177dbb3befca43e36cfc56778b006c3d050 
1# IA-64 Itanium 2 events
2
3# IA64_2 Basic Events, Table 11-1
4event:0x12 counters:0,1,2,3 um:zero minimum:500 name:CPU_CYCLES : CPU Cycles
5event:0x08 counters:0,1,2,3 um:zero minimum:500 name:IA64_INST_RETIRED : IA-64 Instructions Retired
6event:0x59 counters:0,1,2,3 um:zero minimum:5000 name:IA32_INST_RETIRED : IA-32 Instructions Retired
7event:0x07 counters:0,1,2,3 um:zero minimum:500 name:IA32_ISA_TRANSITIONS : Itanium to/from IA-32 ISA Transitions
8
9# IA64_2 Instruction Disperal Events, Table 11-3
10event:0x49 counters:0,1,2,3 um:zero minimum:5000 name:DISP_STALLED : Number of cycles dispersal stalled
11event:0x4d counters:0,1,2,3 um:zero minimum:5000 name:INST_DISPERSED : Syllables Dispersed from REN to REG stage
12event:0x4e counters:0,1,2,3 um:syll_not_dispersed minimum:5000 name:SYLL_NOT_DISPERSED : Syllables not dispersed
13event:0x4f counters:0,1,2,3 um:syll_overcount minimum:5000 name:SYLL_OVERCOUNT : Syllables overcounted
14
15# IA64_2 Instruction Execution Events, Table 11-4
16event:0x58 counters:0,1,2,3 um:alat_capacity_miss minimum:5000 name:ALAT_CAPACITY_MISS : ALAT Entry Replaced
17event:0x06 counters:0,1,2,3 um:zero minimum:5000 name:FP_FAILED_FCHKF : Failed fchkf
18event:0x05 counters:0,1,2,3 um:zero minimum:5000 name:FP_FALSE_SIRSTALL : SIR stall without a trap
19event:0x0b counters:0,1,2,3 um:zero minimum:5000 name:FP_FLUSH_TO_ZERO : Result Flushed to Zero
20event:0x09 counters:0,1,2,3 um:zero minimum:5000 name:FP_OPS_RETIRED : Retired FP operations
21event:0x03 counters:0,1,2,3 um:zero minimum:5000 name:FP_TRUE_SIRSTALL : SIR stall asserted and leads to a trap
22event:0x08 counters:0,1,2,3 um:tagged_inst_retired minimum:5000 name:IA64_TAGGED_INST_RETIRED : Retired Tagged Instructions
23event:0x56 counters:0,1,2,3 um:alat_capacity_miss minimum:5000 name:INST_CHKA_LDC_ALAT : Advanced Check Loads
24event:0x57 counters:0,1,2,3 um:alat_capacity_miss minimum:5000 name:INST_FAILED_CHKA_LDC_ALAT : Failed Advanced Check Loads
25event:0x55 counters:0,1,2,3 um:alat_capacity_miss minimum:5000 name:INST_FAILED_CHKS_RETIRED : Failed Speculative Check Loads
26# To avoid duplication from other tables the following events commented out
27#event:0xcd counters:0,1,2,3 um:zero minimum:5000 name:LOADS_RETIRED : Retired Loads
28#event:0xce counters:0,1,2,3 um:zero minimum:5000 name:MISALIGNED_LOADS_RETIRED : Retired Misaligned Load Instructions
29#event:0xcf counters:0,1,2,3 um:zero minimum:5000 name:UC_LOADS_RETIRED : Retired Uncacheable Loads
30#event:0xd1 counters:0,1,2,3 um:zero minimum:5000 name:STORES_RETIRED : Retired Stores
31#event:0xd2 counters:0,1,2,3 um:zero minimum:5000 name:MISALIGNED_STORES_RETIRED : Retired Misaligned Store Instructions
32#event:0xd0 counters:0,1,2,3 um:zero minimum:5000 name:UC_STORES_RETIRED : Retired Uncacheable Stores
33event:0x50 counters:0,1,2,3 um:zero minimum:5000 name:NOPS_RETIRED : Retired NOP Instructions
34event:0x51 counters:0,1,2,3 um:zero minimum:5000 name:PREDICATE_SQUASHED_RETIRED : Instructions Squashed Due to Predicate Off`
35
36# IA64_2 Stall Events, Table 11-6
37event:0x00 counters:0,1,2,3 um:back_end_bubble minimum:5000 name:BACK_END_BUBBLE : Full pipe bubbles in main pipe
38event:0x02 counters:0,1,2,3 um:be_exe_bubble minimum:5000 name:BE_EXE_BUBBLE : Full pipe bubbles in main pipe due to Execution unit stalls
39event:0x04 counters:0,1,2,3 um:be_flush_bubble minimum:5000 name:BE_FLUSH_BUBBLE : Full pipe bubbles in main pipe due to flushes
40event:0xca counters:0,1,2,3 um:be_l1d_fpu_bubble minimum:5000 name:BE_L1D_FPU_BUBBLE : Full pipe bubbles in main pipe due to FP or L1 dcache
41# To avoid duplication from other tables the following events commented out
42#event:0x72 counters:0,1,2,3 um:be_lost_bw_due_to_fe minimum:5000 name:BE_LOST_BW_DUE_TO_FE : Invalid bundles if BE not stalled for other reasons
43event:0x01 counters:0,1,2,3 um:be_rse_bubble minimum:5000 name:BE_RSE_BUBBLE : Full pipe bubbles in main pipe due to RSE stalls
44event:0x71 counters:0,1,2,3 um:fe_bubble minimum:5000 name:FE_BUBBLE : Bubbles seen by FE
45event:0x70 counters:0,1,2,3 um:fe_lost minimum:5000 name:FE_LOST_BW : Invalid bundles at the entrance to IB
46event:0x73 counters:0,1,2,3 um:fe_lost minimum:5000 name:IDEAL_BE_LOST_BW_DUE_TO_FE : Invalid bundles at the exit from IB
47
48# IA64_2 Branch Events, Table 11-7
49event:0x61 counters:0,1,2,3 um:be_br_mispredict_detail minimum:5000 name:BE_BR_MISPRED_DETAIL : BE branch misprediction detail
50event:0x11 counters:0,1,2,3 um:zero minimum:5000 name:BRANCH_EVENT : Branch Event Captured
51event:0x5b counters:0,1,2,3 um:br_mispred_detail minimum:5000 name:BR_MISPRED_DETAIL : Branch Mispredict Detail
52event:0x68 counters:0,1,2,3 um:br_mispredict_detail2 minimum:5000 name:BR_MISPRED_DETAIL2 : FE Branch Mispredict Detail (Unknown path component)
53event:0x54 counters:0,1,2,3 um:br_path_pred minimum:5000 name:BR_PATH_PRED : FE Branch Path Prediction Detail
54event:0x6a counters:0,1,2,3 um:br_path_pred2 minimum:5000 name:BR_PATH_PRED2 : FE Branch Path Prediction Detail (Unknown prediction component)
55event:0x63 counters:0,1,2,3 um:encbr_mispred_detail minimum:5000 name:ENCBR_MISPRED_DETAIL : Number of encoded branches retired
56
57# IA64_2 L1 Instruction Cache and Prefetch Events, Table 11-8
58event:0x46 counters:0,1,2,3 um:zero minimum:5000 name:ISB_BUNPAIRS_IN : Bundle pairs written from L2 into FE
59event:0x43 counters:0,1,2,3 um:zero minimum:5000 name:L1I_EAR_EVENTS : Instruction EAR Events
60event:0x66 counters:0,1,2,3 um:zero minimum:5000 name:L1I_FETCH_ISB_HIT : "\"Just-in-time\" instruction fetch hitting in and being bypassed from ISB
61event:0x65 counters:0,1,2,3 um:zero minimum:5000 name:L1I_FETCH_RAB_HIT : Instruction fetch hitting in RAB
62event:0x41 counters:0,1,2,3 um:zero minimum:5000 name:L1I_FILLS : L1 Instruction Cache Fills
63event:0x44 counters:0,1,2,3 um:zero minimum:5000 name:L1I_PREFETCHES : Instruction Prefetch Requests
64event:0x42 counters:0,1,2,3 um:zero minimum:5000 name:L2_INST_DEMAND_READS : L1 Instruction Cache and ISB Misses
65event:0x67 counters:0,1,2,3 um:l1i_prefetch_stall minimum:5000 name:L1I_PREFETCH_STALL : Why prefetch pipeline is stalled?
66event:0x4b counters:0,1,2,3 um:zero minimum:5000 name:L1I_PURGE : L1ITLB purges handled by L1I
67event:0x69 counters:0,1,2,3 um:zero minimum:5000 name:L1I_PVAB_OVERFLOW : PVAB overflow
68event:0x64 counters:0,1,2,3 um:zero minimum:5000 name:L1I_RAB_ALMOST_FULL : Is RAB almost full?
69event:0x60 counters:0,1,2,3 um:zero minimum:500 name:L1I_RAB_FULL : Is RAB full?
70event:0x40 counters:0,1,2,3 um:zero minimum:5000 name:L1I_READS : L1 Instruction Cache Read
71event:0x4a counters:0,1,2,3 um:zero minimum:5000 name:L1I_SNOOP : Snoop requests handled by L1I
72event:0x5f counters:0,1,2,3 um:zero minimum:5000 name:L1I_STRM_PREFETCHES : L1 Instruction Cache line prefetch requests
73event:0x45 counters:0,1,2,3 um:zero minimum:5000 name:L2_INST_PREFETCHES : Instruction Prefetch Requests
74
75# IA64_2 L1 Data Cache Events, Table 11-10
76event:0xc8 counters:0,1,2,3 um:zero minimum:5000 name:DATA_EAR_EVENTS : Data Cache EAR Events
77# To avoid duplication from other tables the following events commented out
78#event:0xc2 counters:0,1,2,3 um:zero minimum:5000 name:L1D_READS_SET0 : L1 Data Cache Reads
79#event:0xc3 counters:0,1,2,3 um:zero minimum:5000 name:DATA_REFERENCES_SET0 : Data memory references issued to memory pipeline
80#event:0xc4 counters:0,1,2,3 um:zero minimum:5000 name:L1D_READS_SET1 : L1 Data Cache Reads
81#event:0xc5 counters:0,1,2,3 um:zero minimum:5000 name:DATA_REFERENCES_SET1 : Data memory references issued to memory pipeline
82#event:0xc7 counters:0,1,2,3 um:l1d_read_misses minimum:5000 name:L1D_READ_MISSES : L1 Data Cache Read Misses
83
84# IA64_2 L1 Data Cache Set 0 Events, Table 11-11
85event:0xc0 counters:1 um:zero minimum:5000 name:L1DTLB_TRANSFER : L1DTLB misses that hit in the L2DTLB for accesses counted in L1D_READS
86event:0xc1 counters:1 um:zero minimum:5000 name:L2DTLB_MISSES : L2DTLB Misses
87event:0xc2 counters:1 um:zero minimum:5000 name:L1D_READS_SET0 : L1 Data Cache Reads
88event:0xc3 counters:1 um:zero minimum:5000 name:DATA_REFERENCES_SET0 : Data memory references issued to memory pipeline
89
90# IA64_2 L1 Data Cache Set 1 Events, Table 11-12
91event:0xc4 counters:1 um:zero minimum:5000 name:L1D_READS_SET1 : L1 Data Cache Reads
92event:0xc5 counters:1 um:zero minimum:5000 name:DATA_REFERENCES_SET1 : Data memory references issued to memory pipeline
93event:0xc7 counters:1 um:l1d_read_misses minimum:5000 name:L1D_READ_MISSES : L1 Data Cache Read Misses
94
95# IA64_2 L1 Data Cache Set 2 Events, Table 11-13
96event:0xca counters:1 um:be_l1d_fpu_bubble minimum:5000 name:BE_L1D_FPU_BUBBLE : Full pipe bubbles in main pipe due to FP or L1 dcache
97
98# IA64_2 L1 Data Cache Set 3 Events, Table 11-14
99event:0xcd counters:1 um:zero minimum:5000 name:LOADS_RETIRED : Retired Loads
100event:0xce counters:1 um:zero minimum:5000 name:MISALIGNED_LOADS_RETIRED : Retired Misaligned Load Instructions
101event:0xcf counters:1 um:zero minimum:5000 name:UC_LOADS_RETIRED : Retired Uncacheable Loads
102
103# IA64_2 L1 Data Cache Set 4 Events, Table 11-15
104event:0xd1 counters:1 um:zero minimum:5000 name:STORES_RETIRED : Retired Stores
105event:0xd2 counters:1 um:zero minimum:5000 name:MISALIGNED_STORES_RETIRED : Retired Misaligned Store Instructions
106event:0xd0 counters:1 um:zero minimum:5000 name:UC_STORES_RETIRED : Retired Uncacheable Stores
107
108# IA64_2 L2 Unified Cache Events, Table 11-16
109# To avoid duplication from other tables the following events commented out
110#event:0xb9 counters:0,1,2,3 um:zero minimum:5000 name:L2_BAD_LINES_SELECTED : Valid line replaced when invalid line is available
111#event:0xb8 counters:0,1,2,3 um:l2_bypass minimum:5000 name:L2_BYPASS : Count bypass
112#event:0xb2 counters:0,1,2,3 um:l2_data_references minimum:5000 name:L2_DATA_REFERENCES : Data read/write access to L2
113event:0xbf counters:0,1,2,3 um:zero minimum:5000 name:L2_FILLB_FULL : L2D Fill buffer is full
114#event:0xb4 counters:0,1,2,3 um:l2_force_recirc minimum:5000 name:L2_FORCE_RECIRC : Forced recirculates
115event:0xba counters:0,1,2,3 um:recirc_ifetch minimum:5000 name:L2_GOT_RECIRC_IFETCH : Instruction fetch recirculates received by L2D
116#event:0xb6 counters:0,1,2,3 um:zero minimum:5000 name:L2_GOT_RECIRC_OZQ_ACC : Counts number of OZQ accesses recirculated back to L1D
117#event:0xa1 counters:0,1,2,3 um:l2_ifet_cancels minimum:5000 name:L2_IFET_CANCELS : Instruction fetch cancels by the L2.
118#event:0xa5 counters:0,1,2,3 um:l2_ifet_cancels minimum:5000 name:L2_IFET_CANCELS : Instruction fetch cancels by the L2.
119#event:0xa9 counters:0,1,2,3 um:l2_ifet_cancels minimum:5000 name:L2_IFET_CANCELS : Instruction fetch cancels by the L2.
120#event:0xad counters:0,1,2,3 um:l2_ifet_cancels minimum:5000 name:L2_IFET_CANCELS : Instruction fetch cancels by the L2.
121event:0xb9 counters:0,1,2,3 um:recirc_ifetch minimum:5000 name:L2_ISSUED_RECIRC_IFETCH : Instruction fetch recirculates issued by L2D
122#event:0xb5 counters:0,1,2,3 um:zero minimum:5000 name:L2_ISSUED_RECIRC_OZQ_ACC : Count number of times a recirculate issue was attempted and not preempted
123#event:0xb0 counters:0,1,2,3 um:l2_l3_access_cancel minimum:5000 name:L2_L3ACCESS_CANCEL : Canceled L3 accesses
124event:0xcb counters:0,1,2,3 um:zero minimum:5000 name:L2_MISSES : L2 Misses
125event:0xb8 counters:0,1,2,3 um:l2_ops_issued minimum:5000 name:L2_OPS_ISSUED : Different operations issued by L2D
126#event:0xbd counters:0,1,2,3 um:zero minimum:5000 name:L2_OZDB_FULL : L2D OZQ is full
127#event:0xa2 counters:0,1,2,3 um:zero minimum:5000 name:L2_OZQ_ACQUIRE : Clocks with acquire ordering attribute existed in L2 OZQ
128#event:0xa6 counters:0,1,2,3 um:zero minimum:5000 name:L2_OZQ_ACQUIRE : Clocks with acquire ordering attribute existed in L2 OZQ
129#event:0xaa counters:0,1,2,3 um:zero minimum:5000 name:L2_OZQ_ACQUIRE : Clocks with acquire ordering attribute existed in L2 OZQ
130#event:0xae counters:0,1,2,3 um:zero minimum:5000 name:L2_OZQ_ACQUIRE : Clocks with acquire ordering attribute existed in L2 OZQ
131#event:0xa0 counters:0,1,2,3 um:l2_ozq_cancels0 minimum:5000 name:L2_OZQ_CANCELS0 : L2 OZQ cancels
132#event:0xac counters:0,1,2,3 um:l2_ozq_cancels1 minimum:5000 name:L2_OZQ_CANCELS1 : L2 OZQ cancels
133#event:0xa8 counters:0,1,2,3 um:l2_ozq_cancels2 minimum:5000 name:L2_OZQ_CANCELS2 : L2 OZQ cancels
134#event:0xbc counters:0,1,2,3 um:zero minimum:5000 name:L2_OZQ_FULL : L2D OZQ is full
135#event:0xa3 counters:0,1,2,3 um:zero minimum:5000 name:L2_OZQ_RELEASE : Clocks with release ordering attribute existed in L2 OZQ
136#event:0xa7 counters:0,1,2,3 um:zero minimum:5000 name:L2_OZQ_RELEASE : Clocks with release ordering attribute existed in L2 OZQ
137#event:0xab counters:0,1,2,3 um:zero minimum:5000 name:L2_OZQ_RELEASE : Clocks with release ordering attribute existed in L2 OZQ
138#event:0xaf counters:0,1,2,3 um:zero minimum:5000 name:L2_OZQ_RELEASE : Clocks with release ordering attribute existed in L2 OZQ
139#event:0xb1 counters:0,1,2,3 um:zero minimum:5000 name:L2_REFERENCES : Requests made from L2
140#event:0xba counters:0,1,2,3 um:zero minimum:5000 name:L2_STORE_HIT_SHARED : Store hit a shared line
141#event:0xb7 counters:0,1,2,3 um:zero minimum:5000 name:L2_SYNTH_PROBE : Synthesized Probe
142#event:0xbe counters:0,1,2,3 um:zero minimum:5000 name:L2_VICTIMB_FULL : L2D victim buffer is full
143
144# IA64_2 L2 Cache Events Set 0, Table 11-18
145# FIXME all sorts of restrictions on how these can be combined
146event:0xa1 counters:0 um:l2_ifet_cancels minimum:5000 name:L2_IFET_CANCELS : Instruction fetch cancels by the L2.
147event:0xa5 counters:0 um:l2_ifet_cancels minimum:5000 name:L2_IFET_CANCELS : Instruction fetch cancels by the L2.
148event:0xa9 counters:0 um:l2_ifet_cancels minimum:5000 name:L2_IFET_CANCELS : Instruction fetch cancels by the L2.
149event:0xad counters:0 um:l2_ifet_cancels minimum:5000 name:L2_IFET_CANCELS : Instruction fetch cancels by the L2.
150event:0xa2 counters:0 um:zero minimum:5000 name:L2_OZQ_ACQUIRE : Clocks with acquire ordering attribute existed in L2 OZQ
151event:0xa6 counters:0 um:zero minimum:5000 name:L2_OZQ_ACQUIRE : Clocks with acquire ordering attribute existed in L2 OZQ
152event:0xaa counters:0 um:zero minimum:5000 name:L2_OZQ_ACQUIRE : Clocks with acquire ordering attribute existed in L2 OZQ
153event:0xae counters:0 um:zero minimum:5000 name:L2_OZQ_ACQUIRE : Clocks with acquire ordering attribute existed in L2 OZQ
154event:0xa0 counters:0 um:l2_ozq_cancels0 minimum:5000 name:L2_OZQ_CANCELS0 : L2 OZQ cancels
155event:0xac counters:0 um:l2_ozq_cancels1 minimum:5000 name:L2_OZQ_CANCELS1 : L2 OZQ cancels
156event:0xa8 counters:0 um:l2_ozq_cancels2 minimum:5000 name:L2_OZQ_CANCELS2 : L2 OZQ cancels
157event:0xa3 counters:0 um:zero minimum:5000 name:L2_OZQ_RELEASE : Clocks with release ordering attribute existed in L2 OZQ
158event:0xa7 counters:0 um:zero minimum:5000 name:L2_OZQ_RELEASE : Clocks with release ordering attribute existed in L2 OZQ
159event:0xab counters:0 um:zero minimum:5000 name:L2_OZQ_RELEASE : Clocks with release ordering attribute existed in L2 OZQ
160event:0xaf counters:0 um:zero minimum:5000 name:L2_OZQ_RELEASE : Clocks with release ordering attribute existed in L2 OZQ
161
162# IA64_2 L2 Cache Events Set 1, Table 11-19
163# manual states that L2_L3ACCESS_CANCEL must be measured in PMD4.
164# FIXME Don't have any way of enforcing the constraints
165# so only l2_l3_access_cancel allowed.
166event:0xb0 counters:0 um:l2_l3_access_cancel minimum:5000 name:L2_L3ACCESS_CANCEL : Canceled L3 accesses
167#event:0xb2 counters:0,1,2,3 um:l2_data_references minimum:5000 name:L2_DATA_REFERENCES : Data read/write access to L2
168#event:0xb1 counters:0,1,2,3 um:zero minimum:5000 name:L2_REFERENCES : Requests made from L2
169
170# IA64_2 L2 Cache Events Set 2, Table 11-20
171# manual states that L2_FORCE_RECIRC must be measured in PMD4.
172# FIXME Don't have anyway of enforcing thes constraint
173# so only L2_FORCE_RECIRC allowed.
174event:0xb4 counters:0 um:l2_force_recirc minimum:5000 name:L2_FORCE_RECIRC : Forced recirculates
175#event:0xb5 counters:0,1,2,3 um:zero minimum:5000 name:L2_ISSUED_RECIRC_OZQ_ACC : Count number of times a recirculate issue was attempted and not preempted
176#event:0xb6 counters:0,1,2,3 um:zero minimum:5000 name:L2_GOT_RECIRC_OZQ_ACC : Counts number of OZQ accesses recirculated back to L1D
177#event:0xb7 counters:0,1,2,3 um:zero minimum:5000 name:L2_SYNTH_PROBE : Synthesized Probe
178
179# IA64_2 L2 Cache Events Set 3, Table 11-21
180# The manual states that all events in this set share the same umask.
181event:0xb9 counters:0 um:zero minimum:5000 name:L2_BAD_LINES_SELECTED : Valid line replaced when invalid line is available
182event:0xb8 counters:0 um:l2_bypass minimum:5000 name:L2_BYPASS : Count bypass
183event:0xba counters:0 um:zero minimum:5000 name:L2_STORE_HIT_SHARED : Store hit a shared line
184
185# IA64_2 L2 Cache Events Set 4, Table 11-22
186# The manual states one of the following needs to be in pmd4 and these events
187# share the same umask.
188event:0xba counters:0 um:recirc_ifetch minimum:5000 name:L2_GOT_RECIRC_IFETCH : Instruction fetch recirculates received by L2D
189event:0xb9 counters:0 um:recirc_ifetch minimum:5000 name:L2_ISSUED_RECIRC_IFETCH : Instruction fetch recirculates issued by L2D
190event:0xb8 counters:0 um:l2_ops_issued minimum:5000 name:L2_OPS_ISSUED : Different operations issued by L2D
191
192# IA64_2 L2 Cache Events Set 5, Table 11-23
193# manual states one of the following needs to be in pmd4 and
194#       these events share the same umask
195event:0xbc counters:0 um:zero minimum:5000 name:L2_OZQ_FULL : L2D OZQ is full
196event:0xbd counters:0 um:zero minimum:5000 name:L2_OZDB_FULL : L2D OZQ is full
197event:0xbe counters:0 um:zero minimum:5000 name:L2_VICTIMB_FULL : L2D victim buffer is full
198event:0xbf counters:0 um:zero minimum:5000 name:L2_FILLB_FULL : L2D Fill buffer is full
199
200# IA64_2 L3 Cache Events, Table 11-24
201event:0xdf counters:0,1,2,3 um:zero minimum:5000 name:L3_LINES_REPLACED : Cache Lines Replaced
202event:0xdc counters:0,1,2,3 um:zero minimum:5000 name:L3_MISSES : L3 Misses
203event:0xdb counters:0,1,2,3 um:zero minimum:5000 name:L3_REFERENCES : L3 References
204event:0xdd counters:0,1,2,3 um:l3_reads minimum:5000 name:L3_READS : L3 Reads
205event:0xde counters:0,1,2,3 um:l3_writes minimum:5000 name:L3_WRITES : L3 Writes
206
207# IA64_2 System Events, Table 11-26
208event:0x13 counters:0,1,2,3 um:zero minimum:5000 name:CPU_CPL_CHANGES : Privilege Level Changes
209event:0x52 counters:0,1,2,3 um:zero minimum:5000 name:DATA_DEBUG_REGISTER_FAULT : Fault due to data debug reg. Match to load/store instruction
210event:0xc6 counters:0,1,2,3 um:zero minimum:5000 name:DATA_DEBUG_REGISTER_MATCHES : Data debug register matches data address of memory reference
211event:0x9e counters:0,1,2,3 um:extern_dp_pins_0_to_3 minimum:5000 name:EXTERN_DP_PINS_0_TO_3 : DP pins 0-3 asserted
212event:0x9f counters:0,1,2,3 um:extern_dp_pins_4_to_5 minimum:5000 name:EXTERN_DP_PINS_4_TO_5 : DP pins 4-5 asserted
213event:0x53 counters:0,1,2,3 um:zero minimum:5000 name:SERIALIZATION_EVENTS : Number of srlz.I instructions
214
215# IA64_2 TLB Events, Table 11-28
216event:0xc9 counters:0,1,2,3 um:zero minimum:5000 name:DTLB_INSERTS_HPW : Hardware Page Walker Installs to DTLB"
217event:0x2c counters:0,1,2,3 um:zero minimum:500 name:DTLB_INSERTS_HPW_RETIRED : VHPT entries inserted into DTLB by HW PW
218event:0x2d counters:0,1,2,3 um:zero minimum:500 name:HPW_DATA_REFERENCES : Data memory references to VHPT
219#event:0xc1 counters:1 um:zero minimum:5000 name:L2DTLB_MISSES : L2DTLB Misses
220event:0x48 counters:0,1,2,3 um:zero minimum:5000 name:L1ITLB_INSERTS_HPW : L1ITLB Hardware Page Walker Inserts
221event:0x47 counters:0,1,2,3 um:itlb_misses_fetch minimum:5000 name:ITLB_MISSES_FETCH : ITLB Misses Demand Fetch
222#event:0xc0 counters:1 um:zero minimum:5000 name:L1DTLB_TRANSFER : L1DTLB misses that hit in the L2DTLB for accesses counted in L1D_READS
223
224# IA64_2 System Bus Events, Table 11-30
225event:0x87 counters:0,1,2,3 um:bus minimum:5000 name:BUS_ALL : Bus Transactions
226event:0x9c counters:0,1,2,3 um:zero minimum:5000 name:BUS_BRQ_LIVE_REQ_HI : BRQ Live Requests (two most-significant-bit of the 5-bit outstanding BRQ request count)
227event:0x9b counters:0,1,2,3 um:zero minimum:5000 name:BUS_BRQ_LIVE_REQ_LO : BRQ Live Requests (three least-significant-bit of the 5-bit outstanding BRQ request count
228event:0x9d counters:0,1,2,3 um:zero minimum:5000 name:BUS_BRQ_REQ_INSERTED : BRQ Requests Inserted
229event:0x88 counters:0,1,2,3 um:zero minimum:5000 name:BUS_DATA_CYCLE : Valid data cycle on the Bus
230event:0x84 counters:0,1,2,3 um:zero minimum:5000 name:BUS_HITM : Bus Hit Modified Line Transactions
231event:0x90 counters:0,1,2,3 um:bus minimum:5000 name:BUS_IO : IA-32 Compatible IO Bus Transactions
232event:0x98 counters:0,1,2,3 um:zero minimum:5000 name:BUS_IOQ_LIVE_REQ_HI : Inorder Bus Queue Requests (two most-significant-bit of the 4-bit outstanding IOQ request count)
233event:0x97 counters:0,1,2,3 um:zero minimum:5000 name:BUS_IOQ_LIVE_REQ_LO : Inorder Bus Queue Requests (two least-significant-bit of the 4-bit outstanding IOQ request count)
234event:0x93 counters:0,1,2,3 um:bus_lock minimum:5000 name:BUS_LOCK : IA-32 Compatible Bus Lock Transactions
235event:0x8e counters:0,1,2,3 um:bus_backsnp_req minimum:5000 name:BUS_BACKSNP_REQ : Bus Back Snoop Requests
236event:0x8a counters:0,1,2,3 um:bus_memory minimum:5000 name:BUS_MEMORY : Bus Memory Transactions
237event:0x8b counters:0,1,2,3 um:bus_mem_read minimum:5000 name:BUS_MEM_READ : Full Cache line D/I memory RD, RD invalidate, and BRIL
238event:0x94 counters:0,1,2,3 um:zero minimum:5000 name:BUS_MEM_READ_OUT_HI : Outstanding memory RD transactions
239event:0x95 counters:0,1,2,3 um:zero minimum:5000 name:BUS_MEM_READ_OUT_LO : Outstanding memory RD transactions
240event:0x9a counters:0,1,2,3 um:zero minimum:5000 name:BUS_OOQ_LIVE_REQ_HI : Out-of-order Bus Queue Requests (two most-significant-bit of the 4-bit outstanding OOQ request count)
241event:0x99 counters:0,1,2,3 um:zero minimum:5000 name:BUS_OOQ_LIVE_REQ_LO : Out-of-order Bus Queue Requests (three least-significant-bit of the 4-bit outstanding OOQ request count)
242event:0x8c counters:0,1,2,3 um:bus minimum:5000 name:BUS_RD_DATA : Bus Read Data Transactions
243event:0x80 counters:0,1,2,3 um:zero minimum:5000 name:BUS_RD_HIT : Bus Read Hit Clean Non-local Cache Transactions
244event:0x81 counters:0,1,2,3 um:zero minimum:5000 name:BUS_RD_HITM : Bus Read Hit Modified Non-local Cache Transactions
245event:0x83 counters:0,1,2,3 um:zero minimum:5000 name:BUS_RD_INVAL_ALL_HITM : Bus BIL or BRIL Transaction Results in HITM
246event:0x82 counters:0,1,2,3 um:zero minimum:5000 name:BUS_RD_INVAL_HITM : Bus BIL Transaction Results in HITM
247event:0x91 counters:0,1,2,3 um:bus minimum:5000 name:BUS_RD_IO : IA-32 Compatible IO Read Transactions
248event:0x8d counters:0,1,2,3 um:bus minimum:5000 name:BUS_RD_PRTL : Bus Read Partial Transactions
249event:0x96 counters:0,1,2,3 um:zero minimum:5000 name:BUS_SNOOPQ_REQ : Bus Snoop Queue Requests
250event:0x86 counters:0,1,2,3 um:bus minimum:5000 name:BUS_SNOOPS : Bus Snoops Total
251event:0x85 counters:0,1,2,3 um:bus_snoop minimum:5000 name:BUS_SNOOPS_HITM : Bus Snoops HIT Modified Cache Line
252event:0x8f counters:0,1,2,3 um:bus_snoop minimum:5000 name:BUS_SNOOP_STALL_CYCLES : Bus Snoop Stall Cycles (from any agent)
253event:0x92 counters:0,1,2,3 um:bus_wr_wb minimum:5000 name:BUS_WR_WB : Bus Write Back Transactions
254event:0x89 counters:0,1,2,3 um:mem_read_current minimum:5000 name:MEM_READ_CURRENT : Current Mem Read Transactions On Bus
255
256# RSE Events, Table 11-34
257event:0x2b counters:0,1,2,3 um:zero minimum:500 name:RSE_CURRENT_REGS_2_TO_0 : Current RSE registers
258event:0x2a counters:0,1,2,3 um:zero minimum:500 name:RSE_CURRENT_REGS_5_TO_3 : Current RSE registers
259event:0x26 counters:0,1,2,3 um:zero minimum:500 name:RSE_CURRENT_REGS_6 : Current RSE registers
260event:0x29 counters:0,1,2,3 um:zero minimum:500 name:RSE_DIRTY_REGS_2_TO_0 : Dirty RSE registers
261event:0x28 counters:0,1,2,3 um:zero minimum:500 name:RSE_DIRTY_REGS_5_TO_3 : Dirty RSE registers
262event:0x24 counters:0,1,2,3 um:zero minimum:500 name:RSE_DIRTY_REGS_6 : Dirty RSE registers
263event:0x32 counters:0,1,2,3 um:zero minimum:500 name:RSE_EVENT_RETIRED : Retired RSE operations
264event:0x20 counters:0,1,2,3 um:rse_references_retired minimum:500 name:RSE_REFERENCES_RETIRED : RSE Accesses
265
266# IA64 Performance Monitors Ordered by Code, Table 11-36
267event:0xbb counters:0,1,2,3 um:zero minimum:5000 name:TAGGED_L2_DATA_RETURN_POR : Tagged L2 Data Return Ports 0/1
268