events revision cc2ee177dbb3befca43e36cfc56778b006c3d050
1# 2# MIPS 24K 3# 4# As standard the CPU supports 2 performance counters. Event 0, 1, 11, 22, 5# are available on both counters; events 12, 13, 24 - 63 are reserved; 6# the remaining are counter-specific. 7# 8event:0 counters:0,1 um:zero minimum:500 name:CYCLES : Cycles 9event:1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS : Instructions completed 10event:11 counters:0,1 um:zero minimum:500 name:DCACHE_MISS : Data cache misses 11event:22 counters:0,1 um:zero minimum:500 name:L2_MISSES : L2 cache misses 12 13# 14# Events specific to counter 0 15# 16event:2 counters:0 um:zero minimum:500 name:BRANCHES_LAUNCHED : Branch instructions launched (whether completed or mispredicted) 17event:3 counters:0 um:zero minimum:500 name:JR_31_LAUNCHED : jr r31 (return) instructions launched (whether completed or mispredicted) 18event:4 counters:0 um:zero minimum:500 name:JR_NON_31_LAUNCHED : jr (not r31) issues, which cost the same as a mispredict. 19event:5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : Instruction micro-TLB accesses 20event:6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : Data micro-TLB accesses 21event:7 counters:0 um:zero minimum:500 name:JTLB_DATA_ACCESSES : Joint TLB instruction accesses 22event:8 counters:0 um:zero minimum:500 name:JTLB_INSTRUCTION_ACCESSES : Joint TLB data (non-instruction) accesses 23event:9 counters:0 um:zero minimum:500 name:INSTRUCTION_CACHE_ACCESSES : Instruction cache accesses 24event:10 counters:0 um:zero minimum:500 name:DCACHE_ACCESSES : Data cache accesses 25event:14 counters:0 um:zero minimum:500 name:INTEGER_INSNS_COMPLETED : Integer instructions completed 26event:15 counters:0 um:zero minimum:500 name:LOADS_COMPLETED : Loads completed (including FP) 27event:16 counters:0 um:zero minimum:500 name:J_JAL_INSNS_COMPLETED : j/jal instructions completed 28event:17 counters:0 um:zero minimum:500 name:NOPS_COMPLETED : no-ops completed, ie instructions writing $0 29event:18 counters:0 um:zero minimum:500 name:STALLS : Stalls 30event:19 counters:0 um:zero minimum:500 name:SC_COMPLETED : sc instructions completed 31event:20 counters:0 um:zero minimum:500 name:PREFETCH_COMPLETED : Prefetch instructions completed 32event:21 counters:0 um:zero minimum:500 name:SCACHE_WRITEBACKS : L2 cache writebacks 33event:23 counters:0 um:zero minimum:500 name:EXCEPTIONS_TAKEN : Exceptions taken 34event:24 counters:0 um:zero minimum:500 name:CACHE_FIXUPS : ``cache fixup'' events (specific to the 24K family microarchitecture). 35 36# 37# Events specific to counter 1 38# 39event:2 counters:1 um:zero minimum:500 name:BRANCH_MISSPREDICTS : Branch mispredictions 40event:3 counters:1 um:zero minimum:500 name:JR_31_MISSPREDICTS : jr r31 (return) mispredictions 41event:5 counters:1 um:zero minimum:500 name:ITLB_MISSES : Instruction micro-TLB misses 42event:6 counters:1 um:zero minimum:500 name:DTLB_MISSES : Data micro-TLB misses 43event:7 counters:1 um:zero minimum:500 name:JTLB_INSN_MISSES : Joint TLB instruction misses 44event:8 counters:1 um:zero minimum:500 name:JTLB_DATA_MISSES : Joint TLB data (non-instruction) misses 45event:9 counters:1 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses 46event:10 counters:1 um:zero minimum:500 name:DCACHE_WRITEBACKS : Data cache writebacks 47event:14 counters:1 um:zero minimum:500 name:FPU_INSNS_NON_LOAD_STORE_COMPLETED : FPU instructions completed (not including loads/stores) 48event:15 counters:1 um:zero minimum:500 name:STORES_COMPLETED : Stores completed (including FP) 49event:16 counters:1 um:zero minimum:500 name:MIPS16_INSTRUCTIONS_COMPLETED : MIPS16 instructions completed 50event:17 counters:1 um:zero minimum:500 name:INTEGER_MUL_DIV_COMPLETED : integer multiply/divide unit instructions completed 51event:18 counters:1 um:zero minimum:500 name:REPLAY_TRAPS_NOT_UTLB : ``replay traps'' (other than micro-TLB related) 52event:19 counters:1 um:zero minimum:500 name:SC_COMPLETE_BUT_FAILED : sc instructions completed, but store failed (because the link bit had been cleared). 53event:20 counters:1 um:zero minimum:500 name:SUPERFLUOUS_INSTRUCTIONS : ``superfluous'' prefetch instructions (data was already in cache). 54event:21 counters:1 um:zero minimum:500 name:SCACHE_ACCESSES : L2 cache accesses 55