events revision cc2ee177dbb3befca43e36cfc56778b006c3d050
1# 2# VR5500, VR5532 and VR7701 events 3# 4# Very similar to what the VR5432 provides. 5# 6event:0 counters:0,1 um:zero minimum:500 name:CYCLES : Processor clock cycles 7event:1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_EXECUTED : Instructions executed 8event:2 counters:0,1 um:zero minimum:500 name:LOAD_PREF_CACHE_INSTRUCTIONS : Execution of load/prefetch/cache instruction 9event:3 counters:0,1 um:zero minimum:500 name:STORES : Execution of store instruction 10event:4 counters:0,1 um:zero minimum:500 name:BRANCHES : Execution of branch instruction 11event:5 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS : Execution of floating-point instruction 12event:6 counters:0,1 um:zero minimum:500 name:DOUBLEWORDS_FLUSHED : Doubleword flush to main memory 13event:7 counters:0,1 um:zero minimum:500 name:JTLB_REFILLS : TLB refill 14event:8 counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Data cache miss 15event:9 counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache miss 16event:10 counters:0,1 um:zero minimum:500 name:BRANCHES_MISPREDICTED : Branch prediction miss 17