events revision 7a33c86eb98056ef0570c99e713214f8dc56b6ef
1# ppc64 pa6t events 2# 3# Unlike the IBM ppc64 chips, any of pa6t's events can be programmed into any 4# of the counters (pmc2-5). The notion of groups on pa6t is thus 5# artificial. That said, we can still define useful aggregations to guide the 6# user in his choice of group for a profiling session. 7 8# Group Default 9event:0x1 counters:0 um:zero minimum:10000 name:CYCLES : Processor Cycles 10event:0x3 counters:3 um:zero minimum:10000 name:ISS_CYCLES : Processor Cycles with instructions issued 11event:0x4 counters:4 um:zero minimum:10000 name:RET_UOP : Retired Micro-operatioins 12 13# Group 1, Load/Store 14event:0x10 counters:0 um:zero minimum:10000 name:GRP1_CYCLES : Processor Cycles 15event:0x11 counters:1 um:zero minimum:10000 name:GRP1_INST_RETIRED : Instructions retired 16event:0x12 counters:2 um:zero minimum:1000 name:GRP1_DCACHE_RD_MISS__NS : Dcache read misses NS 17event:0x13 counters:3 um:zero minimum:500 name:GRP1_MRB_LD_MISS_L2__NS : Load misses filling from memory 18event:0x14 counters:4 um:zero minimum:500 name:GRP1_MRB_ST_MISS_ALLOC__NS : Store misses in L1D and allocates an MRB entry 19event:0x15 counters:5 um:zero minimum:500 name:GRP1_TLB_MISS_D__NS : TLB misses NS (D- only) 20 21# Group 2, Frontend 22event:0x20 counters:0 um:zero minimum:10000 name:GRP2_CYCLES : Processor Cycles 23event:0x21 counters:1 um:zero minimum:10000 name:GRP2_INST_RETIRED : Instructions retired 24event:0x22 counters:2 um:zero minimum:2000 name:GRP2_FETCH_REQ : Demand fetch requests made to the Icache 25event:0x23 counters:3 um:zero minimum:500 name:GRP2_ICACHE_MISS_DEM__NS : Demand fetch requests missing in the Icache 26event:0x24 counters:4 um:zero minimum:500 name:GRP2_ICACHE_MISS_ALL : Demand and spec fetch requests missing in the Icache 27event:0x25 counters:5 um:zero minimum:2000 name:GRP2_ICACHE_ACC : Icache accesses 28 29# Group 3, Branches 30event:0x30 counters:0 um:zero minimum:10000 name:GRP3_CYCLES : Processor Cycles 31event:0x31 counters:1 um:zero minimum:10000 name:GRP3_INST_RETIRED : Instructions retired 32event:0x32 counters:2 um:zero minimum:500 name:GRP3_NXT_LINE_MISPRED__NS : Next fetch address mispredict 33event:0x33 counters:3 um:zero minimum:500 name:GRP3_DIRN_MISPRED__NS : Branch direction mispredict 34event:0x34 counters:4 um:zero minimum:500 name:GRP3_TGT_ADDR_MISPRED__NS : Branch target address mispredict 35event:0x35 counters:5 um:zero minimum:2000 name:GRP3_BRA_TAKEN__NS : Taken branches 36 37# Group 4, Translation 38event:0x40 counters:0 um:zero minimum:10000 name:GRP4_CYCLES : Processor Cycles 39event:0x41 counters:1 um:zero minimum:10000 name:GRP4_INST_RETIRED : Instructions retired 40event:0x42 counters:2 um:zero minimum:500 name:GRP4_TLB_MISS_D__NS : TLB Misses (D-) 41event:0x43 counters:3 um:zero minimum:500 name:GRP4_TLB_MISS_I__NS : TLB MIsses (I-) 42event:0x44 counters:4 um:zero minimum:500 name:GRP4_DERAT_MISS__NS : DERAT Misses 43event:0x45 counters:5 um:zero minimum:500 name:GRP4_IERAT_MISS__NS : IERAT Misses 44 45# Group 5, Memory 46event:0x50 counters:0 um:zero minimum:10000 name:GRP5_CYCLES : Processor Cycles 47event:0x51 counters:1 um:zero minimum:10000 name:GRP5_INST_RETIRED : Instructions retired 48event:0x52 counters:2 um:zero minimum:500 name:GRP5_DCACHE_RD_MISS__NS : Dcache read misses NS 49event:0x53 counters:3 um:zero minimum:500 name:GRP5_MRB_LD_MISS_L2__NS : Load misses filling from memory 50event:0x54 counters:4 um:zero minimum:500 name:GRP5_DCACHE_VIC : Dcache line evicted (snoops not included) 51event:0x55 counters:5 um:zero minimum:500 name:GRP5_MRB_ST_MISS_ALLOC__NS : Store misses in L1D and allocates an MRB entry 52 53