atomic-inline.h revision 62af8f258367c68b346f691387495284973f681c 
1/*
2 * Copyright (C) 2010 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ANDROID_CUTILS_ATOMIC_INLINE_H
18#define ANDROID_CUTILS_ATOMIC_INLINE_H
19
20/*
21 * Inline declarations and macros for some special-purpose atomic
22 * operations.  These are intended for rare circumstances where a
23 * memory barrier needs to be issued inline rather than as a function
24 * call.
25 *
26 * Most code should not use these.
27 *
28 * Anything that does include this file must set ANDROID_SMP to either
29 * 0 or 1, indicating compilation for UP or SMP, respectively.
30 */
31
32#if !defined(ANDROID_SMP)
33# error "Must define ANDROID_SMP before including atomic-inline.h"
34#endif
35
36#ifdef __cplusplus
37extern "C" {
38#endif
39
40/*
41 * Define the full memory barrier for an SMP system.  This is
42 * platform-specific.
43 */
44
45#ifdef __arm__
46#include <machine/cpu-features.h>
47
48/*
49 * For ARMv6K we need to issue a specific MCR instead of the DMB, since
50 * that wasn't added until v7.  For anything older, SMP isn't relevant.
51 * Since we don't have an ARMv6K to test with, we're not going to deal
52 * with that now.
53 *
54 * The DMB instruction is found in the ARM and Thumb2 instruction sets.
55 * This will fail on plain 16-bit Thumb.
56 */
57#if defined(__ARM_HAVE_DMB)
58# define __android_membar_full_smp() \
59    do { __asm__ __volatile__ ("dmb" ::: "memory"); } while (0)
60#else
61# define __android_membar_full_smp()  ARM_SMP_defined_but_no_DMB()
62#endif
63
64#elif defined(__i386__) || defined(__x86_64__)
65/*
66 * For recent x86, we can use the SSE2 mfence instruction.
67 */
68# define __android_membar_full_smp() \
69    do { __asm__ __volatile__ ("mfence" ::: "memory"); } while (0)
70
71#else
72/*
73 * Implementation not defined for this platform.  Hopefully we're building
74 * in uniprocessor mode.
75 */
76# define __android_membar_full_smp()  SMP_barrier_not_defined_for_platform()
77#endif
78
79
80/*
81 * Full barrier.  On uniprocessors this is just a compiler reorder barrier,
82 * which ensures that the statements appearing above the barrier in the C/C++
83 * code will be issued after the statements appearing below the barrier.
84 *
85 * For SMP this also includes a memory barrier instruction.  On an ARM
86 * CPU this means that the current core will flush pending writes, wait
87 * for pending reads to complete, and discard any cached reads that could
88 * be stale.  Other CPUs may do less, but the end result is equivalent.
89 */
90#if ANDROID_SMP != 0
91# define android_membar_full() __android_membar_full_smp()
92#else
93# define android_membar_full() \
94    do { __asm__ __volatile__ ("" ::: "memory"); } while (0)
95#endif
96
97#ifdef __cplusplus
98} // extern "C"
99#endif
100
101#endif // ANDROID_CUTILS_ATOMIC_INLINE_H
102