Lines Matching refs:outb
854 static void outb();
1162 outb(port, val)
1430 outb(base_port + UART_THR, data);
1464 if (action & BIOS_PRINTF_DEBUG) outb(DEBUG_PORT, c);
1465 if (action & BIOS_PRINTF_INFO) outb(INFO_PORT, c);
1641 outb(PANIC_PORT2, 0x00);
1754 while ( (inb(0x64) & 0x02) && (--max>0)) outb(0x80, 0x00);
1759 outb(0x80, 0x00);
1773 outb(0x64, 0xaa);
1777 while ( (inb(0x64) & 0x02) && (--max>0)) outb(0x80, 0x00);
1782 while ( ((inb(0x64) & 0x01) == 0) && (--max>0) ) outb(0x80, 0x01);
1791 outb(0x64,0xab);
1795 while ((inb(0x64) & 0x02) && (--max>0)) outb(0x80, 0x10);
1800 while ( ((inb(0x64) & 0x01) == 0) && (--max>0) ) outb(0x80, 0x11);
1810 outb(0x64,0xae);
1811 outb(0x64,0xa8);
1815 outb(0x60, 0xff);
1819 while ((inb(0x64) & 0x02) && (--max>0)) outb(0x80, 0x20);
1824 while ( ((inb(0x64) & 0x01) == 0) && (--max>0) ) outb(0x80, 0x21);
1834 while ( ((inb(0x64) & 0x01) == 0) && (--max>0) ) outb(0x80, 0x31);
1842 outb(0x60, 0xf5);
1846 while ((inb(0x64) & 0x02) && (--max>0)) outb(0x80, 0x40);
1851 while ( ((inb(0x64) & 0x01) == 0) && (--max>0) ) outb(0x80, 0x41);
1860 outb(0x64, 0x60);
1864 while ((inb(0x64) & 0x02) && (--max>0)) outb(0x80, 0x50);
1868 outb(0x60, 0x61);
1872 while ((inb(0x64) & 0x02) && (--max>0)) outb(0x80, 0x60);
1876 outb(0x60, 0xf4);
1880 while ((inb(0x64) & 0x02) && (--max>0)) outb(0x80, 0x70);
1885 while ( ((inb(0x64) & 0x01) == 0) && (--max>0) ) outb(0x80, 0x71);
1893 outb(0x80, 0x77);
2169 outb(BX_DEBUG_PORT+UART_LCR, 0x03); /* setup for serial logging: 8N1 */
2187 outb(0x92, oldval | 0x02);
2189 outb(0x92, oldval & 0xfd);
2197 outb(0xfedc, 0x01);
2203 outb(0xfedc, 0x00);
2527 outb(iobase2+ATA_CB_DC, ATA_CB_DC_HD15 | ATA_CB_DC_NIEN);
2530 outb(iobase1+ATA_CB_DH, slave ? ATA_CB_DH_DEV1 : ATA_CB_DH_DEV0);
2531 outb(iobase1+ATA_CB_SC, 0x55);
2532 outb(iobase1+ATA_CB_SN, 0xaa);
2533 outb(iobase1+ATA_CB_SC, 0xaa);
2534 outb(iobase1+ATA_CB_SN, 0x55);
2535 outb(iobase1+ATA_CB_SC, 0x55);
2536 outb(iobase1+ATA_CB_SN, 0xaa);
2549 outb(iobase1+ATA_CB_DH, slave ? ATA_CB_DH_DEV1 : ATA_CB_DH_DEV0);
2802 outb(iobase2+ATA_CB_DC, ATA_CB_DC_HD15 | ATA_CB_DC_NIEN | ATA_CB_DC_SRST);
2808 outb(iobase2+ATA_CB_DC, ATA_CB_DC_HD15 | ATA_CB_DC_NIEN);
2815 outb(iobase1+ATA_CB_DH, slave?ATA_CB_DH_DEV1:ATA_CB_DH_DEV0);
2831 outb(iobase2+ATA_CB_DC, ATA_CB_DC_HD15);
2880 outb(iobase2 + ATA_CB_DC, ATA_CB_DC_HD15 | ATA_CB_DC_NIEN);
2885 outb(iobase1 + ATA_CB_FR, 0x00);
2886 outb(iobase1 + ATA_CB_SC, (count >> 8) & 0xff);
2887 outb(iobase1 + ATA_CB_SN, lba_low >> 24);
2888 outb(iobase1 + ATA_CB_CL, lba_high & 0xff);
2889 outb(iobase1 + ATA_CB_CH, lba_high >> 8);
2899 outb(iobase1 + ATA_CB_FR, 0x00);
2900 outb(iobase1 + ATA_CB_SC, count);
2901 outb(iobase1 + ATA_CB_SN, sector);
2902 outb(iobase1 + ATA_CB_CL, cylinder & 0x00ff);
2903 outb(iobase1 + ATA_CB_CH, cylinder >> 8);
2904 outb(iobase1 + ATA_CB_DH, (slave ? ATA_CB_DH_DEV1 : ATA_CB_DH_DEV0) | (Bit8u) head );
2905 outb(iobase1 + ATA_CB_CMD, command);
2988 outb(iobase2+ATA_CB_DC, ATA_CB_DC_HD15);
3031 outb(iobase2 + ATA_CB_DC, ATA_CB_DC_HD15 | ATA_CB_DC_NIEN);
3036 outb(iobase1 + ATA_CB_FR, 0x00);
3037 outb(iobase1 + ATA_CB_SC, (count >> 8) & 0xff);
3038 outb(iobase1 + ATA_CB_SN, lba_low >> 24);
3039 outb(iobase1 + ATA_CB_CL, lba_high & 0xff);
3040 outb(iobase1 + ATA_CB_CH, lba_high >> 8);
3050 outb(iobase1 + ATA_CB_FR, 0x00);
3051 outb(iobase1 + ATA_CB_SC, count);
3052 outb(iobase1 + ATA_CB_SN, sector);
3053 outb(iobase1 + ATA_CB_CL, cylinder & 0x00ff);
3054 outb(iobase1 + ATA_CB_CH, cylinder >> 8);
3055 outb(iobase1 + ATA_CB_DH, (slave ? ATA_CB_DH_DEV1 : ATA_CB_DH_DEV0) | (Bit8u) head );
3056 outb(iobase1 + ATA_CB_CMD, command);
3140 outb(iobase2+ATA_CB_DC, ATA_CB_DC_HD15);
3197 outb(iobase2 + ATA_CB_DC, ATA_CB_DC_HD15 | ATA_CB_DC_NIEN);
3198 outb(iobase1 + ATA_CB_FR, 0x00);
3199 outb(iobase1 + ATA_CB_SC, 0x00);
3200 outb(iobase1 + ATA_CB_SN, 0x00);
3201 outb(iobase1 + ATA_CB_CL, 0xfff0 & 0x00ff);
3202 outb(iobase1 + ATA_CB_CH, 0xfff0 >> 8);
3203 outb(iobase1 + ATA_CB_DH, slave ? ATA_CB_DH_DEV1 : ATA_CB_DH_DEV0);
3204 outb(iobase1 + ATA_CB_CMD, ATA_CMD_PACKET);
3417 outb(iobase2+ATA_CB_DC, ATA_CB_DC_HD15);
3757 outb(addr+3, inb(addr+3) | 0x80);
3759 outb(addr, 0x17);
3760 outb(addr+1, 0x04);
3763 outb(addr, val16 & 0xFF);
3764 outb(addr+1, val16 >> 8);
3766 outb(addr+3, regs.u.r8.al & 0x1F);
3780 if (timeout) outb(addr, regs.u.r8.al);
3894 outb( 0xA1, irqDisable & 0xFE );
4683 outb(0x60, 0xed);
4684 while ((inb(0x64) & 0x01) == 0) outb(0x80, 0x21);
4688 outb(0x60, led_flags & 0x07);
4689 while ((inb(0x64) & 0x01) == 0) outb(0x80, 0x21);
4751 outb(0x60, 0xf2);
4754 while ( ((inb(0x64) & 0x01) == 0) && (--max>0) ) outb(0x80, 0x00);
4759 while ( ((inb(0x64) & 0x01) == 0) && (--max>0) ) outb(0x80, 0x00);
4866 outb(0x64, 0x20); // get command byte
4875 outb(0x64, 0x60); // write command byte
4876 outb(0x60, command_byte);
4888 outb(0x64, 0x20); // get command byte
4896 outb(0x64, 0x60); // write command byte
4897 outb(0x60, command_byte);
4909 outb(0x64, 0xD4);
4910 outb(0x60, sendbyte);
4938 outb(0x64, 0xD4);
4940 outb(0x64, 0x60); // write command byte
4941 outb(0x60, command_byte);
6425 outb(0x01f2, num_sectors);
6432 outb(0x01f3, sector);
6433 outb(0x01f4, cylinder & 0x00ff);
6434 outb(0x01f5, cylinder >> 8);
6435 outb(0x01f6, 0xa0 | ((drive & 0x01)<<4) | (head & 0x0f));
6437 outb(0x01f7, 0x20);
6565 outb(0x01f2, num_sectors);
6573 outb(0x01f3, sector);
6574 outb(0x01f4, cylinder & 0x00ff);
6575 outb(0x01f5, cylinder >> 8);
6576 outb(0x01f6, 0xa0 | ((GET_ELDL() & 0x01)<<4) | (head & 0x0f));
6578 outb(0x01f7, 0x30);
6884 outb(0x03f2, val8 & ~0x04);
6885 outb(0x03f2, val8 | 0x04);
6911 outb(0x03f2, dor);
7091 outb(0x03f5, 0x07); // 07: Recalibrate
7092 outb(0x03f5, drive); // 0=drive0, 1=drive1
7268 outb(0x000a, 0x06);
7271 outb(0x000c, 0x00); // clear flip-flop
7272 outb(0x0004, base_address);
7273 outb(0x0004, base_address>>8);
7275 outb(0x000c, 0x00); // clear flip-flop
7276 outb(0x0005, base_count);
7277 outb(0x0005, base_count>>8);
7283 outb(0x000b, mode_register);
7287 outb(0x0081, page);
7290 outb(0x000a, 0x02); // unmask channel 2
7293 outb(0x000a, 0x02);
7301 outb(0x03f5, 0xe6); // e6: read normal data
7302 outb(0x03f5, (head << 2) | drive); // HD DR1 DR2
7303 outb(0x03f5, track);
7304 outb(0x03f5, head);
7305 outb(0x03f5, sector);
7306 outb(0x03f5, 2); // 512 byte sector size
7307 outb(0x03f5, sector + num_sectors - 1); // last sector to read on track
7308 outb(0x03f5, 0); // Gap length
7309 outb(0x03f5, 0xff); // Gap length
7409 outb(0x000a, 0x06);
7411 outb(0x000c, 0x00); // clear flip-flop
7412 outb(0x0004, base_address);
7413 outb(0x0004, base_address>>8);
7414 outb(0x000c, 0x00); // clear flip-flop
7415 outb(0x0005, base_count);
7416 outb(0x0005, base_count>>8);
7421 outb(0x000b, mode_register);
7424 outb(0x0081, page);
7427 outb(0x000a, 0x02);
7435 outb(0x03f5, 0xc5); // c5: write normal data
7436 outb(0x03f5, (head << 2) | drive); // HD DR1 DR2
7437 outb(0x03f5, track);
7438 outb(0x03f5, head);
7439 outb(0x03f5, sector);
7440 outb(0x03f5, 2); // 512 byte sector size
7441 outb(0x03f5, sector + num_sectors - 1); // last sector to write on track
7442 outb(0x03f5, 0); // Gap length
7443 outb(0x03f5, 0xff); // Gap length
7584 outb(0x000a, 0x06);
7585 outb(0x000c, 0x00); // clear flip-flop
7586 outb(0x0004, base_address);
7587 outb(0x0004, base_address>>8);
7588 outb(0x000c, 0x00); // clear flip-flop
7589 outb(0x0005, base_count);
7590 outb(0x0005, base_count>>8);
7593 outb(0x000b, mode_register);
7595 outb(0x0081, page);
7596 outb(0x000a, 0x02);
7602 outb(0x03f5, 0x4d); // 4d: format track
7603 outb(0x03f5, (head << 2) | drive); // HD DR1 DR2
7604 outb(0x03f5, 2); // 512 byte sector size
7605 outb(0x03f5, num_sectors); // number of sectors per track
7606 outb(0x03f5, 0); // Gap length
7607 outb(0x03f5, 0xf6); // Fill byte
7923 outb(0x03f2, DOR); // Digital Output Register
7947 outb(addr, regs.u.r8.al);
7949 outb(addr+2, val8 | 0x01); // send strobe
7953 outb(addr+2, val8 & ~0x01);
7960 outb(addr+2, val8 & ~0x04); // send init
7964 outb(addr+2, val8 | 0x04);
8309 outb(0xa1, inb(0xa1) & 0xfe); // enable IRQ 8