Searched defs:Opc (Results 1 - 25 of 76) sorted by relevance

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/external/llvm/lib/Target/Mips/
H A DMipsAnalyzeImmediate.h20 unsigned Opc, ImmOpnd; member in struct:llvm::MipsAnalyzeImmediate::Inst
21 Inst(unsigned Opc, unsigned ImmOpnd);
H A DMipsInstrInfo.cpp51 unsigned Opc = MI->getOpcode(); local
53 if ((Opc == Mips::LW) || (Opc == Mips::LW_P8) || (Opc == Mips::LD) ||
54 (Opc == Mips::LD_P8) || (Opc == Mips::LWC1) || (Opc == Mips::LWC1_P8) ||
55 (Opc == Mips::LDC1) || (Opc == Mips::LDC164) ||
56 (Opc
76 unsigned Opc = MI->getOpcode(); local
106 unsigned Opc = 0, ZeroReg = 0; local
190 unsigned Opc = 0; local
217 unsigned Opc = 0; local
248 GetAnalyzableBrOpc(unsigned Opc) argument
260 GetOppositeBranchOpc(unsigned Opc) argument
281 AnalyzeCondBr(const MachineInstr* Inst, unsigned Opc, MachineBasicBlock *&BB, SmallVectorImpl<MachineOperand>& Cond) argument
380 unsigned Opc = Cond[0].getImm(); local
[all...]
H A DMipsMCInstLower.cpp110 static void CreateMCInst(MCInst& Inst, unsigned Opc, const MCOperand& Opnd0, argument
113 Inst.setOpcode(Opc);
211 unsigned Opc = MI->getOpcode(); local
233 switch (Opc) {
H A DMipsAsmPrinter.cpp74 unsigned Opc = MI->getOpcode(); local
78 switch (Opc) {
/external/llvm/lib/Target/Hexagon/
H A DHexagonExpandPredSpillCode.cpp76 int Opc = MI->getOpcode(); local
77 if (Opc == Hexagon::STriw_pred) {
119 } else if (Opc == Hexagon::LDriw_pred) {
H A DHexagonSplitTFRCondSets.cpp84 int Opc = MI->getOpcode(); local
85 if (Opc == Hexagon::TFR_condset_rr) {
103 } else if (Opc == Hexagon::TFR_condset_ii) {
H A DHexagonCFGOptimizer.cpp53 static bool IsConditionalBranch(int Opc) { argument
54 return (Opc == Hexagon::JMP_c) || (Opc == Hexagon::JMP_cNot)
55 || (Opc == Hexagon::JMP_cdnPt) || (Opc == Hexagon::JMP_cdnNotPt);
59 static bool IsUnconditionalJump(int Opc) { argument
60 return (Opc == Hexagon::JMP);
106 int Opc = MI->getOpcode(); local
107 if (IsConditionalBranch(Opc)) {
/external/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h41 // Return the non-pre/post incrementing version of 'Opc'. Return 0
43 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
323 bool isUncondBranchOpcode(int Opc) { argument
324 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
328 bool isCondBranchOpcode(int Opc) { argument
329 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc
333 isJumpTableBranchOpcode(int Opc) argument
339 isIndirectBranchOpcode(int Opc) argument
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H A DThumb1RegisterInfo.cpp128 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); local
130 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
131 if (Opc != ARM::tADDhirr)
142 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes, argument
147 if (Opc == ARM::tADDrSPi) {
181 int Opc = 0;
189 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
202 Opc = ARM::tADDrSPi;
211 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
216 Opc
327 unsigned Opc = Old->getOpcode(); local
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/external/llvm/lib/Target/MSP430/
H A DMSP430FrameLowering.cpp142 unsigned Opc = PI->getOpcode(); local
143 if (Opc != MSP430::POP16r && !PI->isTerminator())
H A DMSP430InstrInfo.cpp92 unsigned Opc; local
94 Opc = MSP430::MOV16rr;
96 Opc = MSP430::MOV8rr;
100 BuildMI(MBB, I, DL, get(Opc), DestReg)
H A DMSP430ISelDAGToDAG.cpp364 unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8); local
369 CurDAG->SelectNodeTo(Op, Opc,
/external/llvm/lib/Target/MBlaze/
H A DMBlazeISelDAGToDAG.cpp101 unsigned Opc = N->getOpcode(); local
102 if (Opc != ISD::Constant)
213 unsigned Opc = MBlaze::ADDIK; local
215 return CurDAG->SelectNodeTo(Node, Opc, VT, TFI, imm);
216 return CurDAG->getMachineNode(Opc, dl, VT, TFI, imm);
H A DMBlazeInstrInfo.cpp196 unsigned Opc = MBlaze::BRID; local
198 Opc = (unsigned)Cond[0].getImm();
202 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
204 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
208 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
H A DMBlazeInstrInfo.h144 inline static bool isUncondBranchOpcode(int Opc) { argument
145 switch (Opc) {
155 inline static bool isCondBranchOpcode(int Opc) { argument
156 switch (Opc) {
/external/llvm/lib/Target/X86/
H A DX86FrameLowering.cpp107 unsigned Opc = MBBI->getOpcode(); local
108 switch (Opc) {
152 unsigned Opc;
154 Opc = getLEArOpcode(Is64Bit);
156 Opc = isSub
171 Opc = isSub
174 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
186 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
189 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
209 unsigned Opc
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H A DX86RegisterInfo.cpp430 unsigned Opc = getADDriOpcode(Is64Bit, Amount); local
431 New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
451 unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt); local
452 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
486 unsigned Opc = MI.getOpcode();
487 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
/external/llvm/include/llvm/Support/
H A DConstantFolder.h97 Constant *CreateBinOp(Instruction::BinaryOps Opc, argument
99 return ConstantExpr::get(Opc, LHS, RHS);
H A DTargetFolder.h109 Constant *CreateBinOp(Instruction::BinaryOps Opc, argument
111 return Fold(ConstantExpr::get(Opc, LHS, RHS));
H A DNoFolder.h147 Instruction *CreateBinOp(Instruction::BinaryOps Opc, argument
149 return BinaryOperator::Create(Opc, LHS, RHS);
/external/llvm/lib/MC/
H A DMCExpr.cpp146 const MCBinaryExpr *MCBinaryExpr::Create(Opcode Opc, const MCExpr *LHS, argument
148 return new (Ctx) MCBinaryExpr(Opc, LHS, RHS);
151 const MCUnaryExpr *MCUnaryExpr::Create(Opcode Opc, const MCExpr *Expr, argument
153 return new (Ctx) MCUnaryExpr(Opc, Expr);
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAddressingModes.h407 static inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO, argument
410 bool isSub = Opc == sub;
442 static inline unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset,
444 bool isSub = Opc == sub;
492 static inline unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset) {
493 bool isSub = Opc == sub;
/external/llvm/lib/Target/CellSPU/
H A DSPUInstrInfo.cpp430 unsigned Opc; //! The incoming opcode member in struct:__anon7574
443 unsigned Opc = unsigned(Cond[0].getImm()); local
446 if (revconds[i].Opc == Opc) {
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp325 unsigned Opc; local
327 Opc = PPC::OR;
329 Opc = PPC::OR8;
331 Opc = PPC::FMR;
333 Opc = PPC::MCRF;
335 Opc = PPC::VOR;
337 Opc = PPC::CROR;
341 const MCInstrDesc &MCID = get(Opc);
/external/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.cpp290 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); local
291 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
299 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); local
300 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())

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