Searched defs:Order (Results 1 - 23 of 23) sorted by relevance

/external/icu4c/test/intltest/
H A Dtscoll.h26 struct Order struct in class:IntlTestCollator
51 Order *getOrders(CollationElementIterator &iter, int32_t &orderLength);
H A Dssearch.cpp674 struct Order struct
690 const Order *get(int32_t index) const;
699 Order *list;
707 list = new Order[listMax];
732 list = new Order[listMax];
763 Order *newList = new Order[listMax];
765 uprv_memcpy(newList, list, listSize * sizeof(Order));
777 const Order *OrderList::get(int32_t index) const
788 const Order *orde
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/external/aac/libAACdec/src/
H A Daacdec_tns.h113 UCHAR Order; member in struct:__anon24
/external/llvm/lib/CodeGen/
H A DAllocationOrder.cpp1 //===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
44 ArrayRef<uint16_t> Order = local
47 if (Order.empty())
52 unsigned *P = new unsigned[Order.size()];
54 for (unsigned i = 0; i != Order.size(); ++i)
55 if (!RCI.isReserved(Order[i]))
56 *P++ = Order[i];
H A DRegisterClassInfo.h32 OwningArrayPtr<unsigned> Order; member in struct:llvm::RegisterClassInfo::RCInfo
36 return makeArrayRef(Order.get(), NumRegs);
H A DCriticalAntiDepBreaker.cpp404 ArrayRef<unsigned> Order = RegClassInfo.getOrder(RC); local
405 for (unsigned i = 0; i != Order.size(); ++i) {
406 unsigned NewReg = Order[i];
H A DRegAllocBasic.cpp246 ArrayRef<unsigned> Order = local
248 for (ArrayRef<unsigned>::iterator I = Order.begin(), E = Order.end(); I != E;
H A DRegAllocGreedy.cpp449 AllocationOrder &Order,
451 Order.rewind();
453 while ((PhysReg = Order.next())) {
459 if (!PhysReg || Order.isHint(PhysReg))
467 if (Order.isHint(Hint) && !clobberedByRegMask(Hint)) {
485 unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost);
618 /// @param Order Physregs to try.
621 AllocationOrder &Order,
637 Order.rewind();
638 while (unsigned PhysReg = Order
448 tryAssign(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<LiveInterval*> &NewVRegs) argument
620 tryEvict(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<LiveInterval*> &NewVRegs, unsigned CostPerUseLimit) argument
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/external/llvm/lib/Target/
H A DTargetRegisterInfo.cpp74 ArrayRef<uint16_t> Order = RC->getRawAllocationOrder(MF); local
75 for (unsigned i = 0; i != Order.size(); ++i)
76 R.set(Order[i]);
/external/llvm/lib/CodeGen/SelectionDAG/
H A DSDNodeDbgValue.h50 unsigned Order; member in class:llvm::SDDbgValue
55 unsigned O) : mdPtr(mdP), Offset(off), DL(dl), Order(O),
65 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) {
72 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) {
103 unsigned getOrder() { return Order; }
H A DSelectionDAGDumper.cpp480 if (unsigned Order = G->GetOrdering(this))
481 OS << " [ORD=" << Order << ']'; local
H A DScheduleDAGSDNodes.cpp456 const SDep &dep = SDep(OpSU, isChain ? SDep::Order : SDep::Data,
670 unsigned Order) {
683 if (!Order || DVOrder == ++Order) {
702 unsigned Order = DAG->GetOrdering(N); local
703 if (!Order || !Seen.insert(Order)) {
713 Orders.push_back(std::make_pair(Order, (MachineInstr*)0));
717 Orders.push_back(std::make_pair(Order, prior(Emitter.getInsertPos())));
718 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order);
666 ProcessSDDbgValues(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter, SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders, DenseMap<SDValue, unsigned> &VRBaseMap, unsigned Order) argument
832 unsigned Order = Orders[i].first; local
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H A DSelectionDAG.cpp5634 void SelectionDAG::AssignOrdering(const SDNode *SD, unsigned Order) { argument
5636 Ordering->add(SD, Order);
H A DSelectionDAGBuilder.cpp3335 static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order, argument
3342 if (Order == AcquireRelease || Order == SequentiallyConsistent)
3343 Order = Release;
3344 else if (Order == Acquire || Order == Monotonic)
3347 if (Order == AcquireRelease)
3348 Order = Acquire;
3349 else if (Order == Release || Order
3361 AtomicOrdering Order = I.getOrdering(); local
3408 AtomicOrdering Order = I.getOrdering(); local
3448 AtomicOrdering Order = I.getOrdering(); local
3478 AtomicOrdering Order = I.getOrdering(); local
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/external/llvm/lib/Support/
H A DDwarf.cpp606 const char *llvm::dwarf::ArrayOrderString(unsigned Order) { argument
607 switch (Order) {
/external/llvm/lib/MC/
H A DMachObjectWriter.cpp532 const SmallVectorImpl<MCSectionData*> &Order = Layout.getSectionOrder(); local
533 for (int i = 0, n = Order.size(); i != n ; ++i) {
534 const MCSectionData *SD = Order[i];
/external/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp537 ArrayRef<Record*> Order = RC.getOrder(); local
546 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
547 Record *Reg = Order[i];
556 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
557 Record *Reg = Order[i];
727 ArrayRef<Record*> Order = RC.getOrder(); local
730 AllocatableRegs.insert(Order.begin(), Order.end());
844 << " const ArrayRef<uint16_t> Order[] = {\n"
853 << ");\n return Order[Selec
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H A DCodeGenRegisters.cpp494 SetTheory::RecSet Order; local
496 RegBank.getSets().evaluate(AltOrders->getElement(i), Order);
497 Orders[1 + i].append(Order.begin(), Order.end());
499 while (!Order.empty()) {
500 CodeGenRegister *Reg = RegBank.getReg(Order.back());
501 Order.pop_back();
637 // Order by descending set size. Note that the classes' allocation order may
644 // Order by ascending spill size.
650 // Order b
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/external/llvm/include/llvm/CodeGen/
H A DScheduleDAG.h52 Order ///< Any other ordering dependency. enumerator in enum:llvm::SDep::Kind
67 /// Order - Additional information about Order dependencies.
81 } Order; member in union:llvm::SDep::__anon7148
107 assert(!isMustAlias && "isMustAlias only applies with SDep::Order!");
108 assert(!isArtificial && "isArtificial only applies with SDep::Order!");
111 case Order:
113 Contents.Order.isNormalMemory = isNormalMemory;
114 Contents.Order.isMustAlias = isMustAlias;
115 Contents.Order
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/external/clang/lib/CodeGen/
H A DCGBuiltin.cpp1005 Value *Order = EmitScalarExpr(E->getArg(1)); local
1006 if (isa<llvm::ConstantInt>(Order)) {
1007 int ord = cast<llvm::ConstantInt>(Order)->getZExtValue();
1056 Order = Builder.CreateIntCast(Order, Builder.getInt32Ty(), false);
1057 llvm::SwitchInst *SI = Builder.CreateSwitch(Order, BBs[0]);
1092 Value *Order = EmitScalarExpr(E->getArg(1)); local
1093 if (isa<llvm::ConstantInt>(Order)) {
1094 int ord = cast<llvm::ConstantInt>(Order)->getZExtValue();
1123 Order
1152 Value *Order = EmitScalarExpr(E->getArg(0)); local
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H A DCGExpr.cpp2701 uint64_t Size, unsigned Align, llvm::AtomicOrdering Order) {
2720 CGF.Builder.CreateAtomicCmpXchg(Ptr, LoadVal1, LoadVal2, Order);
2733 Load->setAtomic(Order);
2748 Store->setAtomic(Order);
2811 CGF.Builder.CreateAtomicRMW(Op, Ptr, LoadVal1, Order);
2859 llvm::Value *Ptr, *Order, *OrderFail = 0, *Val1 = 0, *Val2 = 0; local
2883 Order = EmitScalarExpr(E->getOrder());
2994 Args.add(RValue::get(Order),
2996 Order = OrderFail;
3037 Args.add(RValue::get(Order),
2699 EmitAtomicOp(CodeGenFunction &CGF, AtomicExpr *E, llvm::Value *Dest, llvm::Value *Ptr, llvm::Value *Val1, llvm::Value *Val2, uint64_t Size, unsigned Align, llvm::AtomicOrdering Order) argument
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/external/llvm/lib/VMCore/
H A DInstructions.cpp970 unsigned Align, AtomicOrdering Order,
977 setAtomic(Order, SynchScope);
983 unsigned Align, AtomicOrdering Order,
990 setAtomic(Order, SynchScope);
1117 unsigned Align, AtomicOrdering Order,
1128 setAtomic(Order, SynchScope);
1161 unsigned Align, AtomicOrdering Order,
1172 setAtomic(Order, SynchScope);
969 LoadInst(Value *Ptr, const Twine &Name, bool isVolatile, unsigned Align, AtomicOrdering Order, SynchronizationScope SynchScope, Instruction *InsertBef) argument
982 LoadInst(Value *Ptr, const Twine &Name, bool isVolatile, unsigned Align, AtomicOrdering Order, SynchronizationScope SynchScope, BasicBlock *InsertAE) argument
1116 StoreInst(Value *val, Value *addr, bool isVolatile, unsigned Align, AtomicOrdering Order, SynchronizationScope SynchScope, Instruction *InsertBefore) argument
1160 StoreInst(Value *val, Value *addr, bool isVolatile, unsigned Align, AtomicOrdering Order, SynchronizationScope SynchScope, BasicBlock *InsertAtEnd) argument
/external/mesa3d/src/mesa/main/
H A Dmtypes.h1666 GLuint Order; /**< Number of control points */ member in struct:gl_1d_map

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