/external/llvm/lib/Target/ARM/ |
H A D | Thumb2RegisterInfo.cpp | 38 unsigned DestReg, unsigned SubIdx, 49 .addReg(DestReg, getDefRegState(true), SubIdx) 35 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
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H A D | Thumb1RegisterInfo.cpp | 67 unsigned DestReg, unsigned SubIdx, 78 .addReg(DestReg, getDefRegState(true), SubIdx) 64 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
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H A D | ARMBaseRegisterInfo.cpp | 693 unsigned DestReg, unsigned SubIdx, int Val, 703 .addReg(DestReg, getDefRegState(true), SubIdx) 690 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
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H A D | ARMISelDAGToDAG.cpp | 2069 unsigned SubIdx = ARM::dsub_0; local 2072 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
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H A D | ARMBaseInstrInfo.cpp | 733 unsigned Reg, unsigned SubIdx, unsigned State, 735 if (!SubIdx) 739 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); 740 return MIB.addReg(Reg, State, SubIdx); 1166 unsigned DestReg, unsigned SubIdx, 1173 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 732 AddDReg(MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) argument 1164 reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const argument
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/external/llvm/lib/CodeGen/ |
H A D | ExpandPostRAPseudos.cpp | 105 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?"); 106 unsigned SubIdx = MI->getOperand(3).getImm(); local 108 assert(SubIdx != 0 && "Invalid index for insert_subreg"); 109 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); 125 MI->RemoveOperand(3); // SubIdx
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H A D | RegisterCoalescer.h | 42 unsigned SubIdx; member in class:llvm::CoalescerPair 60 : TII(tii), TRI(tri), DstReg(0), SrcReg(0), SubIdx(0), 68 /// because DstReg is a physical register, or SubIdx is set. 99 unsigned getSubIdx() const { return SubIdx; }
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H A D | MachineCopyPropagation.cpp | 129 unsigned SubIdx = TRI->getSubRegIndex(SrcSrc, Def); local 130 if (!SubIdx) 132 return SubIdx == TRI->getSubRegIndex(SrcDef, Src);
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H A D | PeepholeOptimizer.cpp | 131 unsigned SrcReg, DstReg, SubIdx; local 132 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx)) 247 .addReg(DstReg, 0, SubIdx);
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H A D | TargetInstrInfoImpl.cpp | 234 unsigned SubIdx, 238 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI); 231 reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const argument
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H A D | LiveDebugVariables.cpp | 250 /// renameRegister - Update locations to rewrite OldReg as NewReg:SubIdx. 251 void renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx, 337 /// renameRegister - Replace all references to OldReg with NewReg:SubIdx. 338 void renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx); 701 renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx, argument 711 Loc.substVirtReg(NewReg, SubIdx, *TRI); 717 renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx) { argument 727 UV->renameRegister(OldReg, NewReg, SubIdx, TRI); 733 renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx) { argument 735 static_cast<LDVImpl*>(pImpl)->renameRegister(OldReg, NewReg, SubIdx); [all...] |
H A D | MachineVerifier.cpp | 668 unsigned SubIdx = MO->getSubReg(); local 671 if (SubIdx) { 685 if (SubIdx) { 687 TRI->getSubClassWithSubReg(RC, SubIdx); 691 << " does not support subreg index " << SubIdx << "\n"; 697 << " does not fully support subreg index " << SubIdx << "\n"; 702 if (SubIdx) { 709 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
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H A D | MachineInstr.cpp | 118 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx, argument 121 if (SubIdx && getSubReg()) 122 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); 124 if (SubIdx) 125 setSubReg(SubIdx); 1234 unsigned SubIdx, 1237 if (SubIdx) 1238 ToReg = RegInfo.getSubReg(ToReg, SubIdx); 1250 MO.substVirtReg(ToReg, SubIdx, RegInf 1232 substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo) argument [all...] |
H A D | RegisterCoalescer.cpp | 236 SrcReg = DstReg = SubIdx = 0; 312 "Cannot have a physical SubIdx"); 315 SubIdx = DstSub; 320 if (SubIdx || TargetRegisterInfo::isPhysicalRegister(DstReg)) 346 assert(!SubIdx && "Inconsistent CoalescerPair state."); 360 return compose(TRI, SubIdx, SrcSub) == DstSub; 915 unsigned SubIdx = CP.getSubIdx(); local 918 LDV->renameRegister(SrcReg, DstReg, SubIdx); 948 if (SubIdx && !Reads) 954 MO.substVirtReg(DstReg, SubIdx, *TR [all...] |
H A D | TwoAddressInstructionPass.cpp | 1603 unsigned SubIdx = mi->getOperand(3).getImm(); local 1606 mi->getOperand(0).setSubReg(SubIdx); 1637 unsigned DstReg, unsigned SubIdx, 1644 MO.substVirtReg(DstReg, SubIdx, TRI); 1837 unsigned SubIdx = MI->getOperand(i+1).getImm(); local 1862 MRI->getRegClass(SrcReg), SubIdx)) { 1891 .addReg(DstReg, RegState::Define, SubIdx) 1903 unsigned SubIdx = MI->getOperand(i+1).getImm(); local 1904 UpdateRegSequenceSrcs(SrcReg, DstReg, SubIdx, MRI, *TRI); 1636 UpdateRegSequenceSrcs(unsigned SrcReg, unsigned DstReg, unsigned SubIdx, MachineRegisterInfo *MRI, const TargetRegisterInfo &TRI) argument
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/external/llvm/lib/Target/ |
H A D | TargetRegisterInfo.cpp | 41 if (SubIdx) { 43 OS << ':' << TRI->getSubRegIndexName(SubIdx); 45 OS << ":sub(" << SubIdx << ')'; local
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/external/llvm/utils/TableGen/ |
H A D | CodeGenRegisters.h | 236 // registers have a SubIdx sub-register. 238 getSubClassWithSubReg(CodeGenSubRegIndex *SubIdx) const { 239 return SubClassWithSubReg.lookup(SubIdx); 242 void setSubClassWithSubReg(CodeGenSubRegIndex *SubIdx, argument 244 SubClassWithSubReg[SubIdx] = SubRC; 248 // containing only SubIdx super-registers of this class. 249 void getSuperRegClasses(CodeGenSubRegIndex *SubIdx, BitVector &Out) const; 252 void addSuperRegClass(CodeGenSubRegIndex *SubIdx, argument 254 SuperRegClasses[SubIdx].insert(SuperRC);
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H A D | AsmMatcherEmitter.cpp | 1491 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second; local 1498 int SrcOperand = FindAsmOperand(Name, SubIdx); 1503 unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1);
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H A D | CodeGenRegisters.cpp | 714 CodeGenRegisterClass::getSuperRegClasses(CodeGenSubRegIndex *SubIdx, argument 718 FindI = SuperRegClasses.find(SubIdx); 1170 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size(); 1171 SubIdx != EndIdx; ++SubIdx) { 1172 const RegUnitSet &SubSet = RegUnitSets[SubIdx]; 1175 if (SuperIdx == SubIdx) 1185 SuperSetIDs.push_back(SubIdx); 1424 // Make sure that the set of registers in RC with a given SubIdx sub-register 1445 CodeGenSubRegIndex *SubIdx local 1477 CodeGenSubRegIndex *SubIdx = SubRegIndices[sri]; local [all...] |
/external/llvm/include/llvm/Target/ |
H A D | TargetRegisterInfo.h | 324 const char *getSubRegIndexName(unsigned SubIdx) const { 325 assert(SubIdx && "This is not a subregister index"); 326 return SubRegIndexNames[SubIdx-1]; 394 /// Reg so its sub-register of index SubIdx is Reg. 395 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, argument 397 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC); 733 unsigned SubIdx; member in class:llvm::PrintReg 736 : TRI(tri), Reg(reg), SubIdx(subidx) {}
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.cpp | 1145 unsigned &SubIdx) const { 1178 SubIdx = X86::sub_8bit; 1184 SubIdx = X86::sub_16bit; 1188 SubIdx = X86::sub_32bit; 1495 unsigned DestReg, unsigned SubIdx, 1532 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 1493 reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const argument
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