Searched defs:SubRegs (Results 1 - 5 of 5) sorted by relevance

/external/llvm/lib/Target/Mips/
H A DMipsFrameLowering.cpp221 const uint16_t *SubRegs = RegInfo->getSubRegisters(Reg); local
224 MachineLocation SrcML0(*SubRegs);
225 MachineLocation SrcML1(*(SubRegs + 1));
/external/llvm/include/llvm/MC/
H A DMCRegisterInfo.h102 /// alias EAX. The SubRegs field is a zero terminated array of registers that
111 uint32_t SubRegs; // Sub-register set, described above member in struct:llvm::MCRegisterDesc
258 return RegLists + get(RegNo).SubRegs;
/external/llvm/utils/TableGen/
H A DCodeGenRegisters.h109 return SubRegs;
158 SubRegMap SubRegs; member in struct:llvm::CodeGenRegister
H A DCodeGenRegisters.cpp154 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
175 return SubRegs;
178 std::vector<Record*> SubList = TheDef->getValueAsListOfDefs("SubRegs");
182 " SubRegIndices doesn't match SubRegs");
190 if (!SubRegs.insert(std::make_pair(Idx, SR)).second)
211 if (!SubRegs.insert(*SI).second)
227 CodeGenRegister *SR = SubRegs[Idx];
239 if (SubRegs.count(I->second) || !Orphans.erase(SRI->second))
242 SubRegs
363 ListInit *SubRegs = Def->getValueAsListInit("SubRegs"); local
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/external/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp685 unsigned SubRegs = 0; local
690 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 2;
692 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 4;
695 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2;
697 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3;
699 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4;
702 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2, Spacing = 2;
704 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3, Spacing = 2;
706 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4, Spacing = 2;
711 for (unsigned i = 0; i != SubRegs;
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