/external/llvm/lib/Target/MBlaze/ |
H A D | MBlazeInstrInfo.cpp | 116 MachineBasicBlock *&TBB, 140 TBB = LastInst->getOperand(0).getMBB(); 145 TBB = LastInst->getOperand(1).getMBB(); 164 TBB = SecondLastInst->getOperand(1).getMBB(); 175 TBB = SecondLastInst->getOperand(0).getMBB(); 187 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, argument 192 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 202 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB); 204 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB); 208 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB); 115 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument [all...] |
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430InstrInfo.cpp | 170 MachineBasicBlock *&TBB, 200 TBB = I->getOperand(0).getMBB(); 212 TBB = 0; 218 // TBB is used to indicate the unconditinal destination. 219 TBB = I->getOperand(0).getMBB(); 232 FBB = TBB; 233 TBB = I->getOperand(0).getMBB(); 241 assert(TBB); 245 if (TBB != I->getOperand(0).getMBB()) 260 MSP430InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, argument 169 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument [all...] |
/external/llvm/lib/CodeGen/ |
H A D | CodePlacementOpt.cpp | 77 MachineBasicBlock *TBB = 0, *FBB = 0; local 79 if (TII->AnalyzeBranch(*MBB, TBB, FBB, Cond)) 85 if (Cond.empty() && TBB) 106 MachineBasicBlock *TBB = 0, *FBB = 0; 109 if (TII->AnalyzeBranch(*MBB, TBB, FBB, Cond))
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H A D | MachineBasicBlock.cpp | 347 MachineBasicBlock *TBB = 0, *FBB = 0; 350 bool B = TII->AnalyzeBranch(*this, TBB, FBB, Cond); 354 if (TBB) { 357 if (isLayoutSuccessor(TBB)) 366 assert(!TBB && "Found more than one non-landing-pad successor!"); 367 TBB = *SI; 372 if (!TBB) 377 if (!isLayoutSuccessor(TBB)) 378 TII->InsertBranch(*this, TBB, 0, Cond, dl); 385 if (isLayoutSuccessor(TBB)) { 605 MachineBasicBlock *TBB = 0, *FBB = 0; local [all...] |
H A D | MachineBlockPlacement.cpp | 888 MachineBasicBlock *TBB = 0, *FBB = 0; // For AnalyzeBranch. local 889 if (!TII->AnalyzeBranch(*BB, TBB, FBB, Cond) || !FI->canFallThrough()) 990 MachineBasicBlock *TBB = 0, *FBB = 0; // For AnalyzeBranch. local 991 if (!TII->AnalyzeBranch(*PrevBB, TBB, FBB, Cond)) 997 MachineBasicBlock *TBB = 0, *FBB = 0; // For AnalyzeBranch. local 998 if (!TII->AnalyzeBranch(F.back(), TBB, FBB, Cond))
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H A D | BranchFolding.cpp | 199 MachineBasicBlock *MBB = I, *TBB = 0, *FBB = 0; local 201 if (!TII->AnalyzeBranch(*MBB, TBB, FBB, Cond, true)) 202 MadeChange |= MBB->CorrectExtraCFGEdges(TBB, FBB, !Cond.empty()); 464 MachineBasicBlock *TBB = 0, *FBB = 0; local 468 !TII->AnalyzeBranch(*CurMBB, TBB, FBB, Cond, true)) { 470 if (TBB == NextBB && !Cond.empty() && !FBB) { 887 MachineBasicBlock *TBB = 0, *FBB = 0; local 889 if (!TII->AnalyzeBranch(*PBB, TBB, FBB, Cond, true)) { 893 if (!Cond.empty() && TBB == IBB) { 908 if (TBB 1570 MachineBasicBlock *TBB = 0, *FBB = 0; local [all...] |
H A D | MachineLICM.cpp | 804 MachineBasicBlock *TBB = 0, *FBB = 0; local 806 if (!TII->AnalyzeBranch(*BB, TBB, FBB, Cond, false) && Cond.empty())
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H A D | MachineVerifier.cpp | 444 MachineBasicBlock *TBB = 0, *FBB = 0; local 447 TBB, FBB, Cond)) { 450 if (!TBB && !FBB) { 478 } else if (TBB && !FBB && Cond.empty()) { 483 } else if (!MBB->isSuccessor(TBB)) { 497 } else if (TBB && !FBB && !Cond.empty()) { 506 } else if (!matchPair(MBB->succ_begin(), TBB, MBBI)) { 520 } else if (TBB && FBB) { 526 } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
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H A D | IfConversion.cpp | 82 /// TargetInstrInfo::AnalyzeBranch() (i.e. TBB, FBB, and Cond), and its 213 bool MeetIfcvtSizeLimit(MachineBasicBlock &TBB, argument 219 TII->isProfitableToIfCvt(TBB, TCycle, TExtra, FBB, FCycle, FExtra, 807 // TBB FBB 824 // | TBB 847 // | TBB---> exit 949 MachineBasicBlock *TBB = NULL, *FBB = NULL; local 951 if (!TII->AnalyzeBranch(*BBI.BB, TBB, FBB, Cond)) 952 BBI.BB->CorrectExtraCFGEdges(TBB, FBB, !Cond.empty());
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/external/llvm/lib/Target/CellSPU/ |
H A D | SPUInstrInfo.cpp | 213 SPUInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, argument 239 TBB = LastInst->getOperand(0).getMBB(); 243 TBB = LastInst->getOperand(1).getMBB(); 264 TBB = SecondLastInst->getOperand(1).getMBB(); 276 TBB = SecondLastInst->getOperand(0).getMBB(); 351 SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, argument 356 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 375 MIB.addMBB(TBB); 384 MIB.addMBB(TBB); 389 MIB.addReg(Cond[1].getReg()).addMBB(TBB); [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsInstrInfo.cpp | 297 MachineBasicBlock *&TBB, 310 // just return false, leaving TBB/FBB null. 311 TBB = FBB = NULL; 339 TBB = LastInst->getOperand(0).getMBB(); 344 AnalyzeCondBr(LastInst, LastOpc, TBB, Cond); 360 TBB = SecondLastInst->getOperand(0).getMBB(); 370 AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond); 377 MachineBasicBlock *TBB, DebugLoc DL, 387 MIB.addMBB(TBB); 391 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, argument 296 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument 376 BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, DebugLoc DL, const SmallVectorImpl<MachineOperand>& Cond) const argument [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 189 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, argument 214 TBB = LastInst->getOperand(0).getMBB(); 220 TBB = LastInst->getOperand(2).getMBB(); 243 TBB = SecondLastInst->getOperand(2).getMBB(); 256 TBB = SecondLastInst->getOperand(0).getMBB(); 295 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, argument 300 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 307 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB); 310 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 316 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); [all...] |
/external/llvm/lib/Target/Sparc/ |
H A D | SparcInstrInfo.cpp | 128 MachineBasicBlock *&TBB, 155 TBB = I->getOperand(0).getMBB(); 166 TBB = 0; 173 TBB = I->getOperand(0).getMBB(); 217 FBB = TBB; 218 TBB = I->getOperand(0).getMBB(); 230 SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, argument 234 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 240 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB); 248 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB) 127 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreInstrInfo.cpp | 169 /// just return false, leaving TBB/FBB null. 170 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 173 /// an successor block, it sets TBB to be the branch destination block and a 178 /// block, it returns the 'true' destination in TBB, the 'false' destination 187 XCoreInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, argument 210 TBB = LastInst->getOperand(0).getMBB(); 221 TBB = LastInst->getOperand(1).getMBB(); 243 TBB = SecondLastInst->getOperand(1).getMBB(); 255 TBB = SecondLastInst->getOperand(0).getMBB(); 275 XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, argument [all...] |
/external/llvm/lib/Target/PTX/ |
H A D | PTXInstrInfo.cpp | 178 MachineBasicBlock *&TBB, 198 DEBUG(dbgs() << "AnalyzeBranch: TBB: " << TBB << "\n"); 212 TBB = GetBranchTarget(instLast1); 221 TBB = GetBranchTarget(instLast1); 237 TBB = GetBranchTarget(instLast2); 265 MachineBasicBlock *TBB, 270 DEBUG(if (TBB) dbgs() << "InsertBranch: TBB: " << TBB 177 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument 264 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument [all...] |
/external/llvm/include/llvm/Target/ |
H A D | TargetInstrInfo.h | 252 /// just return false, leaving TBB/FBB null. 253 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 256 /// successor block, it sets TBB to be the branch destination block and a 260 /// unconditional branch, it returns the 'true' destination in TBB, the 271 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, argument 295 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, argument
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonInstrInfo.cpp | 121 HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, argument 129 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 156 return InsertBranch(MBB, TBB, 0, Cond, DL); 159 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); 162 get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB); 167 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB); 175 MachineBasicBlock *&TBB, 221 TBB = LastInst->getOperand(0).getMBB(); 226 TBB = LastInst->getOperand(1).getMBB(); 232 TBB 174 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 1260 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)]; local 1273 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) { 1274 std::swap(TBB, FBB); 1289 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR); 1291 FuncInfo.MBB->addSuccessor(TBB); 1305 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) { 1306 std::swap(TBB, FBB); 1312 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR); 1315 FuncInfo.MBB->addSuccessor(TBB); 1321 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB; [all...] |
H A D | ARMBaseInstrInfo.cpp | 267 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, argument 291 TBB = LastInst->getOperand(0).getMBB(); 296 TBB = LastInst->getOperand(0).getMBB(); 317 TBB = LastInst->getOperand(0).getMBB(); 332 TBB = SecondLastInst->getOperand(0).getMBB(); 342 TBB = SecondLastInst->getOperand(0).getMBB(); 395 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, argument 407 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 414 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0); 416 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.cpp | 2162 MachineBasicBlock *&TBB, 2190 TBB = I->getOperand(0).getMBB(); 2203 TBB = 0; 2210 // TBB is used to indicate the unconditional destination. 2211 TBB = I->getOperand(0).getMBB(); 2260 FBB = TBB; 2261 TBB = I->getOperand(0).getMBB(); 2270 assert(TBB); 2274 if (TBB != I->getOperand(0).getMBB()) 2326 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, argument 2161 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGBuilder.cpp | 1342 MachineBasicBlock *TBB, 1370 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1378 NULL, TBB, FBB, CurBB); 1384 MachineBasicBlock *TBB, 1396 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1408 // jmp_if_X TBB 1411 // jmp_if_Y TBB 1416 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1419 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1426 // jmp_if_Y TBB 1341 EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock *CurBB, MachineBasicBlock *SwitchBB) argument 1383 FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock *CurBB, MachineBasicBlock *SwitchBB, unsigned Opc) argument [all...] |