Searched defs:isSub (Results 1 - 6 of 6) sorted by relevance

/external/llvm/lib/Target/X86/
H A DX86FrameLowering.cpp150 bool isSub = NumBytes < 0; local
151 uint64_t Offset = isSub ? -NumBytes : NumBytes;
156 Opc = isSub
167 unsigned Reg = isSub
171 Opc = isSub
175 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
176 if (isSub)
187 StackPtr, false, isSub ? -ThisVal : ThisVal);
195 if (isSub)
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/external/llvm/lib/Target/ARM/
H A DThumb1RegisterInfo.cpp100 bool isSub = false; local
106 isSub = true;
128 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
133 if (DestReg == ARM::SP || isSub)
173 bool isSub = NumBytes < 0; local
175 if (isSub) Bytes = -NumBytes;
189 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
191 } else if (!isSub && BaseReg == ARM::SP) {
211 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
216 Opc = isSub
347 bool isSub = Imm < 0; local
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H A DARMBaseInstrInfo.cpp161 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; local
169 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
176 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
181 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
187 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; local
192 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
197 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
1582 bool isSub = NumBytes < 0; local
1583 if (isSub) NumBytes = -NumBytes;
1596 unsigned Opc = isSub
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H A DARMISelLowering.cpp6247 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub; local
6249 if (isSub)
/external/llvm/lib/Transforms/InstCombine/
H A DInstCombineAndOrXor.cpp335 /// where isSub determines whether the operator is a sub. If we can fold one of
345 ConstantInt *Mask, bool isSub,
385 if (isSub)
344 FoldLogicalPlusAnd(Value *LHS, Value *RHS, ConstantInt *Mask, bool isSub, Instruction &I) argument
/external/valgrind/main/VEX/priv/
H A Dguest_arm_toIR.c15335 UInt isSub = INSN0(9,9); local
15340 putIRegT(rD, binop(isSub ? Iop_Sub32 : Iop_Add32,
15343 setFlags_D1_D2( isSub ? ARMG_CC_OP_SUB : ARMG_CC_OP_ADD,
15345 DIP("%s r%u, r%u, #%u\n", isSub ? "subs" : "adds", rD, rN, uimm3);
15356 UInt isSub = INSN0(9,9); local
15361 putIRegT( rD, binop(isSub ? Iop_Sub32 : Iop_Add32,
15364 setFlags_D1_D2( isSub ? ARMG_CC_OP_SUB : ARMG_CC_OP_ADD,
15366 DIP("%s r%u, r%u, r%u\n", isSub ? "subs" : "adds", rD, rN, rM);
15509 UInt isSub = INSN0(11,11); local
15516 putIRegT( rN, binop(isSub
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