/dalvik/vm/compiler/template/ia32/ |
H A D | header.S | 23 #define rINST %ebx define
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/dalvik/vm/compiler/template/armv5te/ |
H A D | header.S | 65 r7 rINST first 16-bit code unit of current instruction 77 #define rINST r7 define
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/dalvik/vm/compiler/template/out/ |
H A D | CompilerTemplateAsm-ia32.S | 30 #define rINST %ebx define
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H A D | CompilerTemplateAsm-armv5te.S | 72 r7 rINST first 16-bit code unit of current instruction 84 #define rINST r7 define
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H A D | CompilerTemplateAsm-armv5te-vfp.S | 72 r7 rINST first 16-bit code unit of current instruction 84 #define rINST r7 define
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H A D | CompilerTemplateAsm-armv7-a-neon.S | 72 r7 rINST first 16-bit code unit of current instruction 84 #define rINST r7 define
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H A D | CompilerTemplateAsm-armv7-a.S | 72 r7 rINST first 16-bit code unit of current instruction 84 #define rINST r7 define
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/dalvik/vm/mterp/x86-atom/ |
H A D | header.S | 46 * %ebx rINST first 16-bit code unit of current instruction 62 #define rINST %ebx define 144 * Fetch the next instruction from rPC into rINST. Does not advance rPC. 148 movzwl (rPC), rINST 162 movzwl (rPC), rINST 173 movzwl (rPC), rINST 271 movzbl 1(rPC), rINST 286 movzbl (\_count*2 + 1)(rPC), rINST 302 movzbl 1(\_reg, rPC), rINST 317 movzbl 1(rPC), rINST [all...] |
/dalvik/vm/mterp/armv5te/ |
H A D | header.S | 60 r7 rINST first 16-bit code unit of current instruction 72 #define rINST r7 define 104 * Fetch the next instruction from rPC into rINST. Does not advance rPC. 106 #define FETCH_INST() ldrh rINST, [rPC] 120 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #((_count)*2)]! 124 * src and dest registers are parameterized (not hard-wired to rPC and rINST). 134 * We want to write "ldrh rINST, [rPC, _reg, lsl #1]!", but some of the 139 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]! 160 #define GET_INST_OPCODE(_reg) and _reg, rINST, #255
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/dalvik/vm/mterp/out/ |
H A D | InterpAsm-x86-atom.S | 53 * %ebx rINST first 16-bit code unit of current instruction 69 #define rINST %ebx define 151 * Fetch the next instruction from rPC into rINST. Does not advance rPC. 155 movzwl (rPC), rINST 169 movzwl (rPC), rINST 180 movzwl (rPC), rINST 278 movzbl 1(rPC), rINST 293 movzbl (\_count*2 + 1)(rPC), rINST 309 movzbl 1(\_reg, rPC), rINST 324 movzbl 1(rPC), rINST [all...] |
H A D | InterpAsm-x86.S | 78 #define rINST %ebx define 172 movzwl (rPC),rINST 196 movzwl \_count*2(rPC),rINST 204 movzwl (rPC,\_reg,2),rINST 223 movzbl rINSTbh,rINST 232 movzbl 1(rPC),rINST 325 shrl $4,rINST # rINST<- B 326 GET_VREG_R rINST rINST [all...] |
H A D | InterpAsm-armv5te-vfp.S | 67 r7 rINST first 16-bit code unit of current instruction 79 #define rINST r7 define 111 * Fetch the next instruction from rPC into rINST. Does not advance rPC. 113 #define FETCH_INST() ldrh rINST, [rPC] 127 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #((_count)*2)]! 131 * src and dest registers are parameterized (not hard-wired to rPC and rINST). 141 * We want to write "ldrh rINST, [rPC, _reg, lsl #1]!", but some of the 146 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]! 167 #define GET_INST_OPCODE(_reg) and _reg, rINST, #255 315 FETCH_INST() @ load rINST fro [all...] |
H A D | InterpAsm-armv5te.S | 67 r7 rINST first 16-bit code unit of current instruction 79 #define rINST r7 define 111 * Fetch the next instruction from rPC into rINST. Does not advance rPC. 113 #define FETCH_INST() ldrh rINST, [rPC] 127 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #((_count)*2)]! 131 * src and dest registers are parameterized (not hard-wired to rPC and rINST). 141 * We want to write "ldrh rINST, [rPC, _reg, lsl #1]!", but some of the 146 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]! 167 #define GET_INST_OPCODE(_reg) and _reg, rINST, #255 315 FETCH_INST() @ load rINST fro [all...] |
H A D | InterpAsm-armv7-a-neon.S | 67 r7 rINST first 16-bit code unit of current instruction 79 #define rINST r7 define 111 * Fetch the next instruction from rPC into rINST. Does not advance rPC. 113 #define FETCH_INST() ldrh rINST, [rPC] 127 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #((_count)*2)]! 131 * src and dest registers are parameterized (not hard-wired to rPC and rINST). 141 * We want to write "ldrh rINST, [rPC, _reg, lsl #1]!", but some of the 146 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]! 167 #define GET_INST_OPCODE(_reg) and _reg, rINST, #255 329 FETCH_INST() @ load rINST fro [all...] |
H A D | InterpAsm-armv7-a.S | 67 r7 rINST first 16-bit code unit of current instruction 79 #define rINST r7 define 111 * Fetch the next instruction from rPC into rINST. Does not advance rPC. 113 #define FETCH_INST() ldrh rINST, [rPC] 127 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #((_count)*2)]! 131 * src and dest registers are parameterized (not hard-wired to rPC and rINST). 141 * We want to write "ldrh rINST, [rPC, _reg, lsl #1]!", but some of the 146 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]! 167 #define GET_INST_OPCODE(_reg) and _reg, rINST, #255 329 FETCH_INST() @ load rINST fro [all...] |
/dalvik/vm/mterp/x86/ |
H A D | header.S | 71 #define rINST %ebx define 165 movzwl (rPC),rINST 189 movzwl \_count*2(rPC),rINST 197 movzwl (rPC,\_reg,2),rINST 216 movzbl rINSTbh,rINST 225 movzbl 1(rPC),rINST
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/dalvik/vm/compiler/codegen/x86/ |
H A D | X86LIR.h | 31 * ebx is rINST 47 * Preload rINST/%ebx such that high 24 bits are zero and 149 #define rINST rEBX macro
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