/dalvik/vm/mterp/armv5te/ |
H A D | OP_IGET_QUICK.S | 6 GET_VREG(r3, r2) @ r3<- object we're operating on 8 cmp r3, #0 @ check object for null 11 ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits)
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H A D | OP_IGET_WIDE_QUICK.S | 5 GET_VREG(r3, r2) @ r3<- object we're operating on 7 cmp r3, #0 @ check object for null 10 ldrd r0, [r3, ip] @ r0<- obj.field (64 bits, aligned) 13 add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 15 stmia r3, {r0-r1} @ fp[A]<- r0/r1
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H A D | OP_NEW_INSTANCE.S | 13 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 15 ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 16 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 18 add r10, r3, r1, lsl #2 @ r10<- &resolved_class 35 mov r3, rINST, lsr #8 @ r3<- AA 52 SET_VREG(r0, r3) [all...] |
H A D | OP_INVOKE_VIRTUAL.S | 12 ldr r3, [rSELF, #offThread_methodClassDex] @ r3<- pDvmDex 14 ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 16 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 23 ldr r3, [rSELF, #offThread_method] @ r3<- self->method 24 ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 42 ldr r3, [r [all...] |
H A D | binopWide.S | 4 * specifies an instruction that performs "result = r0-r1 op r2-r3". 21 mov r3, r0, lsr #8 @ r3<- CC 24 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 26 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 28 orrs ip, r2, r3 [all...] |
H A D | OP_CONST_WIDE_16.S | 4 mov r3, rINST, lsr #8 @ r3<- AA 7 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 9 stmia r3, {r0-r1} @ vAA<- r0/r1
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H A D | OP_CONST_WIDE_32.S | 4 mov r3, rINST, lsr #8 @ r3<- AA 8 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 11 stmia r3, {r0-r1} @ vAA<- r0/r1
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H A D | OP_CONST_WIDE_HIGH16.S | 4 mov r3, rINST, lsr #8 @ r3<- AA 8 add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 10 stmia r3, {r0-r1} @ vAA<- r0/r1
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H A D | OP_MOVE_WIDE_16.S | 4 FETCH(r3, 2) @ r3<- BBBB 6 add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 8 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB]
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H A D | OP_MOVE_WIDE_FROM16.S | 4 FETCH(r3, 1) @ r3<- BBBB 6 add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 8 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB]
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H A D | OP_INVOKE_VIRTUAL_QUICK.S | 11 FETCH(r3, 2) @ r3<- FEDC or CCCC 14 and r3, r3, #15 @ r3<- C (or stays CCCC) 16 GET_VREG(r9, r3) @ r9<- vC ("this" ptr) 22 ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB]
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H A D | unopNarrower.S | 13 mov r3, rINST, lsr #12 @ r3<- B 15 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 17 ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1 20 $instr @ r0<- op, r0-r3 changed
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H A D | unopWide.S | 11 mov r3, rINST, lsr #12 @ r3<- B 13 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 15 ldmia r3, {r0-r1} @ r0/r1<- vAA 18 $instr @ r0/r1<- op, r2-r3 changed
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/dalvik/vm/mterp/armv6t2/ |
H A D | unopNarrower.S | 13 mov r3, rINST, lsr #12 @ r3<- B 15 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 16 ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1 19 $instr @ r0<- op, r0-r3 changed
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H A D | OP_IGET_QUICK.S | 7 GET_VREG(r3, r2) @ r3<- object we're operating on 9 cmp r3, #0 @ check object for null 11 ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits)
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H A D | OP_IGET_WIDE_QUICK.S | 6 GET_VREG(r3, r2) @ r3<- object we're operating on 8 cmp r3, #0 @ check object for null 10 ldrd r0, [r3, ip] @ r0<- obj.field (64 bits, aligned) 12 add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 14 stmia r3, {r0-r1} @ fp[A]<- r0/r1
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H A D | OP_MOVE_WIDE.S | 4 mov r3, rINST, lsr #12 @ r3<- B 6 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 8 ldmia r3, {r0-r1} @ r0/r1<- fp[B]
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H A D | unopWide.S | 10 mov r3, rINST, lsr #12 @ r3<- B 12 add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 14 ldmia r3, {r0-r1} @ r0/r1<- vAA 17 $instr @ r0/r1<- op, r2-r3 changed
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/dalvik/vm/compiler/template/armv5te/ |
H A D | TEMPLATE_MONITOR_ENTER.S | 13 mov r3, #0 @ Record that we're not returning 14 str r3, [r0, #offThread_inJitCodeCache]
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H A D | TEMPLATE_MONITOR_ENTER_DEBUG.S | 13 mov r3, #0 @ Record that we're not returning 14 str r3, [r0, #offThread_inJitCodeCache]
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/dalvik/vm/mterp/arm-vfp/ |
H A D | fbinop2addr.S | 9 mov r3, rINST, lsr #12 @ r3<- B 11 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 13 flds s1, [r3] @ s1<- vB
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H A D | fbinopWide2addr.S | 10 mov r3, rINST, lsr #12 @ r3<- B 12 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 14 fldd d1, [r3] @ d1<- vB
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H A D | funop.S | 8 mov r3, rINST, lsr #12 @ r3<- B 10 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 11 flds s0, [r3] @ s0<- vB
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H A D | funopNarrower.S | 8 mov r3, rINST, lsr #12 @ r3<- B 10 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 11 fldd d0, [r3] @ d0<- vB
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H A D | funopWider.S | 8 mov r3, rINST, lsr #12 @ r3<- B 10 VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 11 flds s0, [r3] @ s0<- vB
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