| /dalvik/vm/compiler/template/ia32/ |
| H A D | header.S | 21 #define rPC %esi define
|
| H A D | TEMPLATE_INTERPRET.S | 6 * will be located at *rp. When called from static code, rPC is
13 * we got here via chaining. Otherwise, we'll assume rPC is valid.
33 movl %eax,rPC
|
| /dalvik/vm/mterp/x86-atom/ |
| H A D | header.S | 44 * %esi rPC interpreted program counter, used for fetching
66 #define rPC %esi define
90 movl rPC, offGlue_pc(\_reg)
100 movl offGlue_pc(rFP), rPC
115 movl rPC, (-sizeofStackSaveArea + offStackSaveArea_currentPc)(rFP)
144 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
148 movzwl (rPC), rINST
152 * Fetch the next instruction from the specified offset. Advances rPC
161 add $$(\_count*2), rPC
[all...] |
| H A D | zcmp.S | 50 movzbl 4(rPC), %edx # grab the next opcode
51 movzbl 5(rPC), rINST # update the instruction
52 addl $$4, rPC # update the program counter
|
| /dalvik/vm/mterp/armv5te/ |
| H A D | OP_BREAKPOINT.S | 9 mov r0, rPC
10 bl dvmGetOriginalOpcode @ (rPC)
|
| H A D | header.S | 57 r4 rPC interpreted program counter, used for fetching instructions
69 #define rPC r4 define
76 #define LOAD_PC_FROM_SELF() ldr rPC, [rSELF, #offThread_pc]
77 #define SAVE_PC_TO_SELF() str rPC, [rSELF, #offThread_pc]
80 #define LOAD_PC_FP_FROM_SELF() ldmia rSELF, {rPC, rFP}
81 #define SAVE_PC_FP_TO_SELF() stmia rSELF, {rPC, rFP}
93 str rPC, [rFP, #(-sizeofStackSaveArea + offStackSaveArea_currentPc)]
104 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
106 #define FETCH_INST() ldrh rINST, [rPC]
[all...] |
| /dalvik/vm/mterp/x86/ |
| H A D | OP_BREAKPOINT.S | 12 movl rPC,OUT_ARG0(%esp)
16 movzbl 1(rPC),rINST
|
| H A D | OP_MOVE_16.S | 4 movzwl 4(rPC),%ecx # ecx<- BBBB
5 movzwl 2(rPC),%eax # eax<- AAAA
|
| H A D | binopLit8.S | 13 movzbl 2(rPC),%eax # eax<- BB
14 movsbl 3(rPC),%ecx # ecx<- ssssssCC
|
| H A D | OP_CONST_16.S | 3 movswl 2(rPC),%ecx # ecx<- ssssBBBB
|
| H A D | OP_CONST_WIDE.S | 3 movl 2(rPC),%eax # eax<- lsw
5 movl 6(rPC),rINST # rINST<- msw
|
| H A D | OP_MOVE_WIDE_16.S | 4 movzwl 4(rPC),%ecx # ecx<- BBBB
5 movzwl 2(rPC),%eax # eax<- AAAA
|
| H A D | OP_MUL_INT.S | 6 movzbl 2(rPC),%eax # eax<- BB
7 movzbl 3(rPC),%ecx # ecx<- CC
|
| H A D | OP_MUL_INT_LIT8.S | 3 movzbl 2(rPC),%eax # eax<- BB
4 movsbl 3(rPC),%ecx # ecx<- ssssssCC
|
| H A D | binflop.S | 7 movzbl 2(rPC),%eax # eax<- CC
8 movzbl 3(rPC),%ecx # ecx<- BB
|
| H A D | binop.S | 12 movzbl 2(rPC),%eax # eax<- BB
13 movzbl 3(rPC),%ecx # ecx<- CC
|
| H A D | binop1.S | 7 movzbl 2(rPC),%eax # eax<- BB
8 movzbl 3(rPC),%ecx # ecx<- CC
|
| H A D | OP_CONST_HIGH16.S | 3 movzwl 2(rPC),%eax # eax<- 0000BBBB
|
| H A D | OP_GOTO_16.S | 10 movswl 2(rPC),%eax # eax<- ssssAAAA
|
| H A D | OP_GOTO_32.S | 10 movl 2(rPC),%eax # eax<- AAAAAAAA
|
| H A D | header.S | 54 rPC edi interpreted program counter, used for fetching instructions
63 o rPC, rFP, rINSTw/rINSTbl valid on handler entry and exit
69 #define rPC %esi define
125 movl rPC,offThread_pc(\_reg)
131 movl offThread_pc(rFP),rPC
149 movl rPC, (-sizeofStackSaveArea + offStackSaveArea_currentPc)(rFP)
162 * Fetch the next instruction from rPC into rINSTw. Does not advance rPC.
165 movzwl (rPC),rINST
173 movzbl (rPC),\_re
[all...] |
| H A D | OP_CONST.S | 3 movl 2(rPC),%eax # grab all 32 bits at once
|
| H A D | OP_MOVE_FROM16.S | 5 movw 2(rPC),rINSTw # rINSTw <= BBBB
|
| /dalvik/vm/compiler/template/armv5te/ |
| H A D | header.S | 64 r4 rPC interpreted program counter, used for fetching instructions
74 #define rPC r4 define
89 str rPC, [rFP, #(-sizeofStackSaveArea + offStackSaveArea_currentPc)]
|
| /dalvik/vm/compiler/template/out/ |
| H A D | CompilerTemplateAsm-ia32.S | 28 #define rPC %esi define
64 * will be located at *rp. When called from static code, rPC is
71 * we got here via chaining. Otherwise, we'll assume rPC is valid.
91 movl %eax,rPC
|