Searched refs:ADDE (Results 1 - 15 of 15) sorted by relevance
| /external/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 210 ADDE, SUBE, enumerator in enum:llvm::ISD::NodeType
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| H A D | SelectionDAG.h | 911 case ISD::ADDE: return true;
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| /external/llvm/lib/Target/Mips/ |
| H A D | MipsISelDAGToDAG.cpp | 387 case ISD::ADDE: {
390 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
395 if (Opcode == ISD::ADDE) {
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| H A D | MipsISelLowering.cpp | 262 setTargetDAGCombine(ISD::ADDE);
713 case ISD::ADDE:
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 80 ADDE, // Add using carry enumerator in enum:llvm::ARMISD::NodeType
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| H A D | ARMISelLowering.cpp | 616 setOperationAction(ISD::ADDE, MVT::i32, Custom);
917 case ARMISD::ADDE: return "ARMISD::ADDE";
5080 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break;
5185 case ISD::ADDE:
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| /external/qemu/tcg/ppc/ |
| H A D | tcg-target.c | 346 #define ADDE XO31(138) macro
1617 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1622 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 199 case ISD::ADDE: return "adde";
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| H A D | LegalizeIntegerTypes.cpp | 1153 case ISD::ADDE:
1291 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps, 3);
1527 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1529 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1542 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1591 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
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| H A D | SelectionDAG.cpp | 1983 case ISD::ADDE: {
2001 // With ADDE, a carry bit may be added in, so we can only use this
2005 if (KnownZeroOut >= 2) // ADDE
3048 case ISD::ADDE:
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| H A D | DAGCombiner.cpp | 1095 case ISD::ADDE: return visitADDE(N);
1574 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
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| /external/qemu/tcg/ppc64/ |
| H A D | tcg-target.c | 336 #define ADDE XO31(138) macro
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| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 89 setOperationAction(ISD::ADDE, MVT::i32, Expand);
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| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 316 case ISD::ADDE:
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| H A D | X86ISelLowering.cpp | 360 setOperationAction(ISD::ADDE, VT, Custom);
10808 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10888 case ISD::ADDE:
10951 case ISD::ADDE:
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