/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelDAGToDAG.cpp | 106 bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM); 107 bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM); 108 bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM); 139 bool MSP430DAGToDAGISel::MatchWrapper(SDValue N, MSP430ISelAddressMode &AM) { argument 142 if (AM.hasSymbolicDisplacement()) 148 AM.GV = G->getGlobal(); 149 AM.Disp += G->getOffset(); 150 //AM.SymbolFlags = G->getTargetFlags(); 152 AM.CP = CP->getConstVal(); 153 AM 171 MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM) argument 184 MatchAddress(SDValue N, MSP430ISelAddressMode &AM) argument 250 MSP430ISelAddressMode AM; local 303 ISD::MemIndexedMode AM = LD->getAddressingMode(); local [all...] |
H A D | MSP430ISelLowering.h | 173 ISD::MemIndexedMode &AM,
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrBuilder.h | 123 const X86AddressMode &AM) { 124 assert(AM.Scale == 1 || AM.Scale == 2 || AM.Scale == 4 || AM.Scale == 8); 126 if (AM.BaseType == X86AddressMode::RegBase) 127 MIB.addReg(AM.Base.Reg); 129 assert(AM.BaseType == X86AddressMode::FrameIndexBase); 130 MIB.addFrameIndex(AM.Base.FrameIndex); 133 MIB.addImm(AM 122 addFullAddress(const MachineInstrBuilder &MIB, const X86AddressMode &AM) argument [all...] |
H A D | X86ISelDAGToDAG.cpp | 194 bool FoldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM); 195 bool MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM); 196 bool MatchWrapper(SDValue N, X86ISelAddressMode &AM); 197 bool MatchAddress(SDValue N, X86ISelAddressMode &AM); 198 bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM, 200 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM); 229 inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base, argument 232 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ? 233 CurDAG->getTargetFrameIndex(AM.Base_FrameIndex, TLI.getPointerTy()) : 234 AM 565 FoldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM) argument 584 MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM) argument 612 MatchWrapper(SDValue N, X86ISelAddressMode &AM) argument 699 MatchAddress(SDValue N, X86ISelAddressMode &AM) argument 744 FoldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N, uint64_t Mask, SDValue Shift, SDValue X, X86ISelAddressMode &AM) argument 787 FoldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N, uint64_t Mask, SDValue Shift, SDValue X, X86ISelAddressMode &AM) argument 854 FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N, uint64_t Mask, SDValue Shift, SDValue X, X86ISelAddressMode &AM) argument 935 MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM, unsigned Depth) argument 1246 MatchAddressBase(SDValue N, X86ISelAddressMode &AM) argument 1276 X86ISelAddressMode AM; local 1361 X86ISelAddressMode AM; local 1425 X86ISelAddressMode AM; local [all...] |
H A D | X86FastISel.cpp | 81 bool X86FastEmitLoad(EVT VT, const X86AddressMode &AM, unsigned &RR); 83 bool X86FastEmitStore(EVT VT, const Value *Val, const X86AddressMode &AM); 84 bool X86FastEmitStore(EVT VT, unsigned Val, const X86AddressMode &AM); 89 bool X86SelectAddress(const Value *V, X86AddressMode &AM); 90 bool X86SelectCallAddress(const Value *V, X86AddressMode &AM); 176 bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM, argument 226 DL, TII.get(Opc), ResultReg), AM); 235 X86FastISel::X86FastEmitStore(EVT VT, unsigned Val, const X86AddressMode &AM) { argument 276 DL, TII.get(Opc)), AM).addReg(Val); 281 const X86AddressMode &AM) { 280 X86FastEmitStore(EVT VT, const Value *Val, const X86AddressMode &AM) argument 337 X86SelectAddress(const Value *V, X86AddressMode &AM) argument 597 X86SelectCallAddress(const Value *V, X86AddressMode &AM) argument 1433 X86AddressMode AM; local 1440 X86AddressMode AM; local 1748 X86AddressMode AM; local 2044 X86AddressMode AM; local 2159 X86AddressMode AM; local [all...] |
/external/chromium/chrome/common/extensions/docs/examples/extensions/benchmark/jquery/ |
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/external/llvm/include/llvm/Transforms/Utils/ |
H A D | AddrModeMatcher.h | 50 static inline raw_ostream &operator<<(raw_ostream &OS, const ExtAddrMode &AM) { argument 51 AM.print(OS); 75 Instruction *MI, ExtAddrMode &AM) 76 : AddrModeInsts(AMI), TLI(T), AccessTy(AT), MemoryInst(MI), AddrMode(AM) { 73 AddressingModeMatcher(SmallVectorImpl<Instruction*> &AMI, const TargetLowering &T, Type *AT, Instruction *MI, ExtAddrMode &AM) argument
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/external/llvm/lib/Transforms/Scalar/ |
H A D | LoopStrengthReduce.cpp | 224 /// AM - This is used to represent complex addressing, as well as other kinds 226 TargetLowering::AddrMode AM; member in struct:__anon7782::Formula 229 /// non-empty, AM.HasBaseReg should be set to true. 233 /// when AM.Scale is not zero. 327 AM.HasBaseReg = true; 333 AM.HasBaseReg = true; 349 AM.BaseGV ? AM.BaseGV->getType() : 382 if (AM.BaseGV) { 384 WriteAsOperand(OS, AM 1261 isLegalUse(const TargetLowering::AddrMode &AM, LSRUse::KindType Kind, Type *AccessTy, const TargetLowering *TLI) argument 1318 isLegalUse(TargetLowering::AddrMode AM, int64_t MinOffset, int64_t MaxOffset, LSRUse::KindType Kind, Type *AccessTy, const TargetLowering *TLI) argument 1978 TargetLowering::AddrMode AM; local [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGDumper.cpp | 315 const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { argument 316 switch (AM) { 450 const char *AM = getIndexedModeName(LD->getAddressingMode()); local 451 if (*AM) 452 OS << ", " << AM; local 461 const char *AM = getIndexedModeName(ST->getAddressingMode()); local 462 if (*AM) 463 OS << ", " << AM; local
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H A D | TargetLowering.cpp | 3220 /// by AM is legal for this target, for a load/store of the specified type. 3221 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, argument 3227 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 3231 if (AM.BaseGV) 3235 switch (AM.Scale) { 3239 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 3244 if (AM.HasBaseReg || AM [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.h | 137 ISD::MemIndexedMode &AM, 148 /// by AM is legal for this target, for a load/store of the specified type. 152 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
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H A D | HexagonISelLowering.cpp | 626 ISD::MemIndexedMode &AM, 651 AM = isInc ? ISD::POST_INC : ISD::POST_DEC; 1418 /// AM is legal for this target, for a load/store of the specified type. 1419 bool HexagonTargetLowering::isLegalAddressingMode(const AddrMode &AM, argument 1422 if (AM.BaseOffs <= -(1LL << 13) || AM.BaseOffs >= (1LL << 13)-1) { 1427 if (AM.BaseGV) { 1431 int Scale = AM.Scale; 623 getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const argument
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H A D | HexagonISelDAGToDAG.cpp | 581 ISD::MemIndexedMode AM = LD->getAddressingMode(); local 584 if (AM != ISD::UNINDEXED) { 720 ISD::MemIndexedMode AM = ST->getAddressingMode(); local 723 if (AM != ISD::UNINDEXED) {
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/external/llvm/lib/Analysis/ |
H A D | TypeBasedAliasAnalysis.cpp | 220 const MDNode *AM = LocA.TBAATag; local 221 if (!AM) return AliasAnalysis::alias(LocA, LocB); 226 if (Aliases(AM, BM))
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/external/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 285 /// by AM is legal for this target, for a load/store of the specified type. 286 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const; 287 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 306 ISD::MemIndexedMode &AM, 314 ISD::MemIndexedMode &AM,
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H A D | ARMISelDAGToDAG.cpp | 728 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) local 731 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) 764 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) local 767 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) 784 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) local 787 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) 857 ISD::MemIndexedMode AM local 943 ISD::MemIndexedMode AM = LdSt->getAddressingMode(); local 1259 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) local 1332 ISD::MemIndexedMode AM = LD->getAddressingMode(); local 1405 ISD::MemIndexedMode AM = LD->getAddressingMode(); local [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 1562 /// by AM is legal for this target, for a load/store of the specified type. 1564 XCoreTargetLowering::isLegalAddressingMode(const AddrMode &AM, argument 1567 return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs); 1571 if (AM.BaseGV) { 1572 return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 && 1573 AM.BaseOffs%4 == 0; 1579 if (AM [all...] |
H A D | XCoreISelLowering.h | 103 virtual bool isLegalAddressingMode(const AddrMode &AM,
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/external/llvm/lib/Target/CellSPU/ |
H A D | SPUISelLowering.h | 180 virtual bool isLegalAddressingMode(const AddrMode &AM,
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H A D | SPUISelLowering.cpp | 3243 SPUTargetLowering::isLegalAddressingMode(const AddrMode &AM, argument 3247 if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && AM.BaseOffs == 0) 3251 if (AM.BaseGV ==0 && AM.HasBaseReg && AM.Scale == 0 && isInt<14>(AM.BaseOffs)) 3255 if (AM [all...] |
/external/apache-harmony/luni/src/test/api/common/org/apache/harmony/luni/tests/java/util/ |
H A D | CalendarTest.java | 367 cal.set(Calendar.AM_PM, Calendar.AM); 376 cal.set(Calendar.AM_PM, Calendar.AM); 378 Calendar.AM, cal.get(Calendar.AM_PM)); 390 int newValue = (oldValue == Calendar.AM) ? Calendar.PM : Calendar.AM; 802 cal.set(Calendar.AM_PM, Calendar.AM);
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/external/llvm/include/llvm/CodeGen/ |
H A D | SelectionDAGNodes.h | 606 static const char* getIndexedModeName(ISD::MemIndexedMode AM); 1582 unsigned numOperands, SDVTList VTs, ISD::MemIndexedMode AM, 1585 SubclassData |= AM << 2; 1586 assert(getAddressingMode() == AM && "MemIndexedMode encoding error!"); 1620 ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT, 1623 VTs, AM, MemVT, MMO) { 1651 ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT, 1654 VTs, AM, MemVT, MMO) { 1581 LSBaseSDNode(ISD::NodeType NodeTy, DebugLoc dl, SDValue *Operands, unsigned numOperands, SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT, MachineMemOperand *MMO) argument 1619 LoadSDNode(SDValue *ChainPtrOff, DebugLoc dl, SDVTList VTs, ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT, MachineMemOperand *MMO) argument 1650 StoreSDNode(SDValue *ChainValuePtrOff, DebugLoc dl, SDVTList VTs, ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT, MachineMemOperand *MMO) argument
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H A D | SelectionDAG.h | 664 SDValue Offset, ISD::MemIndexedMode AM); 665 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, 672 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, 693 SDValue Offset, ISD::MemIndexedMode AM);
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.h | 258 ISD::MemIndexedMode &AM, 338 /// by AM is legal for this target, for a load/store of the specified type. 339 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
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/external/jsilver/src/org/clearsilver/jni/ |
H A D | JniHdf.java | 235 cal.get(Calendar.AM_PM) == Calendar.AM ? "1" : "0");
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