/external/clang/lib/Analysis/ |
H A D | FormatString.cpp | 81 const OptionalAmount &Amt = ParseAmount(I, E); local 83 if (Amt.getHowSpecified() == OptionalAmount::NotSpecified) { 94 assert(Amt.getHowSpecified() == OptionalAmount::Constant); 100 if (Amt.getConstantAmount() == 0) { 108 return OptionalAmount(OptionalAmount::Arg, Amt.getConstantAmount() - 1, 131 const OptionalAmount Amt = local 135 if (Amt.isInvalid()) 137 CS.setFieldWidth(Amt); 150 const OptionalAmount &Amt = ParseAmount(I, E); local 158 if (Amt [all...] |
H A D | ScanfFormatString.cpp | 123 const OptionalAmount &Amt = clang::analyze_format_string::ParseAmount(I, E); local 124 if (Amt.getHowSpecified() != OptionalAmount::NotSpecified) { 125 assert(Amt.getHowSpecified() == OptionalAmount::Constant); 126 FS.setFieldWidth(Amt);
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H A D | PrintfFormatString.cpp | 42 const OptionalAmount Amt = ParsePositionAmount(H, Start, Beg, E, local 44 if (Amt.isInvalid()) 46 FS.setPrecision(Amt);
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/external/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMAddressingModes.h | 86 static inline unsigned rotr32(unsigned Val, unsigned Amt) { argument 87 assert(Amt < 32 && "Invalid rotate amount"); 88 return (Val >> Amt) | (Val << ((32-Amt)&31)); 93 static inline unsigned rotl32(unsigned Val, unsigned Amt) { argument 94 assert(Amt < 32 && "Invalid rotate amount"); 95 return (Val << Amt) | (Val >> ((32-Amt)&31));
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/external/clang/lib/StaticAnalyzer/Core/ |
H A D | BasicValueFactory.cpp | 181 uint64_t Amt = V2.getZExtValue(); 183 if (Amt > V1.getBitWidth()) 186 return &getValue( V1.operator<<( (unsigned) Amt )); 199 uint64_t Amt = V2.getZExtValue(); 201 if (Amt > V1.getBitWidth()) 204 return &getValue( V1.operator>>( (unsigned) Amt ));
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/external/llvm/include/llvm/ADT/ |
H A D | APSInt.h | 114 APSInt operator>>(unsigned Amt) const { 115 return IsUnsigned ? APSInt(lshr(Amt), true) : APSInt(ashr(Amt), false); 117 APSInt& operator>>=(unsigned Amt) { argument 118 *this = *this >> Amt; 145 APSInt& operator<<=(unsigned Amt) { argument 146 *this = *this << Amt;
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H A D | APInt.h | 841 APInt sshl_ov(unsigned Amt, bool &Overflow) const;
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/external/llvm/include/llvm/ |
H A D | BasicBlock.h | 277 void AdjustBlockAddressRefCount(int Amt) { argument 278 setValueSubclassData(getSubclassDataFromValue()+Amt);
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/external/clang/include/clang/Analysis/Analyses/ |
H A D | FormatString.h | 344 void setFieldWidth(const OptionalAmount &Amt) { argument 345 FieldWidth = Amt; 447 void setPrecision(const OptionalAmount &Amt) { argument 448 Precision = Amt;
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeIntegerTypes.cpp | 1260 /// and the shift amount is a constant 'Amt'. Expand the operation. 1261 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, argument 1274 if (Amt > VTBits) { 1276 } else if (Amt > NVTBits) { 1279 NVT, InL, DAG.getConstant(Amt-NVTBits, ShTy)); 1280 } else if (Amt == NVTBits) { 1283 } else if (Amt == 1 && 1293 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy)); 1296 DAG.getConstant(Amt, ShTy)), 1298 DAG.getConstant(NVTBits-Amt, ShT 1354 SDValue Amt = N->getOperand(1); local 1442 SDValue Amt = N->getOperand(1); local [all...] |
H A D | LegalizeTypes.h | 340 void ExpandShiftByConstant(SDNode *N, unsigned Amt,
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H A D | DAGCombiner.cpp | 245 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 3397 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { argument 3667 SDValue Amt = DAG.getConstant(ShiftAmt, local 3670 N0.getOperand(0), Amt); 3713 SDValue Amt = local 3717 N0.getOperand(0).getOperand(0), Amt); 4910 unsigned Amt = RHSC->getZExtValue(); local 4913 if (Amt >= Mask.getBitWidth()) break; 4914 APInt NewMask = Mask << Amt;
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H A D | TargetLowering.cpp | 3265 SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType())); local 3266 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt);
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H A D | SelectionDAGBuilder.cpp | 3127 unsigned Amt = ElementSize.logBase2(); local 3130 DAG.getConstant(Amt, IdxN.getValueType()));
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/external/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineCasts.cpp | 120 Value *Amt = 0; local 122 Amt = NumElements; 124 Amt = ConstantInt::get(AI.getArraySize()->getType(), Scale); 126 Amt = AllocaBuilder.CreateMul(Amt, NumElements); 132 Amt = AllocaBuilder.CreateAdd(Amt, Off); 135 AllocaInst *New = AllocaBuilder.CreateAlloca(CastElTy, Amt); 700 if (ConstantInt *Amt = dyn_cast<ConstantInt>(I->getOperand(1))) { 703 BitsToClear += Amt [all...] |
/external/llvm/lib/Target/ARM/InstPrinter/ |
H A D | ARMInstPrinter.cpp | 576 unsigned Amt = ShiftOp & 0x1f; local 578 O << ", asr #" << (Amt == 0 ? 32 : Amt); 579 else if (Amt) 580 O << ", lsl #" << Amt; local
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/external/clang/lib/Sema/ |
H A D | SemaChecking.cpp | 2110 bool HandleAmount(const analyze_format_string::OptionalAmount &Amt, unsigned k, 2113 const analyze_printf::OptionalAmount &Amt, 2140 const analyze_format_string::OptionalAmount &Amt, 2144 if (Amt.hasDataArgument()) { 2146 unsigned argIndex = Amt.getArgIndex(); 2150 getLocationOfByte(Amt.getStart()), 2166 const analyze_printf::ArgTypeResult &ATR = Amt.getArgType(S.Context); 2173 getLocationOfByte(Amt.getStart()), 2187 const analyze_printf::OptionalAmount &Amt, 2195 Amt 2139 HandleAmount( const analyze_format_string::OptionalAmount &Amt, unsigned k, const char *startSpecifier, unsigned specifierLen) argument 2185 HandleInvalidAmount( const analyze_printf::PrintfSpecifier &FS, const analyze_printf::OptionalAmount &Amt, unsigned type, const char *startSpecifier, unsigned specifierLen) argument 2495 const OptionalAmount &Amt = FS.getFieldWidth(); local [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 3855 SDValue Amt = Op.getOperand(2); local 3856 EVT AmtVT = Amt.getValueType(); 3859 DAG.getConstant(BitWidth, AmtVT), Amt); 3860 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt); 3863 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 3867 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt); 3884 SDValue Amt = Op.getOperand(2); local 3885 EVT AmtVT = Amt.getValueType(); 3888 DAG.getConstant(BitWidth, AmtVT), Amt); 3889 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); 3912 SDValue Amt = Op.getOperand(2); local 3984 BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, EVT VT, SelectionDAG &DAG, DebugLoc dl) argument [all...] |
/external/llvm/lib/VMCore/ |
H A D | ConstantFold.cpp | 249 ConstantInt *Amt = dyn_cast<ConstantInt>(CE->getOperand(1)); local 250 if (Amt == 0) 252 unsigned ShAmt = Amt->getZExtValue(); 271 ConstantInt *Amt = dyn_cast<ConstantInt>(CE->getOperand(1)); local 272 if (Amt == 0) 274 unsigned ShAmt = Amt->getZExtValue();
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H A D | Instructions.cpp | 794 static Value *getAISize(LLVMContext &Context, Value *Amt) { argument 795 if (!Amt) 796 Amt = ConstantInt::get(Type::getInt32Ty(Context), 1); 798 assert(!isa<BasicBlock>(Amt) && 800 assert(Amt->getType()->isIntegerTy() && 803 return Amt;
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/external/llvm/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.cpp | 162 unsigned Amt = ARM_AM::getAM2Offset(OffImm); local 164 if (ARM_AM::getSOImmVal(Amt) == -1) 170 .addReg(BaseReg).addImm(Amt) 172 } else if (Amt != 0) { 174 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 188 unsigned Amt = ARM_AM::getAM3Offset(OffImm); local 193 .addReg(BaseReg).addImm(Amt)
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/external/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 10247 SDValue Amt = Op.getOperand(1); local 10254 if (isSplatVector(Amt.getNode())) { 10255 SDValue SclrAmt = Amt->getOperand(0); 10306 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10349 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 10437 if (Amt.getOpcode() == ISD::BUILD_VECTOR) { 10442 Amt1Csts.push_back(Amt->getOperand(i)); 10444 Amt2Csts.push_back(Amt->getOperand(i)); 10452 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl); 10453 Amt2 = Extract128BitVector(Amt, DA [all...] |
H A D | X86InstrInfo.cpp | 1959 unsigned Amt = MI->getOperand(3).getImm(); local 1966 MI->getOperand(3).setImm(Size-Amt);
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/external/llvm/lib/Analysis/ |
H A D | ScalarEvolution.cpp | 3795 uint64_t Amt = BitWidth - CI->getZExtValue(); 3796 if (Amt == BitWidth) 3801 Amt)),
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/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 6810 unsigned Amt = Inst.getOperand(2).getImm(); local 6811 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi; 6812 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
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