Searched refs:Amt (Results 1 - 25 of 25) sorted by relevance

/external/clang/lib/Analysis/
H A DFormatString.cpp81 const OptionalAmount &Amt = ParseAmount(I, E); local
83 if (Amt.getHowSpecified() == OptionalAmount::NotSpecified) {
94 assert(Amt.getHowSpecified() == OptionalAmount::Constant);
100 if (Amt.getConstantAmount() == 0) {
108 return OptionalAmount(OptionalAmount::Arg, Amt.getConstantAmount() - 1,
131 const OptionalAmount Amt = local
135 if (Amt.isInvalid())
137 CS.setFieldWidth(Amt);
150 const OptionalAmount &Amt = ParseAmount(I, E); local
158 if (Amt
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H A DScanfFormatString.cpp123 const OptionalAmount &Amt = clang::analyze_format_string::ParseAmount(I, E); local
124 if (Amt.getHowSpecified() != OptionalAmount::NotSpecified) {
125 assert(Amt.getHowSpecified() == OptionalAmount::Constant);
126 FS.setFieldWidth(Amt);
H A DPrintfFormatString.cpp42 const OptionalAmount Amt = ParsePositionAmount(H, Start, Beg, E, local
44 if (Amt.isInvalid())
46 FS.setPrecision(Amt);
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAddressingModes.h86 static inline unsigned rotr32(unsigned Val, unsigned Amt) { argument
87 assert(Amt < 32 && "Invalid rotate amount");
88 return (Val >> Amt) | (Val << ((32-Amt)&31));
93 static inline unsigned rotl32(unsigned Val, unsigned Amt) { argument
94 assert(Amt < 32 && "Invalid rotate amount");
95 return (Val << Amt) | (Val >> ((32-Amt)&31));
/external/clang/lib/StaticAnalyzer/Core/
H A DBasicValueFactory.cpp181 uint64_t Amt = V2.getZExtValue();
183 if (Amt > V1.getBitWidth())
186 return &getValue( V1.operator<<( (unsigned) Amt ));
199 uint64_t Amt = V2.getZExtValue();
201 if (Amt > V1.getBitWidth())
204 return &getValue( V1.operator>>( (unsigned) Amt ));
/external/llvm/include/llvm/ADT/
H A DAPSInt.h114 APSInt operator>>(unsigned Amt) const {
115 return IsUnsigned ? APSInt(lshr(Amt), true) : APSInt(ashr(Amt), false);
117 APSInt& operator>>=(unsigned Amt) { argument
118 *this = *this >> Amt;
145 APSInt& operator<<=(unsigned Amt) { argument
146 *this = *this << Amt;
H A DAPInt.h841 APInt sshl_ov(unsigned Amt, bool &Overflow) const;
/external/llvm/include/llvm/
H A DBasicBlock.h277 void AdjustBlockAddressRefCount(int Amt) { argument
278 setValueSubclassData(getSubclassDataFromValue()+Amt);
/external/clang/include/clang/Analysis/Analyses/
H A DFormatString.h344 void setFieldWidth(const OptionalAmount &Amt) { argument
345 FieldWidth = Amt;
447 void setPrecision(const OptionalAmount &Amt) { argument
448 Precision = Amt;
/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp1260 /// and the shift amount is a constant 'Amt'. Expand the operation.
1261 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, argument
1274 if (Amt > VTBits) {
1276 } else if (Amt > NVTBits) {
1279 NVT, InL, DAG.getConstant(Amt-NVTBits, ShTy));
1280 } else if (Amt == NVTBits) {
1283 } else if (Amt == 1 &&
1293 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy));
1296 DAG.getConstant(Amt, ShTy)),
1298 DAG.getConstant(NVTBits-Amt, ShT
1354 SDValue Amt = N->getOperand(1); local
1442 SDValue Amt = N->getOperand(1); local
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H A DLegalizeTypes.h340 void ExpandShiftByConstant(SDNode *N, unsigned Amt,
H A DDAGCombiner.cpp245 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
3397 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { argument
3667 SDValue Amt = DAG.getConstant(ShiftAmt, local
3670 N0.getOperand(0), Amt);
3713 SDValue Amt = local
3717 N0.getOperand(0).getOperand(0), Amt);
4910 unsigned Amt = RHSC->getZExtValue(); local
4913 if (Amt >= Mask.getBitWidth()) break;
4914 APInt NewMask = Mask << Amt;
H A DTargetLowering.cpp3265 SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType())); local
3266 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt);
H A DSelectionDAGBuilder.cpp3127 unsigned Amt = ElementSize.logBase2(); local
3130 DAG.getConstant(Amt, IdxN.getValueType()));
/external/llvm/lib/Transforms/InstCombine/
H A DInstCombineCasts.cpp120 Value *Amt = 0; local
122 Amt = NumElements;
124 Amt = ConstantInt::get(AI.getArraySize()->getType(), Scale);
126 Amt = AllocaBuilder.CreateMul(Amt, NumElements);
132 Amt = AllocaBuilder.CreateAdd(Amt, Off);
135 AllocaInst *New = AllocaBuilder.CreateAlloca(CastElTy, Amt);
700 if (ConstantInt *Amt = dyn_cast<ConstantInt>(I->getOperand(1))) {
703 BitsToClear += Amt
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/external/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp576 unsigned Amt = ShiftOp & 0x1f; local
578 O << ", asr #" << (Amt == 0 ? 32 : Amt);
579 else if (Amt)
580 O << ", lsl #" << Amt; local
/external/clang/lib/Sema/
H A DSemaChecking.cpp2110 bool HandleAmount(const analyze_format_string::OptionalAmount &Amt, unsigned k,
2113 const analyze_printf::OptionalAmount &Amt,
2140 const analyze_format_string::OptionalAmount &Amt,
2144 if (Amt.hasDataArgument()) {
2146 unsigned argIndex = Amt.getArgIndex();
2150 getLocationOfByte(Amt.getStart()),
2166 const analyze_printf::ArgTypeResult &ATR = Amt.getArgType(S.Context);
2173 getLocationOfByte(Amt.getStart()),
2187 const analyze_printf::OptionalAmount &Amt,
2195 Amt
2139 HandleAmount( const analyze_format_string::OptionalAmount &Amt, unsigned k, const char *startSpecifier, unsigned specifierLen) argument
2185 HandleInvalidAmount( const analyze_printf::PrintfSpecifier &FS, const analyze_printf::OptionalAmount &Amt, unsigned type, const char *startSpecifier, unsigned specifierLen) argument
2495 const OptionalAmount &Amt = FS.getFieldWidth(); local
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/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp3855 SDValue Amt = Op.getOperand(2); local
3856 EVT AmtVT = Amt.getValueType();
3859 DAG.getConstant(BitWidth, AmtVT), Amt);
3860 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
3863 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3867 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
3884 SDValue Amt = Op.getOperand(2); local
3885 EVT AmtVT = Amt.getValueType();
3888 DAG.getConstant(BitWidth, AmtVT), Amt);
3889 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3912 SDValue Amt = Op.getOperand(2); local
3984 BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, EVT VT, SelectionDAG &DAG, DebugLoc dl) argument
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/external/llvm/lib/VMCore/
H A DConstantFold.cpp249 ConstantInt *Amt = dyn_cast<ConstantInt>(CE->getOperand(1)); local
250 if (Amt == 0)
252 unsigned ShAmt = Amt->getZExtValue();
271 ConstantInt *Amt = dyn_cast<ConstantInt>(CE->getOperand(1)); local
272 if (Amt == 0)
274 unsigned ShAmt = Amt->getZExtValue();
H A DInstructions.cpp794 static Value *getAISize(LLVMContext &Context, Value *Amt) { argument
795 if (!Amt)
796 Amt = ConstantInt::get(Type::getInt32Ty(Context), 1);
798 assert(!isa<BasicBlock>(Amt) &&
800 assert(Amt->getType()->isIntegerTy() &&
803 return Amt;
/external/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp162 unsigned Amt = ARM_AM::getAM2Offset(OffImm); local
164 if (ARM_AM::getSOImmVal(Amt) == -1)
170 .addReg(BaseReg).addImm(Amt)
172 } else if (Amt != 0) {
174 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
188 unsigned Amt = ARM_AM::getAM3Offset(OffImm); local
193 .addReg(BaseReg).addImm(Amt)
/external/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp10247 SDValue Amt = Op.getOperand(1); local
10254 if (isSplatVector(Amt.getNode())) {
10255 SDValue SclrAmt = Amt->getOperand(0);
10306 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10349 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10437 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10442 Amt1Csts.push_back(Amt->getOperand(i));
10444 Amt2Csts.push_back(Amt->getOperand(i));
10452 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl);
10453 Amt2 = Extract128BitVector(Amt, DA
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H A DX86InstrInfo.cpp1959 unsigned Amt = MI->getOperand(3).getImm(); local
1966 MI->getOperand(3).setImm(Size-Amt);
/external/llvm/lib/Analysis/
H A DScalarEvolution.cpp3795 uint64_t Amt = BitWidth - CI->getZExtValue();
3796 if (Amt == BitWidth)
3801 Amt)),
/external/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp6810 unsigned Amt = Inst.getOperand(2).getImm(); local
6811 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
6812 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);

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