Searched refs:MachineInstrBuilder (Results 1 - 25 of 31) sorted by relevance

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/external/llvm/lib/Target/CellSPU/
H A DSPUInstrBuilder.h11 // MachineInstrBuilder.h file to simplify generating frame and constant pool
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 inline const MachineInstrBuilder&
33 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0,
H A DSPUInstrInfo.cpp18 #include "llvm/CodeGen/MachineInstrBuilder.h"
360 MachineInstrBuilder MIB;
403 MachineInstrBuilder MIB2 = BuildMI(&MBB, DL, get(SPU::BR));
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrBuilder.h11 // MachineInstrBuilder.h file to simplify generating frame and constant pool
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 static inline const MachineInstrBuilder&
33 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0,
/external/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h43 class MachineInstrBuilder { class in namespace:llvm
46 MachineInstrBuilder() : MI(0) {} function in class:llvm::MachineInstrBuilder
47 explicit MachineInstrBuilder(MachineInstr *mi) : MI(mi) {} function in class:llvm::MachineInstrBuilder
58 MachineInstrBuilder &addReg(unsigned RegNo, unsigned flags = 0,
76 const MachineInstrBuilder &addImm(int64_t Val) const {
81 const MachineInstrBuilder &addCImm(const ConstantInt *Val) const {
86 const MachineInstrBuilder &addFPImm(const ConstantFP *Val) const {
91 const MachineInstrBuilder &addMBB(MachineBasicBlock *MBB,
97 const MachineInstrBuilder &addFrameIndex(int Idx) const {
102 const MachineInstrBuilder
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/external/llvm/lib/Target/X86/
H A DX86InstrBuilder.h11 // MachineInstrBuilder.h file to handle X86'isms in a clean way.
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
89 static inline const MachineInstrBuilder &
90 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) {
97 static inline const MachineInstrBuilder &
98 addOffset(const MachineInstrBuilder &MIB, int Offset) {
106 static inline const MachineInstrBuilder &
107 addRegOffset(const MachineInstrBuilder &MIB,
114 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder
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H A DX86InstrInfo.cpp25 #include "llvm/CodeGen/MachineInstrBuilder.h"
1582 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
2599 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
2633 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
2654 MachineInstrBuilder(MI).addReg(Reg, RegState::Undef)
2684 MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE));
2696 MachineInstrBuilder MIB(NewMI);
2722 MachineInstrBuilder MIB(NewMI);
2744 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
3248 MachineInstrBuilder MI
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H A DX86FrameLowering.cpp23 #include "llvm/CodeGen/MachineInstrBuilder.h"
1101 MachineInstrBuilder MIB =
1113 MachineInstrBuilder MIB =
/external/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h18 #include "llvm/CodeGen/MachineInstrBuilder.h"
302 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
307 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
312 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
318 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
H A DARMExpandPseudoInsts.cpp25 #include "llvm/CodeGen/MachineInstrBuilder.h"
55 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
73 MachineInstrBuilder &UseMI,
74 MachineInstrBuilder &DefMI) {
383 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
448 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
499 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
583 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
620 MachineInstrBuilder LO1
[all...]
H A DThumb1RegisterInfo.cpp28 #include "llvm/CodeGen/MachineInstrBuilder.h"
129 MachineInstrBuilder MIB =
241 const MachineInstrBuilder MIB =
260 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
268 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
419 MachineInstrBuilder MIB(&MI);
430 MachineInstrBuilder MIB(&MI);
459 MachineInstrBuilder MIB(&MI);
722 MachineInstrBuilder MIB(&MI);
H A DThumb1FrameLowering.cpp18 #include "llvm/CodeGen/MachineInstrBuilder.h"
280 MachineInstrBuilder MIB =
304 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH));
343 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP));
H A DThumb2ITBlockPass.cpp15 #include "llvm/CodeGen/MachineInstrBuilder.h"
185 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
H A DThumb2SizeReduction.cpp18 #include "llvm/CodeGen/MachineInstrBuilder.h"
455 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc));
516 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(),
673 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID);
764 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID);
H A DARMFrameLowering.cpp22 #include "llvm/CodeGen/MachineInstrBuilder.h"
216 MachineInstrBuilder MIB =
435 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
616 MachineInstrBuilder MIB =
622 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc),
681 MachineInstrBuilder MIB =
696 MachineInstrBuilder MIB =
779 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP)
H A DARMFastISel.cpp33 #include "llvm/CodeGen/MachineInstrBuilder.h"
219 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
221 const MachineInstrBuilder &MIB,
266 const MachineInstrBuilder &
267 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
662 MachineInstrBuilder MIB;
680 MachineInstrBuilder MIB;
935 const MachineInstrBuilder &MIB,
1064 MachineInstrBuilder MI
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H A DARMBaseInstrInfo.cpp27 #include "llvm/CodeGen/MachineInstrBuilder.h"
675 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
710 MachineInstrBuilder Mov;
732 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
808 MachineInstrBuilder MIB =
822 MachineInstrBuilder MIB =
952 MachineInstrBuilder MIB =
968 MachineInstrBuilder MIB =
1089 AddDefaultPred(MachineInstrBuilder(M
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H A DThumb2InstrInfo.cpp20 #include "llvm/CodeGen/MachineInstrBuilder.h"
279 MachineInstrBuilder MIB =
411 MachineInstrBuilder MIB(&MI);
H A DMLxExpansionPass.cpp20 #include "llvm/CodeGen/MachineInstrBuilder.h"
225 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg)
H A DARMLoadStoreOptimizer.cpp26 #include "llvm/CodeGen/MachineInstrBuilder.h"
349 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode))
779 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
1084 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(),
1090 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(),
1748 MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, MCID)
1762 MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, MCID)
/external/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp18 #include "llvm/CodeGen/MachineInstrBuilder.h"
159 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
239 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE))
382 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
/external/llvm/lib/CodeGen/
H A DMachineInstrBundle.cpp11 #include "llvm/CodeGen/MachineInstrBuilder.h"
109 MachineInstrBuilder MIB = BuildMI(MBB, FirstMI, FirstMI->getDebugLoc(),
H A DMachineSSAUpdater.cpp17 #include "llvm/CodeGen/MachineInstrBuilder.h"
190 MachineInstrBuilder MIB(InsertedPHI);
/external/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.cpp18 #include "llvm/CodeGen/MachineInstrBuilder.h"
393 MachineInstrBuilder MIB = BuildMI(MF, DL, get(XCore::DBG_VALUE))
/external/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp18 #include "llvm/CodeGen/MachineInstrBuilder.h"
121 MachineInstrBuilder MIB = BuildMI(MF, dl, get(SP::DBG_VALUE))
/external/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp21 #include "llvm/CodeGen/MachineInstrBuilder.h"
622 MachineInstrBuilder MIB = BuildMI(*MF, DL, II);

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