Searched refs:Order (Results 1 - 25 of 43) sorted by relevance

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/external/llvm/lib/CodeGen/
H A DAllocationOrder.cpp1 //===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
44 ArrayRef<uint16_t> Order = local
47 if (Order.empty())
52 unsigned *P = new unsigned[Order.size()];
54 for (unsigned i = 0; i != Order.size(); ++i)
55 if (!RCI.isReserved(Order[i]))
56 *P++ = Order[i];
H A DRegisterClassInfo.cpp80 if (!RCI.Order)
81 RCI.Order.reset(new unsigned[NumRegs]);
98 RCI.Order[N++] = PhysReg;
104 std::copy(CSRAlias.begin(), CSRAlias.end(), &RCI.Order[N]);
118 dbgs() << ' ' << PrintReg(RCI.Order[I], TRI);
H A DRegisterClassInfo.h32 OwningArrayPtr<unsigned> Order; member in struct:llvm::RegisterClassInfo::RCInfo
36 return makeArrayRef(Order.get(), NumRegs);
H A DScheduleDAGInstrs.cpp352 ExitSU.addPred(SDep(SU, SDep::Order, Latency,
599 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
604 I->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
610 BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
617 AliasChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
620 PendingLoads[k]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
623 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
628 I->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
645 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0, /*Reg=*/0,
661 J->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatenc
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H A DRegAllocGreedy.cpp449 AllocationOrder &Order,
451 Order.rewind();
453 while ((PhysReg = Order.next())) {
459 if (!PhysReg || Order.isHint(PhysReg))
467 if (Order.isHint(Hint) && !clobberedByRegMask(Hint)) {
485 unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost);
618 /// @param Order Physregs to try.
621 AllocationOrder &Order,
637 Order.rewind();
638 while (unsigned PhysReg = Order
448 tryAssign(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<LiveInterval*> &NewVRegs) argument
620 tryEvict(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<LiveInterval*> &NewVRegs, unsigned CostPerUseLimit) argument
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H A DRegAllocBasic.cpp246 ArrayRef<unsigned> Order = local
248 for (ArrayRef<unsigned>::iterator I = Order.begin(), E = Order.end(); I != E;
H A DAggressiveAntiDepBreaker.cpp623 ArrayRef<unsigned> Order = RegClassInfo.getOrder(SuperRC);
624 if (Order.empty()) {
632 RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size()));
635 unsigned EndR = ((OrigR == Order.size()) ? 0 : OrigR);
638 if (R == 0) R = Order.size();
640 const unsigned NewSuperReg = Order[R];
H A DCriticalAntiDepBreaker.cpp404 ArrayRef<unsigned> Order = RegClassInfo.getOrder(RC); local
405 for (unsigned i = 0; i != Order.size(); ++i) {
406 unsigned NewReg = Order[i];
/external/llvm/lib/CodeGen/SelectionDAG/
H A DSDNodeDbgValue.h50 unsigned Order; member in class:llvm::SDDbgValue
55 unsigned O) : mdPtr(mdP), Offset(off), DL(dl), Order(O),
65 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) {
72 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) {
103 unsigned getOrder() { return Order; }
H A DScheduleDAGSDNodes.cpp456 const SDep &dep = SDep(OpSU, isChain ? SDep::Order : SDep::Data,
670 unsigned Order) {
683 if (!Order || DVOrder == ++Order) {
702 unsigned Order = DAG->GetOrdering(N); local
703 if (!Order || !Seen.insert(Order)) {
713 Orders.push_back(std::make_pair(Order, (MachineInstr*)0));
717 Orders.push_back(std::make_pair(Order, prior(Emitter.getInsertPos())));
718 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order);
666 ProcessSDDbgValues(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter, SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders, DenseMap<SDValue, unsigned> &VRBaseMap, unsigned Order) argument
832 unsigned Order = Orders[i].first; local
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/external/aac/libAACdec/src/
H A Daacdec_tns.h113 UCHAR Order; member in struct:__anon24
H A Daacdec_tns.cpp176 filter->Order = order = (UCHAR) FDKreadBits(bs, isLongFlag ? 5 : 3);
179 if (filter->Order > TNS_MAXIMUM_ORDER){
180 filter->Order = order = TNS_MAXIMUM_ORDER;
356 if (filter->Order > 0)
361 pCoeff = &coeff[filter->Order-1];
365 for (i=0; i < filter->Order; i++)
371 for (i=0; i < filter->Order; i++)
404 filter->Order );
/external/icu4c/test/intltest/
H A Dtscoll.h26 struct Order struct in class:IntlTestCollator
51 Order *getOrders(CollationElementIterator &iter, int32_t &orderLength);
H A Dtscoll.cpp406 LocalArray<Order> orders(getOrders(iter, orderLength));
499 IntlTestCollator::Order *IntlTestCollator::getOrders(CollationElementIterator &iter, int32_t &orderLength)
503 LocalArray<Order> orders(new Order[maxSize]);
513 Order *temp = new Order[maxSize];
515 uprv_memcpy(temp, orders.getAlias(), size * sizeof(Order));
528 Order *temp = new Order[size];
530 uprv_memcpy(temp, orders.getAlias(), size * sizeof(Order));
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H A Dssearch.cpp674 struct Order struct
690 const Order *get(int32_t index) const;
699 Order *list;
707 list = new Order[listMax];
732 list = new Order[listMax];
763 Order *newList = new Order[listMax];
765 uprv_memcpy(newList, list, listSize * sizeof(Order));
777 const Order *OrderList::get(int32_t index) const
788 const Order *orde
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/external/llvm/include/llvm/CodeGen/
H A DScheduleDAG.h52 Order ///< Any other ordering dependency. enumerator in enum:llvm::SDep::Kind
67 /// Order - Additional information about Order dependencies.
81 } Order; member in union:llvm::SDep::__anon7148
107 assert(!isMustAlias && "isMustAlias only applies with SDep::Order!");
108 assert(!isArtificial && "isArtificial only applies with SDep::Order!");
111 case Order:
113 Contents.Order.isNormalMemory = isNormalMemory;
114 Contents.Order.isMustAlias = isMustAlias;
115 Contents.Order
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/external/llvm/lib/Target/
H A DTargetRegisterInfo.cpp74 ArrayRef<uint16_t> Order = RC->getRawAllocationOrder(MF); local
75 for (unsigned i = 0; i != Order.size(); ++i)
76 R.set(Order[i]);
/external/webkit/LayoutTests/http/conf/
H A Dapache2-debian-httpd.conf295 Order allow,deny
317 Order allow,deny
327 Order allow,deny
333 Order allow,deny
637 # Order deny,allow
H A Dapache2-httpd.conf316 Order allow,deny
338 Order allow,deny
348 Order allow,deny
354 Order allow,deny
658 # Order deny,allow
H A Dapache2-msys-httpd.conf317 Order allow,deny
339 Order allow,deny
349 Order allow,deny
355 Order allow,deny
659 # Order deny,allow
H A Dcygwin-httpd.conf348 Order allow,deny
370 Order allow,deny
380 Order allow,deny
386 Order allow,deny
690 # Order deny,allow
H A Dfedora-httpd.conf336 Order allow,deny
350 # Order allow,deny
354 # Order deny,allow
381 Order allow,deny
391 Order allow,deny
397 Order allow,deny
778 # Order deny,allow
790 # Order deny,allow
803 # Order deny,allow
H A Dhttpd.conf351 Order allow,deny
373 Order allow,deny
383 Order allow,deny
389 Order allow,deny
693 # Order deny,allow
/external/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp537 ArrayRef<Record*> Order = RC.getOrder(); local
546 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
547 Record *Reg = Order[i];
556 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
557 Record *Reg = Order[i];
727 ArrayRef<Record*> Order = RC.getOrder(); local
730 AllocatableRegs.insert(Order.begin(), Order.end());
844 << " const ArrayRef<uint16_t> Order[] = {\n"
853 << ");\n return Order[Selec
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/external/llvm/lib/Support/
H A DDwarf.cpp606 const char *llvm::dwarf::ArrayOrderString(unsigned Order) { argument
607 switch (Order) {

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