Searched refs:RA (Results 1 - 25 of 43) sorted by relevance

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/external/qemu/
H A Dppc-dis.c688 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
689 #define RA NSI + 1
693 /* As above, but 0 in the RA field means zero, not r0. */
694 #define RA0 RA + 1
697 /* The RA field in the DQ form lq instruction, which has special
702 /* The RA field in a D or X form instruction which is an updating
703 load, which means that the RA field may not be zero and may not
708 /* The RA field in an lmw instruction, which has special value
713 /* The RA field in a D or X form instruction which is an updating
714 store or an updating floating point load, which means that the RA
685 #define RA macro
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/external/qemu/tcg/ppc/
H A Dtcg-target.c397 #define RA(r) ((r)<<16) macro
407 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
408 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
449 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
451 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
453 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
461 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
464 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
493 tcg_out32 (s, LWZ | RT (0) | RA (reg));
494 tcg_out32 (s, MTSPR | RA (
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/external/qemu/tcg/ppc64/
H A Dtcg-target.c394 #define RA(r) ((r)<<16) macro
405 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
406 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
447 tcg_out32 (s, op | RA (ra) | RS (rs) | sh | mb);
453 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
455 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
457 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
477 if (h16) tcg_out32 (s, ORIS | RS (ret) | RA (ret) | h16);
478 if (l16) tcg_out32 (s, ORI | RS (ret) | RA (ret) | l16);
521 tcg_out32 (s, LD | RT (0) | RA (re
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/external/llvm/lib/Target/MBlaze/Disassembler/
H A DMBlazeDisassembler.cpp533 unsigned RA = getRA(insn); local
546 if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED)
550 instr.addOperand(MCOperand::CreateReg(RA));
554 if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED)
557 instr.addOperand(MCOperand::CreateReg(RA));
562 if (RD == UNSUPPORTED || RA == UNSUPPORTED)
565 instr.addOperand(MCOperand::CreateReg(RA));
579 if (RA == UNSUPPORTED)
582 instr.addOperand(MCOperand::CreateReg(RA));
595 if (RD == UNSUPPORTED || RA
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/external/llvm/test/MC/MBlaze/
H A Dmblaze_pattern.s6 # TYPE A: OPCODE RD RA RB FLAGS
H A Dmblaze_shift.s6 # TYPE A: OPCODE RD RA RB FLAGS
H A Dmblaze_fpu.s6 # TYPE A: OPCODE RD RA RB FLAGS
H A Dmblaze_memory.s6 # TYPE A: OPCODE RD RA RB FLAGS
H A Dmblaze_typeb.s6 # TYPE B: OPCODE RD RA IMMEDIATE
H A Dmblaze_special.s6 # TYPE A: OPCODE RD RA RB FLAGS
H A Dmblaze_typea.s6 # TYPE A: OPCODE RD RA RB FLAGS
/external/llvm/utils/TableGen/
H A DFixedLenDecoderEmitter.cpp370 void reportRegion(bitAttr_t RA, unsigned StartBit, unsigned BitIndex,
1010 void FilterChooser::reportRegion(bitAttr_t RA, unsigned StartBit, argument
1012 if (RA == ATTR_MIXED && AllowMixed)
1014 else if (RA == ATTR_ALL_SET && !AllowMixed)
1132 bitAttr_t RA = ATTR_NONE; local
1140 switch (RA) {
1147 RA = ATTR_ALL_SET;
1153 RA = ATTR_MIXED;
1162 reportRegion(RA, StartBit, BitIndex, AllowMixed);
1163 RA
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/external/llvm/lib/Transforms/IPO/
H A DDeadArgumentElimination.cpp145 void MarkValue(const RetOrArg &RA, Liveness L,
147 void MarkLive(const RetOrArg &RA);
149 void PropagateLiveness(const RetOrArg &RA);
571 /// MarkValue - This function marks the liveness of RA depending on L. If L is
573 /// such that RA will be marked live if any use in MaybeLiveUses gets marked
575 void DAE::MarkValue(const RetOrArg &RA, Liveness L, argument
578 case Live: MarkLive(RA); break;
585 Uses.insert(std::make_pair(*UI, RA));
610 void DAE::MarkLive(const RetOrArg &RA) { argument
611 if (LiveFunctions.count(RA
623 PropagateLiveness(const RetOrArg &RA) argument
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/external/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCTargetDesc.cpp47 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR; local
50 InitPPCMCRegisterInfo(X, RA, Flavour, Flavour);
/external/llvm/include/llvm/MC/
H A DMCRegisterInfo.h163 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, argument
170 RAReg = RA;
/external/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.cpp47 : MipsGenRegisterInfo(Mips::RA), Subtarget(ST), TII(tii) {}
88 Mips::SP, Mips::FP, Mips::RA
H A DMipsFrameLowering.cpp54 // . saved RA
321 MRI.setPhysRegUsed(Mips::RA);
323 MRI.setPhysRegUnused(Mips::RA);
H A DMipsDelaySlotFiller.cpp224 // Add RA to RegDefs to prevent users of RA from going into delay slot.
226 RegDefs.insert(Mips::RA);
/external/llvm/lib/Analysis/
H A DScalarEvolution.cpp501 const Argument *RA = cast<Argument>(RV); local
502 unsigned LArgNo = LA->getArgNo(), RArgNo = RA->getArgNo();
536 const APInt &RA = RC->getValue()->getValue(); local
537 unsigned LBitWidth = LA.getBitWidth(), RBitWidth = RA.getBitWidth();
540 return LA.ult(RA) ? -1 : 1;
545 const SCEVAddRecExpr *RA = cast<SCEVAddRecExpr>(RHS); local
548 const Loop *LLoop = LA->getLoop(), *RLoop = RA->getLoop();
557 unsigned LNumOps = LA->getNumOperands(), RNumOps = RA->getNumOperands();
563 long X = compare(LA->getOperand(i), RA->getOperand(i));
3851 const SCEV *RA
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/external/libffi/src/powerpc/
H A Ddarwin.S200 .byte 0x41 ; CIE RA Column
H A Ddarwin_closure.S259 .byte 0x41 ; CIE RA Column
H A Dlinux64.S151 .byte 0x41 # CIE RA Column
/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsBaseInfo.h198 case Mips::RA: case Mips::RA_64: case Mips::F31: case Mips::D31_64:
H A DMipsMCTargetDesc.cpp77 InitMipsMCRegisterInfo(X, Mips::RA);
/external/llvm/lib/Transforms/InstCombine/
H A DInstCombineSimplifyDemanded.cpp696 APInt RA = Rem->getValue().abs(); local
697 if (RA.isPowerOf2()) {
698 if (DemandedMask.ult(RA)) // srem won't affect demanded bits
701 APInt LowBits = RA - 1;

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