Searched refs:Reg0 (Results 1 - 6 of 6) sorted by relevance

/external/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp190 unsigned Reg0 = Op0.getReg(); local
191 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);
195 if (TargetRegisterInfo::isVirtualRegister(Reg0)) {
197 if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) {
/external/llvm/lib/CodeGen/
H A DTargetInstrInfoImpl.cpp78 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0; local
88 if (HasDef && Reg0 == Reg1 &&
91 Reg0 = Reg2;
93 } else if (HasDef && Reg0 == Reg2 &&
96 Reg0 = Reg1;
106 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead), SubReg0)
116 MI->getOperand(0).setReg(Reg0);
/external/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1650 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
1662 // FIXME: VLD1/VLD2 fixed increment doesn't need Reg0. Remove the reg0
1670 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1673 Ops.push_back(Reg0);
1686 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1699 Ops.push_back(Reg0);
1703 Ops.push_back(Reg0);
1776 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
1812 // FIXME: VST1/VST2 fixed increment doesn't need Reg0
1940 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
2036 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
2138 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
2379 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
2659 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
2675 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local
[all...]
H A DThumb2SizeReduction.cpp598 unsigned Reg0 = MI->getOperand(0).getReg(); local
604 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1)
607 if (Reg0 != Reg2) {
610 if (Reg1 != Reg0)
617 } else if (Reg0 != Reg1) {
621 CommOpIdx1 != 1 || MI->getOperand(CommOpIdx2).getReg() != Reg0)
627 if (Entry.LowRegs2 && !isARMLowRegister(Reg0))
/external/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp1028 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1030 O << "{" << getRegisterName(Reg0) << ", " << getRegisterName(Reg1) << "}";
1037 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1039 O << "{" << getRegisterName(Reg0) << ", " << getRegisterName(Reg1) << "}";
1073 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1075 O << "{" << getRegisterName(Reg0) << "[], " << getRegisterName(Reg1) << "[]}";
1105 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1107 O << "{" << getRegisterName(Reg0) << "[], " << getRegisterName(Reg1) << "[]}";
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp136 unsigned Reg0 = MI->getOperand(0).getReg(); local
144 if (Reg0 == Reg1) {
158 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); local
161 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))

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