| /external/llvm/lib/Target/ |
| H A D | TargetInstrInfo.cpp | 35 short RegClass = MCID.OpInfo[OpNum].RegClass; local
37 return TRI->getPointerRegClass(RegClass);
40 if (RegClass < 0)
44 return TRI->getRegClass(RegClass);
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| /external/llvm/include/llvm/CodeGen/ |
| H A D | RegisterScavenging.h | 111 unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const;
122 unsigned scavengeRegister(const TargetRegisterClass *RegClass,
124 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) { argument
125 return scavengeRegister(RegClass, MBBI, SPAdj);
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| H A D | MachineRegisterInfo.h | 293 unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
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| /external/llvm/lib/CodeGen/ |
| H A D | RegisterClassInfo.h | 41 OwningArrayPtr<RCInfo> RegClass; member in class:llvm::RegisterClassInfo
65 const RCInfo &RCI = RegClass[RC->getID()];
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| H A D | RegisterClassInfo.cpp | 41 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
75 RCInfo &RCI = RegClass[RC->getID()];
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| H A D | MachineRegisterInfo.cpp | 98 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ argument
99 assert(RegClass && "Cannot create register without RegClass!");
100 assert(RegClass->isAllocatable() &&
101 "Virtual register RegClass must be allocatable.");
110 VRegInfo[Reg].first = RegClass;
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| /external/llvm/include/llvm/MC/ |
| H A D | MCInstrDesc.h | 57 /// RegClass - This specifies the register class enumeration of the operand
61 int16_t RegClass; member in class:llvm::MCOperandInfo
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1455 SDValue RegClass = local
1459 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1467 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, MVT::i32); local
1470 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1478 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32); local
1481 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1490 SDValue RegClass = local
1496 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1506 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32); local
1511 const SDValue Ops[] = { RegClass, V
1521 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, MVT::i32); local
[all...] |
| /external/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.cpp | 961 CodeGenRegisterClass *RegClass = RegBank.getRegClasses()[i]; local
962 if (!RegClass->Allocatable)
965 const CodeGenRegister::Set &Regs = RegClass->getMembers();
1197 // Create a RegUnitSet for each RegClass that contains all units in the class
1202 // RegisterInfoEmitter will map each RegClass to its RegUnitClass and any
1206 // Compute a unique RegUnitSet for each RegClass.
1378 // Compute a unique set of RegUnitSets. One for each RegClass and inferred
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| H A D | CodeGenDAGPatterns.cpp | 1252 Record *RegClass = R->getValueAsDef("RegClass");
1254 return EEVT::TypeSet(T.getRegisterClass(RegClass).getValueTypes());
1540 Record *RegClass = ResultNode->getValueAsDef("RegClass"); local
1542 CDP.getTargetInfo().getRegisterClass(RegClass);
1603 Record *RegClass = OperandNode->getValueAsDef("RegClass"); local
1605 CDP.getTargetInfo().getRegisterClass(RegClass);
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGRRList.cpp | 269 unsigned &RegClass, unsigned &Cost) {
281 RegClass = RC->getID();
289 RegClass = RC->getID();
294 RegClass = TLI->getRepRegClassFor(VT)->getID();
265 GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos, const TargetLowering *TLI, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, unsigned &RegClass, unsigned &Cost) argument
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| /external/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 582 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
|