Searched refs:Rs (Results 1 - 5 of 5) sorted by relevance
/external/qemu/ |
H A D | trace.c | 895 int Rs = (insn >> 8) & 15; local 905 result += 2 + _interlock_use(Rm) + _interlock_use(Rs); 910 int Rs = (insn >> 8) & 15; local 920 result += 3 + _interlock_use(Rm) + _interlock_use(Rs); 1022 int Rs = (insn >> 8) & 15; local 1023 result += 1 + _interlock_use(Rs); 1225 /* the registers can also be Rs and Rn in some cases */
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/external/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCCodeEmitter.cpp | 1111 // shifted. The second is Rs, the amount to shift by, and the third specifies 1117 // {11-8} = Rs 1130 unsigned Rs = MO1.getReg(); local 1131 if (Rs) { 1148 // Encode the shift operation Rs. 1149 // Encode Rs bit[11:8]. 1151 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
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/external/llvm/lib/Target/ARM/ |
H A D | ARMCodeEmitter.cpp | 1015 unsigned Rs = MO1.getReg(); local 1016 if (Rs) { 1049 // Encode the shift operation Rs or shift_imm (except rrx). 1050 if (Rs) { 1051 // Encode Rs bit[11:8]. 1053 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift); 1426 // Encode Rs
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/external/v8/src/arm/ |
H A D | disasm-arm.cc | 332 } else if (format[1] == 's') { // 'rs: Rs register 696 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the 707 // The order of registers is: <RdLo>, <RdHi>, <Rm>, <Rs>
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/external/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 1121 unsigned Rs = fieldFromInstruction32(Val, 8, 4); local 1126 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
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