Searched refs:isDead (Results 1 - 25 of 41) sorted by relevance

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/external/llvm/lib/CodeGen/
H A DMachineInstrBundle.cpp160 if (MO.isDead()) {
166 if (!MO.isDead())
171 if (!MO.isDead()) {
189 bool isDead = DeadDefSet.count(Reg) || KilledDefSet.count(Reg); local
190 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) |
H A DDeadMachineInstructionElim.cpp45 bool isDead(const MachineInstr *MI) const;
54 bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const { function in class:DeadMachineInstructionElim
131 if (isDead(MI)) {
H A DExpandPostRAPseudos.cpp135 if (MI->getOperand(0).isDead())
156 if (DstMO.isDead() || SrcMO.isUndef() || MI->getNumOperands() > 2) {
172 if (DstMO.isDead())
H A DMachineInstr.cpp157 bool isKill, bool isDead, bool isUndef,
180 IsDead = isDead;
246 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
263 if (isKill() || isDead() || isUndef() || isInternalRead()) {
270 if (isDead()) {
817 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
1036 /// the specified register or -1 if it is not found. If isDead is true, defs
1040 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap, argument
1060 if (Found && (!isDead || M
156 ChangeToRegister(unsigned Reg, bool isDef, bool isImp, bool isKill, bool isDead, bool isUndef, bool isDebug) argument
[all...]
H A DPHIElimination.cpp204 bool isDead = MPhi->getOperand(0).isDead(); local
273 if (isDead) {
H A DTailDuplication.cpp93 void UpdateSuccessorsPHIs(MachineBasicBlock *FromBB, bool isDead,
208 bool isDead = MBB->pred_empty() && !MBB->hasAddressTaken(); local
210 UpdateSuccessorsPHIs(MBB, isDead, TDBBs, Succs);
213 if (isDead) {
443 TailDuplicatePass::UpdateSuccessorsPHIs(MachineBasicBlock *FromBB, bool isDead, argument
465 if (isDead) {
H A DRegAllocFast.cpp635 } else if (MO.isDead()) {
646 } else if (MO.isDead()) {
664 return MO.isKill() || MO.isDead();
677 return MO.isDead();
977 definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ?
1063 definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ?
H A DVirtRegMap.cpp158 if (MO.isDead())
H A DLiveIntervalAnalysis.cpp318 if (MO.isDead())
377 if (MO.isDead()) {
1198 } else if (MO.isDead()) {
1242 assert(!MO.isDead() && "Dead-defs not allowed in bundles.");
1264 if (LR->end.isDead()) {
1367 Tmp.end = LR->end.isDead() ? NewIdx.getDeadSlot() : NewIdx.getRegSlot();
H A DTwoAddressInstructionPass.cpp827 if (MO.isDef() && !MO.isDead())
883 bool isDead = NewKills.back().first.second; local
886 if (isDead)
989 if (!MO.isDead() && Defs.count(MOReg))
1101 if (!MO.isDead())
1208 if (!regBKilled && MI.getOperand(DstIdx).isDead() &&
H A DMachineVerifier.cpp831 if (MO->isDead())
1237 if (I->end.isDead()) {
1270 if (MOI->isDef() && MOI->isDead())
1274 if (I->end.isDead()) {
H A DRegisterScavenging.cpp169 if (!isPred && MO.isDead())
H A DLiveInterval.cpp308 bool isDead = true;
311 isDead = false;
314 if (isDead) {
H A DRegisterCoalescer.cpp817 assert(MO.isDef() && MO.isImplicit() && MO.isDead() &&
1886 bool isDead = true; local
1900 if (MO.isDead())
1904 isDead = false;
1908 if (isDead) {
H A DMachineLICM.cpp450 if (!MO.isDead())
942 } else if (!MO.isDead()) {
1444 if (MO.isReg() && MO.isDef() && !MO.isDead())
H A DMachineSink.cpp489 } else if (!MO.isDead()) {
/external/llvm/include/llvm/CodeGen/
H A DMachineOperand.h262 bool isDead() const { function in class:llvm::MachineOperand
503 /// operand. Note: This method ignores isKill and isDead properties.
515 bool isKill = false, bool isDead = false,
541 bool isKill = false, bool isDead = false,
550 Op.IsDead = isDead;
H A DMachineInstr.h709 /// the specified register or -1 if it is not found. If isDead is true, defs
715 bool isDead = false, bool Overlap = false,
720 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
722 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
/external/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h313 bool isDead = false) {
314 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
H A DThumb2SizeReduction.cpp659 if (HasCC && MI->getOperand(NumOps-1).isDead())
750 if (HasCC && MI->getOperand(NumOps-1).isDead())
819 if (!MO.isDead())
908 if (MO && !MO->isDead())
H A DARMExpandPseudoInsts.cpp387 bool DstIsDead = MI.getOperand(OpIdx).isDead();
518 DstIsDead = MI.getOperand(OpIdx).isDead();
617 bool DstIsDead = MI.getOperand(0).isDead();
867 bool DstIsDead = MI.getOperand(0).isDead();
891 bool DstIsDead = MI.getOperand(0).isDead();
949 bool DstIsDead = MI.getOperand(OpIdx).isDead();
H A DMLxExpansionPass.cpp210 bool DstDead = MI->getOperand(0).isDead();
/external/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp273 Src.isKill(), Src.isDead(), Src.isUndef(),
/external/smali/dexlib/src/main/java/org/jf/dexlib/Code/Analysis/
H A DAnalyzedInstruction.java142 public boolean isDead() { method in class:AnalyzedInstruction
/external/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp1478 if (MO.isDef()) return MO.isDead();
1541 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1560 bool isDead = MI->getOperand(0).isDead(); local
1637 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1646 if (isDead)
1672 bool isDead = MI->getOperand(0).isDead(); local
1694 .addReg(A, RegState::Define | getDeadRegState(isDead))
1712 .addReg(A, RegState::Define | getDeadRegState(isDead))
[all...]

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