Searched refs:isSEXTLoad (Results 1 - 4 of 4) sorted by relevance
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 586 bool isSEXTLoad, SDValue &Base, 631 bool isSEXTLoad = false; local 635 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 646 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 585 getIndexedAddressParts(SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG) argument
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/external/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 4747 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N)) 8733 bool isSEXTLoad, SDValue &Base, 8739 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) { 8792 bool isSEXTLoad, SDValue &Base, 8829 bool isSEXTLoad = false; local 8833 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 8843 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, 8846 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, 8868 bool isSEXTLoad = false; local 8872 isSEXTLoad 8732 getARMIndexedAddressParts(SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG) argument 8791 getT2IndexedAddressParts(SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG) argument [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | SelectionDAGNodes.h | 1807 /// isSEXTLoad - Returns true if the specified node is a SEXTLOAD. 1809 inline bool isSEXTLoad(const SDNode *N) { function in namespace:llvm::SDNode::ISD
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 2619 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4293 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
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