Searched refs:lui (Results 1 - 12 of 12) sorted by relevance
/external/openssl/crypto/sha/asm/ |
H A D | sha1-mips.pl | 288 lui $K,0x5a82 295 lui $K,0x6ed9 300 lui $K,0x8f1b 305 lui $K,0xca62
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H A D | sha1-mips.s | 40 lui $31,0x5a82 507 lui $31,0x6ed9 869 lui $31,0x8f1b 1271 lui $31,0xca62
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/external/webkit/Source/JavaScriptCore/assembler/ |
H A D | MacroAssemblerMIPS.h | 154 lui addrTemp, (offset + 0x8000) >> 16 161 m_assembler.lui(addrTempRegister, (address.offset + 0x8000) >> 16); 196 lui addrTemp, (offset + 0x8000) >> 16 202 m_assembler.lui(addrTempRegister, (dest.offset + 0x8000) >> 16); 385 lui addrTemp, (offset + 0x8000) >> 16 392 m_assembler.lui(addrTempRegister, (address.offset + 0x8000) >> 16); 474 lui addrTemp, (offset + 0x8000) >> 16 478 m_assembler.lui(addrTempRegister, (address.offset + 0x8000) >> 16); 491 lui addrTemp, (offset + 0x8000) >> 16 495 m_assembler.lui(addrTempRegiste [all...] |
H A D | MIPSAssembler.h | 257 lui(dest, imm >> 16); 263 void lui(RegisterID rt, int imm) function in class:JSC::MIPSAssembler 771 ASSERT((*insn & 0xffe00000) == 0x3c000000); // lui 804 ASSERT((*insn & 0xffe00000) == 0x3c000000); // lui 841 /* lui */ 848 } else if ((*insn & 0xffe00000) == 0x3c000000) { // lui 853 /* lui */ 893 lui $25, target >> 16 924 /* lui */ 949 /* lui [all...] |
/external/v8/test/cctest/ |
H A D | test-disasm-mips.cc | 220 COMPARE(lui(a0, 0x1), 221 "3c040001 lui a0, 0x1"); 222 COMPARE(lui(v0, 0xffff), 223 "3c02ffff lui v0, 0xffff");
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H A D | test-assembler-mips.cc | 136 // Test lui, ori, and addiu, used in the li pseudo-instruction. 140 __ lui(t0, 0x1234); 216 __ lui(v1, 0x8123); // 0x81230000 517 __ lui(t5, 0x3333);
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/external/v8/src/mips/ |
H A D | disasm-mips.cc | 868 Format(instr, "lui 'rt, 'imm16x");
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H A D | assembler-mips.cc | 182 // specially coded on MIPS means that it is a lui/ori instruction, and that is 1343 lui(at, src.offset_ >> kLuiShift); 1449 void Assembler::lui(Register rd, int32_t j) { function in class:v8::Assembler 2100 lui(at, (imm32 & kHiMask) >> kLuiShift); 2127 // Interpret 2 instructions generated by li: lui/ori 2149 // On Mips, a target address is stored in a lui/ori instruction pair, each 2168 // Must use 2 instructions to insure patchable code => just use lui and ori. 2169 // lui rt, upper-16. 2254 // Address pc points to lui/ori instructions.
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H A D | assembler-mips.h | 577 // has already deserialized the lui/ori instructions etc. 726 void lui(Register rd, int32_t j);
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H A D | macro-assembler-mips.cc | 783 lui(rd, (j.imm32_ >> kLuiShift) & kImm16Mask); 785 lui(rd, (j.imm32_ >> kLuiShift) & kImm16Mask); 794 lui(rd, (j.imm32_ >> kLuiShift) & kImm16Mask); 1284 lui(mask, 0x8000); 2628 lui(at, (imm32 & kHiMask) >> kLuiShift); 2648 lui(at, (imm32 & kHiMask) >> kLuiShift); 5017 // At this point scratch is a lui(at, ...) instruction. 5020 Check(eq, "The instruction to patch should be a lui.", 5039 // Update the I-cache so the new lui and ori can be executed. 5049 Check(eq, "The instruction should be a lui [all...] |
/external/openssl/crypto/aes/asm/ |
H A D | aes-mips.s | 941 lui $2,0x8080 946 lui $25,0x1b1b
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H A D | aes-mips.pl | 1158 lui $x80808080,0x8080 1163 lui $x1b1b1b1b,0x1b1b
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