Searched refs:lwl (Results 1 - 14 of 14) sorted by relevance

/external/openssl/crypto/sha/asm/
H A Dsha1-mips.s39 lwl $8,3($5)
52 lwl $9,1*4+3($5)
76 lwl $10,2*4+3($5)
100 lwl $11,3*4+3($5)
124 lwl $12,4*4+3($5)
148 lwl $13,5*4+3($5)
172 lwl $14,6*4+3($5)
196 lwl $15,7*4+3($5)
220 lwl $16,8*4+3($5)
244 lwl
[all...]
H A Dsha256-mips.s50 lwl $8,3($5)
52 lwl $9,7($5)
104 lwl $10,11($5)
156 lwl $11,15($5)
208 lwl $12,19($5)
260 lwl $13,23($5)
312 lwl $14,27($5)
364 lwl $15,31($5)
416 lwl $16,35($5)
468 lwl
[all...]
H A Dsha1-mips.pl13 # to deploy lwl/lwr pair to load unaligned input. One could have
109 lwl @X[$j],$j*4+$MSB($inp)
287 lwl @X[0],$MSB($inp)
/external/openssl/crypto/aes/asm/
H A Daes-mips.s41 lwl $12,2($1) # Te1[s1>>16]
42 lwl $13,2($2) # Te1[s2>>16]
43 lwl $14,2($24) # Te1[s3>>16]
44 lwl $15,2($25) # Te1[s0>>16]
62 lwl $16,1($1) # Te2[s2>>8]
63 lwl $17,1($2) # Te2[s3>>8]
64 lwl $18,1($24) # Te2[s0>>8]
65 lwl $19,1($25) # Te2[s1>>8]
83 lwl $20,0($1) # Te3[s3]
84 lwl
[all...]
H A Daes-mips.pl18 # additional rotations. Rotations are implemented with lwl/lwr pairs,
142 lwl $t0,3($i0) # Te1[s1>>16]
143 lwl $t1,3($i1) # Te1[s2>>16]
144 lwl $t2,3($i2) # Te1[s3>>16]
145 lwl $t3,3($i3) # Te1[s0>>16]
163 lwl $t4,2($i0) # Te2[s2>>8]
164 lwl $t5,2($i1) # Te2[s3>>8]
165 lwl $t6,2($i2) # Te2[s0>>8]
166 lwl $t7,2($i3) # Te2[s1>>8]
184 lwl
[all...]
/external/qemu/target-mips/
H A Dhelper.h13 DEF_HELPER_3(lwl, tl, tl, tl, int)
H A Dtranslate.c1101 gen_helper_3i(lwl, t1, t1, t0, ctx->mem_idx);
1103 opn = "lwl";
/external/v8/src/mips/
H A Ddisasm-mips.cc878 Format(instr, "lwl 'rt, 'imm16s('rs)");
H A Dassembler-mips.h749 void lwl(Register rd, const MemOperand& rs);
H A Dassembler-mips.cc1399 void Assembler::lwl(Register rd, const MemOperand& rs) { function in class:v8::Assembler
H A Dcode-stubs-mips.cc5810 // This loop uses lwl and lwr instructions. These instructions
5817 __ lwl(scratch1, MemOperand(src, -1));
/external/webkit/Source/JavaScriptCore/assembler/
H A DMacroAssemblerMIPS.h538 lwl dest, address.offset(addrTemp)
541 lwl dest, address.offset+3(addrTemp)
547 m_assembler.lwl(dest, addrTempRegister, address.offset);
550 m_assembler.lwl(dest, addrTempRegister, address.offset + 3);
575 m_assembler.lwl(dest, addrTempRegister, 0);
578 m_assembler.lwl(dest, addrTempRegister, 3);
H A DMIPSAssembler.h427 void lwl(RegisterID rt, RegisterID rs, int offset) function in class:JSC::MIPSAssembler
/external/v8/test/cctest/
H A Dtest-assembler-mips.cc867 __ lwl(t0, MemOperand(a0, OFFSET_OF(T, mem_init)) );
871 __ lwl(t1, MemOperand(a0, OFFSET_OF(T, mem_init) + 1) );
875 __ lwl(t2, MemOperand(a0, OFFSET_OF(T, mem_init) + 2) );
879 __ lwl(t3, MemOperand(a0, OFFSET_OF(T, mem_init) + 3) );

Completed in 141 milliseconds