| /external/kernel-headers/original/asm-x86/ |
| H A D | msr.h | 47 asm volatile("wrmsr" : : "c" (msr), "A"(val));
54 asm volatile("2: wrmsr ; xorl %0,%0\n"
100 static inline void wrmsr(u32 __msr, u32 __low, u32 __high) function
110 /* wrmsr with exception handling */
132 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
154 wrmsr(msr_no, l, h);
191 #define wrmsr(msr,val1,val2) \ macro
192 __asm__ __volatile__("wrmsr" \
196 #define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32)
219 #define write_tsc(val1,val2) wrmsr(
[all...] |
| H A D | paravirt.h | 116 err = 0/-EFAULT. wrmsr returns 0/-EFAULT. */
577 #define wrmsr(msr,val1,val2) do { \ macro
586 #define wrmsrl(msr,val) wrmsr(msr, (u32)((u64)(val)), ((u64)(val))>>32)
616 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
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| H A D | processor_32.h | 507 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
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| /external/oprofile/module/x86/ |
| H A D | op_model_p4.c | 362 #define ESCR_WRITE(escr, high, ev, i) do {wrmsr(ev->bindings[(i)].escr_address, (escr), (high));} while (0)
373 #define CCCR_WRITE(low, high, i) do {wrmsr(p4_counters[(i)].cccr_address, (low), (high));} while (0)
378 #define CTR_WRITE(l, i) do {wrmsr(p4_counters[(i)].counter_address, -(u32)(l), -1);} while (0)
566 wrmsr(p4_counters[VIRT_CTR(stag, i)].cccr_address, low, high);
574 wrmsr(p4_unused_cccr[i], low, high);
580 wrmsr(addr, 0, 0);
585 wrmsr(MSR_P4_IQ_ESCR0, 0, 0);
586 wrmsr(MSR_P4_IQ_ESCR1, 0, 0);
591 wrmsr(addr, 0, 0);
596 wrmsr(add
[all...] |
| H A D | op_apic.c | 122 wrmsr(MSR_IA32_APICBASE, msr_low | (1 << 11), msr_high);
145 wrmsr(MSR_IA32_APICBASE, msr_low & ~(1 << 11), msr_high);
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| H A D | op_model_athlon.c | 21 #define CTR_WRITE(l, msrs, c) do {wrmsr(msrs->counters.addrs[(c)], -(u32)(l), 0xffff);} while (0)
25 #define CTRL_WRITE(l, h, msrs, c) do {wrmsr(msrs->controls.addrs[(c)], (l), (h));} while (0)
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| H A D | op_model_ppro.c | 21 #define CTR_WRITE(l, msrs, c) do {wrmsr(msrs->counters.addrs[(c)], -(u32)(l), -1);} while (0)
25 #define CTRL_WRITE(l, h, msrs, c) do {wrmsr((msrs->controls.addrs[(c)]), (l), (h));} while (0)
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| H A D | op_msr.h | 16 * magically cloberred by wrmsr */
18 #undef wrmsr macro
19 #define wrmsr(msr, val1, val2) \ macro
20 __asm__ __volatile__("wrmsr" \
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| H A D | op_nmi.c | 251 wrmsr(controls->addrs[i],
259 wrmsr(counters->addrs[i],
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| /external/qemu-pc-bios/bochs/bios/ |
| H A D | rombios32start.S | 61 wrmsr
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| H A D | rombios32.c | 165 static void wrmsr(unsigned index, uint64_t val) function
167 asm volatile ("wrmsr" : : "c"(index), "A"(val));
462 wrmsr(index, val);
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| /external/qemu/target-i386/ |
| H A D | helper.h | 85 DEF_HELPER_0(wrmsr, void)
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| /external/valgrind/main/perf/ |
| H A D | tinycc.c | 3212 DEF_ASM_OP0(wrmsr, 0x0f30)
3669 DEF_ASM_OP0(wrmsr, 0x0f30)
4544 DEF_ASM_OP0(wrmsr, 0x0f30)
5001 DEF_ASM_OP0(wrmsr, 0x0f30)
15251 DEF_ASM_OP0(wrmsr, 0x0f30)
15713 DEF_ASM_OP0(wrmsr, 0x0f30)
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| /external/llvm/test/MC/X86/ |
| H A D | x86-32-coverage.s | 4387 // CHECK: wrmsr
4389 wrmsr
14094 // CHECK: wrmsr
14095 wrmsr
|