/external/llvm/lib/Target/X86/Utils/ |
H A D | X86ShuffleDecode.h | 30 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 38 void DecodePSHUFMask(EVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 40 void DecodePSHUFHWMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 42 void DecodePSHUFLWMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 47 void DecodeSHUFPMask(EVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 60 void DecodeVPERM2X128Mask(EVT VT, unsigned Imm,
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H A D | X86ShuffleDecode.cpp | 23 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { argument 31 unsigned ZMask = Imm & 15; 32 unsigned CountD = (Imm >> 4) & 3; 33 unsigned CountS = (Imm >> 6) & 3; 67 void DecodePSHUFMask(EVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { argument 73 int NewImm = Imm; 79 if (NumLaneElts == 4) NewImm = Imm; // reload imm 83 void DecodePSHUFHWMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { argument 89 ShuffleMask.push_back(4+(Imm & 3)); 90 Imm >> 94 DecodePSHUFLWMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 108 DecodeSHUFPMask(EVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 170 DecodeVPERM2X128Mask(EVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument [all...] |
/external/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMAddressingModes.h | 112 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { 113 return ShOp | (Imm << 3); 124 static inline unsigned getSOImmValImm(unsigned Imm) { 125 return Imm & 0xFF; 129 static inline unsigned getSOImmValRot(unsigned Imm) { 130 return (Imm >> 8) * 2; 133 /// getSOImmValRotate - Try to handle Imm with an immediate shifter operand, 137 static inline unsigned getSOImmValRotate(unsigned Imm) { argument 140 if ((Imm & ~255U) == 0) return 0; 143 unsigned TZ = CountTrailingZeros_32(Imm); 218 getThumbImmValShift(unsigned Imm) argument 237 getThumbImm16ValShift(unsigned Imm) argument 271 unsigned u, Vs, Imm; local 335 isT2SOImmTwoPartVal(unsigned Imm) argument 362 getT2SOImmTwoPartFirst(unsigned Imm) argument 379 getT2SOImmTwoPartSecond(unsigned Imm) argument [all...] |
H A D | ARMMCCodeEmitter.cpp | 82 unsigned &Reg, unsigned &Imm, 432 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const { 453 Imm = SImm; 950 unsigned Imm = MO1.getImm(); local 951 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add; 953 uint32_t Binary = ARM_AM::getAM2Offset(Imm); 956 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); 984 unsigned Imm = MO1.getImm(); local 985 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; 987 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm); 431 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const argument 1019 unsigned Imm = MO2.getImm(); local 1367 const MCOperand &Imm = MI.getOperand(Op + 1); local 1390 const MCOperand &Imm = MI.getOperand(Op + 1); local 1416 const MCOperand &Imm = MI.getOperand(Op + 1); local [all...] |
H A D | ARMMCTargetDesc.cpp | 200 int64_t Imm = Inst.getOperand(0).getImm(); 202 return Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
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/external/llvm/lib/Target/Mips/ |
H A D | MipsAnalyzeImmediate.cpp | 29 void MipsAnalyzeImmediate::GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, argument 31 GetInstSeqLs((Imm + 0x8000ULL) & 0xffffffffffff0000ULL, RemSize, SeqLs); 32 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL)); 35 void MipsAnalyzeImmediate::GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, argument 37 GetInstSeqLs(Imm & 0xffffffffffff0000ULL, RemSize, SeqLs); 38 AddInstr(SeqLs, Inst(ORi, Imm & 0xffffULL)); 41 void MipsAnalyzeImmediate::GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, argument 43 unsigned Shamt = CountTrailingZeros_64(Imm); 44 GetInstSeqLs(Imm >> Shamt, RemSize - Shamt, SeqLs); 48 void MipsAnalyzeImmediate::GetInstSeqLs(uint64_t Imm, unsigne argument 125 Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu) argument [all...] |
H A D | MipsAnalyzeImmediate.h | 25 /// Analyze - Get an instrucion sequence to load immediate Imm. The last 28 const InstSeq &Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu); 36 /// load immediate Imm 37 void GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); 40 /// load immediate Imm 41 void GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); 44 /// load immediate Imm 45 void GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); 47 /// GetInstSeqLs - Get instrucion sequences to load immediate Imm. 48 void GetInstSeqLs(uint64_t Imm, unsigne [all...] |
/external/llvm/lib/MC/ |
H A D | MCInstrAnalysis.cpp | 19 int64_t Imm = Inst.getOperand(0).getImm(); 20 return Addr+Size+Imm;
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 62 inline SDValue getI32Imm(unsigned Imm) { argument 63 return CurDAG->getTargetConstant(Imm, MVT::i32); 68 inline SDValue getI64Imm(uint64_t Imm) { argument 69 return CurDAG->getTargetConstant(Imm, MVT::i64); 73 inline SDValue getSmallIPtrImm(unsigned Imm) { argument 74 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy()); 258 static bool isIntS16Immediate(SDNode *N, short &Imm) { argument 262 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue(); 264 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue(); 266 return Imm 269 isIntS16Immediate(SDValue Op, short &Imm) argument 276 isInt32Immediate(SDNode *N, unsigned &Imm) argument 286 isInt64Immediate(SDNode *N, uint64_t &Imm) argument 296 isInt32Immediate(SDValue N, unsigned &Imm) argument 304 isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) argument 451 unsigned Imm; local 492 uint64_t Imm; local 609 unsigned Imm; local 745 int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue(); local 850 unsigned Imm; local 928 unsigned Imm, Imm2, SH, MB, ME; local 978 unsigned Imm, SH, MB, ME; local 990 unsigned Imm, SH, MB, ME; local [all...] |
/external/llvm/utils/TableGen/ |
H A D | PseudoLoweringEmitter.h | 23 enum MapKind { Operand, Imm, Reg }; enumerator in enum:llvm::PseudoLoweringEmitter::OpData::MapKind 27 uint64_t Imm; // Integer immedate value. member in union:llvm::PseudoLoweringEmitter::OpData::__anon7997
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H A D | PseudoLoweringEmitter.cpp | 58 OperandMap[BaseIdx + i].Kind = OpData::Imm; 59 OperandMap[BaseIdx + i].Data.Imm = II->getValue(); 189 case OpData::Imm: 191 << Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n";
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H A D | CodeGenInstruction.h | 286 int64_t Imm; member in struct:llvm::CodeGenInstAlias::ResultOperand 295 ResultOperand(int64_t I) : Imm(I), Kind(K_Imm) {} 304 int64_t getImm() const { assert(isImm()); return Imm; }
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/external/llvm/lib/Target/MBlaze/ |
H A D | MBlazeISelDAGToDAG.cpp | 89 inline SDValue getI32Imm(unsigned Imm) { argument 90 return CurDAG->getTargetConstant(Imm, MVT::i32); 100 static bool isIntS32Immediate(SDNode *N, int32_t &Imm) { argument 105 Imm = (int32_t)cast<ConstantSDNode>(N)->getZExtValue(); 107 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue(); 109 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue(); 112 static bool isIntS32Immediate(SDValue Op, int32_t &Imm) { argument 113 return isIntS32Immediate(Op.getNode(), Imm); 166 uint32_t Imm = CN->getZExtValue(); local 167 Disp = CurDAG->getTargetConstant(Imm, C [all...] |
/external/llvm/lib/VMCore/ |
H A D | AutoUpgrade.cpp | 134 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); local 139 Idxs.push_back(Builder.getInt32((Imm >> i) & 0x1)); 143 Idxs.push_back(Builder.getInt32(((Imm >> (l+i)) & 0x1) + l)); 146 Idxs.push_back(Builder.getInt32((Imm >> (2 * i)) & 0x3)); 150 Idxs.push_back(Builder.getInt32(((Imm >> (2 * i)) & 0x3) + l));
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/external/llvm/include/llvm/CodeGen/ |
H A D | FastISel.h | 191 uint64_t Imm); 212 uint64_t Imm); 221 uint64_t Imm, MVT ImmType); 229 uint64_t Imm); 275 uint64_t Imm); 300 uint64_t Imm); 306 uint64_t Imm);
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/external/llvm/lib/Target/ARM/InstPrinter/ |
H A D | ARMInstPrinter.cpp | 476 unsigned Imm = MO.getImm(); local 477 O << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff); 492 unsigned Imm = MO.getImm(); local 493 O << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2); 585 unsigned Imm = MI->getOperand(OpNum).getImm(); local 586 if (Imm == 0) 588 assert(Imm > 0 && Imm < 3 589 O << ", lsl #" << Imm; local 594 unsigned Imm = MI->getOperand(OpNum).getImm(); local 599 O << ", asr #" << Imm; local 749 unsigned Imm = MI->getOperand(OpNum).getImm(); local [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FastISel.cpp | 388 uint64_t Imm = CI->getZExtValue(); local 393 isPowerOf2_64(Imm)) { 394 Imm = Log2_64(Imm); 400 isPowerOf2_64(Imm)) { 401 --Imm; 406 Op0IsKill, Imm, VT.getSimpleVT()); 1072 unsigned FastISel::FastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) { 1084 uint64_t /*Imm*/) { 1099 uint64_t /*Imm*/) { 1107 FastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t Imm, MVT ImmType) argument 1220 FastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument 1285 FastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm) argument 1309 FastEmitInst_i(unsigned MachineInstOpcode, const TargetRegisterClass *RC, uint64_t Imm) argument [all...] |
/external/llvm/lib/Target/MBlaze/AsmParser/ |
H A D | MBlazeAsmParser.cpp | 95 } Imm; member in union:__anon7591::MBlazeOperand::__anon7592 119 Imm = o.Imm; 146 return Imm.Val; 238 Op->Imm.Val = Val; 246 Op->Imm.Val = Val;
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/external/llvm/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 124 uint64_t Imm); 133 uint64_t Imm); 136 uint64_t Imm); 366 uint64_t Imm) { 373 .addImm(Imm)); 377 .addImm(Imm)); 411 uint64_t Imm) { 419 .addImm(Imm)); 424 .addImm(Imm)); 434 uint64_t Imm) { 363 FastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument 407 FastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm) argument 432 FastEmitInst_i(unsigned MachineInstOpcode, const TargetRegisterClass *RC, uint64_t Imm) argument 516 int Imm; local 572 unsigned Imm = (unsigned)~(CI->getSExtValue()); local 959 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset; local 973 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset; local 1320 uint64_t Imm = CI->getZExtValue(); local 1376 int Imm = 0; local 1637 int Imm = 0; local [all...] |
H A D | Thumb1RegisterInfo.cpp | 236 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7) 343 unsigned DestReg, int Imm, 347 bool isSub = Imm < 0; 348 if (isSub) Imm = -Imm; 351 int ThisVal = (Imm > Chunk) ? Chunk : Imm; 352 Imm -= ThisVal; 356 if (Imm > 0) 357 emitThumbRegPlusImmediate(MBB, MBBI, dl, DestReg, DestReg, Imm, TI 341 emitThumbConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, unsigned DestReg, int Imm, const TargetInstrInfo &TII, const Thumb1RegisterInfo& MRI, DebugLoc dl) argument [all...] |
H A D | ARMCodeEmitter.cpp | 358 unsigned getShiftOp(unsigned Imm) const ; 417 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const { 418 switch (ARM_AM::getAM2ShiftOpc(Imm)) { 1879 unsigned Imm = getMachineOpValue(MI, 1); 1881 Binary |= (Imm & 0x780000) >> 19; 1883 Binary |= (Imm & 0x3800000) >> 7; 1988 unsigned Imm = MI.getOperand(1).getImm(); 1989 unsigned Op = (Imm >> 12) & 1; 1990 unsigned Cmode = (Imm >> 8) & 0xf; 1991 unsigned I = (Imm >> [all...] |
H A D | ARMISelLowering.h | 293 virtual bool isLegalICmpImmediate(int64_t Imm) const; 299 virtual bool isLegalAddImmediate(int64_t Imm) const; 370 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
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/external/llvm/lib/Target/X86/ |
H A D | X86RegisterInfo.cpp | 367 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) { argument 369 if (isInt<8>(Imm)) 373 if (isInt<8>(Imm)) 379 static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) { argument 381 if (isInt<8>(Imm)) 385 if (isInt<8>(Imm)) 510 int Imm = (int)(MI.getOperand(i + 3).getImm()); local 511 int Offset = FIOffset + Imm; 512 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
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/external/llvm/lib/Target/PTX/InstPrinter/ |
H A D | PTXInstPrinter.cpp | 174 double Imm = Op.getFPImm(); local 175 APFloat FPImm(Imm);
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/external/valgrind/main/VEX/priv/ |
H A D | host_ppc_defs.c | 399 op->Prh.Imm.syned = syned; 400 op->Prh.Imm.imm16 = imm16; 418 if (op->Prh.Imm.syned) 419 vex_printf("%d", (Int)(Short)op->Prh.Imm.imm16); 421 vex_printf("%u", (UInt)(UShort)op->Prh.Imm.imm16); 464 op->Pri.Imm = imm64; 477 vex_printf("0x%llx", dst->Pri.Imm); 1350 ppLoadImm(hregPPC_GPR3(mode64), i->Pin.Goto.dst->Pri.Imm, 1368 ppLoadImm(i->Pin.CMov.dst, i->Pin.CMov.src->Pri.Imm, mode64); 2701 vassert(srcR->Prh.Imm [all...] |