1a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden%verify "executed"
2a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden%verify "basic lt, gt, eq */
3a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden%verify "left arg NaN"
4a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden%verify "right arg NaN"
5a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden    /*
6a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden     * Compare two floating-point values.  Puts 0, 1, or -1 into the
7a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden     * destination register based on the results of the comparison.
8a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden     *
9a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden     * int compare(x, y) {
10a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden     *     if (x == y) {
11a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden     *         return 0;
12a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden     *     } else if (x < y) {
13a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden     *         return -1;
14a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden     *     } else if (x > y) {
15a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden     *         return 1;
16a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden     *     } else {
17a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden     *         return 1;
18a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden     *     }
19a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden     * }
20a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden     */
21a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden    /* op vAA, vBB, vCC */
22a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden    FETCH(r0, 1)                        @ r0<- CCBB
238fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden    mov     r9, rINST, lsr #8           @ r9<- AA
24a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden    and     r2, r0, #255                @ r2<- BB
25a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden    mov     r3, r0, lsr #8              @ r3<- CC
268fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden    VREG_INDEX_TO_ADDR(r2, r2)          @ r2<- &vBB
27a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden    VREG_INDEX_TO_ADDR(r3, r3)          @ r3<- &vCC
288fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden    fldd    d0, [r2]                    @ d0<- vBB
29a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden    fldd    d1, [r3]                    @ d1<- vCC
30a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden    fcmped  d0, d1                      @ compare (vBB, vCC)
31a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden    FETCH_ADVANCE_INST(2)               @ advance rPC, load rINST
32a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden    mov     r0, #1                      @ r0<- 1 (default)
33a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden    GET_INST_OPCODE(ip)                 @ extract opcode from rINST
34a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden    fmstat                              @ export status flags
35a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden    mvnmi   r0, #0                      @ (less than) r1<- -1
36a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden    moveq   r0, #0                      @ (equal) r1<- 0
378fd923e066208c4bbebe5677cac4d11a629bac1bAndy McFadden    b       .L${opcode}_finish          @ argh
38a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden
39a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden%break
40a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden.L${opcode}_finish:
41a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden    SET_VREG(r0, r9)                    @ vAA<- r0
42a80b76553c2b9f33c4063ae8c69c5362d961de81Andy McFadden    GOTO_OPCODE(ip)                     @ jump to next instruction
43