1633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 2633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * This file is subject to the terms and conditions of the GNU General Public 3633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * License. See the file "COPYING" in the main directory of this archive 4633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * for more details. 5633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * 6633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle 7633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Copyright (C) 1999 by Silicon Graphics, Inc. 8633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Copyright (C) 2001 MIPS Technologies, Inc. 9633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Copyright (C) 2002 Maciej W. Rozycki 10633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * 11633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Some useful macros for MIPS assembler code 12633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * 13633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Some of the routines below contain useless nops that will be optimized 14633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * away by gas in -O mode. These nops are however required to fill delay 15633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * slots in noreorder mode. 16633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 17633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifndef __ASM_ASM_H 18633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define __ASM_ASM_H 19633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 20633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#include <asm/sgidefs.h> 21633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 22633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifndef CAT 23633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifdef __STDC__ 24633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define __CAT(str1, str2) str1##str2 25633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#else 26633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define __CAT(str1, str2) str1/**/str2 27633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 28633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define CAT(str1, str2) __CAT(str1, str2) 29633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 30633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 31633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 32633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * PIC specific declarations 33633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Not used for the kernel but here seems to be the right place. 34633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 35633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifdef __PIC__ 36633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define CPRESTORE(register) \ 37633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .cprestore register 38633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define CPADD(register) \ 39633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .cpadd register 40633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define CPLOAD(register) \ 41633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .cpload register 42633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#else 43633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define CPRESTORE(register) 44633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define CPADD(register) 45633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define CPLOAD(register) 46633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 47633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 48633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 49633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * LEAF - declare leaf routine 50633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 51633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LEAF(symbol) \ 52633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .globl symbol; \ 53633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .align 2; \ 54633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .type symbol, @function; \ 55633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .ent symbol, 0; \ 56633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamsymbol: .frame sp, 0, ra 57633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 58633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 59633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * NESTED - declare nested routine entry point 60633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 61633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define NESTED(symbol, framesize, rpc) \ 62633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .globl symbol; \ 63633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .align 2; \ 64633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .type symbol, @function; \ 65633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .ent symbol, 0; \ 66633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamsymbol: .frame sp, framesize, rpc 67633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 68633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 69633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * END - mark end of function 70633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 71633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define END(function) \ 72633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .end function; \ 73633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .size function, .-function 74633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 75633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 76633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * EXPORT - export definition of symbol 77633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 78633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EXPORT(symbol) \ 79633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .globl symbol; \ 80633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamsymbol: 81633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 82633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 83633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * FEXPORT - export definition of a function symbol 84633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 85633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define FEXPORT(symbol) \ 86633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .globl symbol; \ 87633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .type symbol, @function; \ 88633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamsymbol: 89633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 90633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 91633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * ABS - export absolute symbol 92633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 93633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ABS(symbol,value) \ 94633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .globl symbol; \ 95633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamsymbol = value 96633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 97633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PANIC(msg) \ 98633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .set push; \ 99633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .set reorder; \ 100633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham PTR_LA a0, 8f; \ 101633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham jal panic; \ 102633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham9: b 9b; \ 103633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .set pop; \ 104633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham TEXT(msg) 105633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 106633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 107633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Print formatted string 108633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 109633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifdef CONFIG_PRINTK 110633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRINT(string) \ 111633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .set push; \ 112633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .set reorder; \ 113633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham PTR_LA a0, 8f; \ 114633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham jal printk; \ 115633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .set pop; \ 116633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham TEXT(string) 117633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#else 118633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRINT(string) 119633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 120633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 121633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define TEXT(msg) \ 122633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .pushsection .data; \ 123633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham8: .asciiz msg; \ 124633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .popsection; 125633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 126633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 127633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Build text tables 128633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 129633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define TTABLE(string) \ 130633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .pushsection .text; \ 131633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .word 1f; \ 132633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .popsection \ 133633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .pushsection .data; \ 134633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham1: .asciiz string; \ 135633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .popsection 136633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 137633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 138633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * MIPS IV pref instruction. 139633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Use with .set noreorder only! 140633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * 141633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * MIPS IV implementations are free to treat this as a nop. The R5000 142633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * is one of them. So we should have an option not to use this instruction. 143633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 144633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifdef CONFIG_CPU_HAS_PREFETCH 145633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 146633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PREF(hint,addr) \ 147633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .set push; \ 148633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .set mips4; \ 149633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham pref hint, addr; \ 150633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .set pop 151633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 152633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PREFX(hint,addr) \ 153633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .set push; \ 154633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .set mips4; \ 155633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham prefx hint, addr; \ 156633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .set pop 157633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 158633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#else /* !CONFIG_CPU_HAS_PREFETCH */ 159633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 160633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PREF(hint, addr) 161633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PREFX(hint, addr) 162633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 163633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif /* !CONFIG_CPU_HAS_PREFETCH */ 164633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 165633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 166633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs. 167633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 168633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#if (_MIPS_ISA == _MIPS_ISA_MIPS1) 169633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MOVN(rd, rs, rt) \ 170633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .set push; \ 171633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .set reorder; \ 172633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham beqz rt, 9f; \ 173633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham move rd, rs; \ 174633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .set pop; \ 175633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham9: 176633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MOVZ(rd, rs, rt) \ 177633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .set push; \ 178633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .set reorder; \ 179633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham bnez rt, 9f; \ 180633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham move rd, rs; \ 181633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .set pop; \ 182633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham9: 183633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */ 184633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) 185633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MOVN(rd, rs, rt) \ 186633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .set push; \ 187633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .set noreorder; \ 188633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham bnezl rt, 9f; \ 189633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham move rd, rs; \ 190633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .set pop; \ 191633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham9: 192633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MOVZ(rd, rs, rt) \ 193633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .set push; \ 194633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .set noreorder; \ 195633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham beqzl rt, 9f; \ 196633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham move rd, rs; \ 197633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham .set pop; \ 198633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham9: 199633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */ 200633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \ 201633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64) 202633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MOVN(rd, rs, rt) \ 203633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham movn rd, rs, rt 204633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MOVZ(rd, rs, rt) \ 205633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham movz rd, rs, rt 206633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */ 207633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 208633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 209633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Stack alignment 210633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 211633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#if (_MIPS_SIM == _MIPS_SIM_ABI32) 212633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ALSZ 7 213633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ALMASK ~7 214633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 215633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) 216633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ALSZ 15 217633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ALMASK ~15 218633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 219633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 220633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 221633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Macros to handle different pointer/register sizes for 32/64-bit code 222633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 223633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 224633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 225633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Size of a register 226633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 227633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifdef __mips64 228633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SZREG 8 229633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#else 230633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SZREG 4 231633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 232633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 233633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 234633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Use the following macros in assemblercode to load/store registers, 235633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * pointers etc. 236633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 237633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#if (_MIPS_SIM == _MIPS_SIM_ABI32) 238633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define REG_S sw 239633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define REG_L lw 240633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define REG_SUBU subu 241633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define REG_ADDU addu 242633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 243633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) 244633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define REG_S sd 245633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define REG_L ld 246633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define REG_SUBU dsubu 247633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define REG_ADDU daddu 248633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 249633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 250633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 251633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * How to add/sub/load/store/shift C int variables. 252633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 253633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#if (_MIPS_SZINT == 32) 254633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_ADD add 255633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_ADDU addu 256633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_ADDI addi 257633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_ADDIU addiu 258633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_SUB sub 259633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_SUBU subu 260633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_L lw 261633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_S sw 262633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_SLL sll 263633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_SLLV sllv 264633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_SRL srl 265633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_SRLV srlv 266633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_SRA sra 267633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_SRAV srav 268633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 269633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 270633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#if (_MIPS_SZINT == 64) 271633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_ADD dadd 272633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_ADDU daddu 273633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_ADDI daddi 274633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_ADDIU daddiu 275633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_SUB dsub 276633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_SUBU dsubu 277633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_L ld 278633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_S sd 279633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_SLL dsll 280633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_SLLV dsllv 281633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_SRL dsrl 282633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_SRLV dsrlv 283633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_SRA dsra 284633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_SRAV dsrav 285633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 286633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 287633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 288633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * How to add/sub/load/store/shift C long variables. 289633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 290633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#if (_MIPS_SZLONG == 32) 291633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONG_ADD add 292633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONG_ADDU addu 293633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONG_ADDI addi 294633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONG_ADDIU addiu 295633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONG_SUB sub 296633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONG_SUBU subu 297633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONG_L lw 298633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONG_S sw 299633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONG_SLL sll 300633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONG_SLLV sllv 301633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONG_SRL srl 302633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONG_SRLV srlv 303633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONG_SRA sra 304633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONG_SRAV srav 305633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 306633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONG .word 307633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONGSIZE 4 308633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONGMASK 3 309633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONGLOG 2 310633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 311633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 312633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#if (_MIPS_SZLONG == 64) 313633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONG_ADD dadd 314633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONG_ADDU daddu 315633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONG_ADDI daddi 316633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONG_ADDIU daddiu 317633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONG_SUB dsub 318633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONG_SUBU dsubu 319633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONG_L ld 320633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONG_S sd 321633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONG_SLL dsll 322633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONG_SLLV dsllv 323633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONG_SRL dsrl 324633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONG_SRLV dsrlv 325633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONG_SRA dsra 326633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONG_SRAV dsrav 327633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 328633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONG .dword 329633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONGSIZE 8 330633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONGMASK 7 331633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LONGLOG 3 332633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 333633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 334633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 335633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * How to add/sub/load/store/shift pointers. 336633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 337633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#if (_MIPS_SZPTR == 32) 338633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_ADD add 339633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_ADDU addu 340633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_ADDI addi 341633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_ADDIU addiu 342633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_SUB sub 343633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_SUBU subu 344633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_L lw 345633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_S sw 346633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_LA la 347633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_LI li 348633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_SLL sll 349633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_SLLV sllv 350633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_SRL srl 351633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_SRLV srlv 352633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_SRA sra 353633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_SRAV srav 354633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 355633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_SCALESHIFT 2 356633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 357633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR .word 358633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTRSIZE 4 359633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTRLOG 2 360633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 361633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 362633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#if (_MIPS_SZPTR == 64) 363633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_ADD dadd 364633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_ADDU daddu 365633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_ADDI daddi 366633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_ADDIU daddiu 367633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_SUB dsub 368633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_SUBU dsubu 369633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_L ld 370633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_S sd 371633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_LA dla 372633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_LI dli 373633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_SLL dsll 374633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_SLLV dsllv 375633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_SRL dsrl 376633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_SRLV dsrlv 377633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_SRA dsra 378633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_SRAV dsrav 379633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 380633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR_SCALESHIFT 3 381633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 382633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTR .dword 383633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTRSIZE 8 384633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PTRLOG 3 385633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 386633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 387633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 388633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Some cp0 registers were extended to 64bit for MIPS III. 389633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 390633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#if (_MIPS_SIM == _MIPS_SIM_ABI32) 391633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MFC0 mfc0 392633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MTC0 mtc0 393633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 394633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) 395633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MFC0 dmfc0 396633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MTC0 dmtc0 397633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 398633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 399633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSNOP sll zero, zero, 1 400633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 401633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifdef CONFIG_SGI_IP28 402633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */ 403633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#include <asm/cacheops.h> 404633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define R10KCBARRIER(addr) cache Cache_Barrier, addr; 405633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#else 406633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define R10KCBARRIER(addr) 407633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 408633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 409633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif /* __ASM_ASM_H */ 410