1633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 2633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * 3633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * BRIEF MODULE DESCRIPTION 4633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Include file for Alchemy Semiconductor's Au1k CPU. 5633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * 6633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Copyright 2000-2001, 2006-2008 MontaVista Software Inc. 7633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Author: MontaVista Software, Inc. <source@mvista.com> 8633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * 9633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * This program is free software; you can redistribute it and/or modify it 10633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * under the terms of the GNU General Public License as published by the 11633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Free Software Foundation; either version 2 of the License, or (at your 12633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * option) any later version. 13633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * 14633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 15633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 16633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 17633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 20633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 21633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * 25633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * You should have received a copy of the GNU General Public License along 26633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * with this program; if not, write to the Free Software Foundation, Inc., 27633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * 675 Mass Ave, Cambridge, MA 02139, USA. 28633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 29633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 30633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 31633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp 32633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 33633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 34633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifndef _AU1000_H_ 35633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define _AU1000_H_ 36633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 37633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 38633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifndef _LANGUAGE_ASSEMBLY 39633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 40633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#include <linux/delay.h> 41633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#include <linux/types.h> 42633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 43633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#include <linux/io.h> 44633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#include <linux/irq.h> 45633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 46633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* cpu pipeline flush */ 47633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamvoid static inline au_sync(void) 48633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham{ 49633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham __asm__ volatile ("sync"); 50633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham} 51633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 52633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamvoid static inline au_sync_udelay(int us) 53633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham{ 54633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham __asm__ volatile ("sync"); 55633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham udelay(us); 56633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham} 57633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 58633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamvoid static inline au_sync_delay(int ms) 59633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham{ 60633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham __asm__ volatile ("sync"); 61633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham mdelay(ms); 62633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham} 63633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 64633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamvoid static inline au_writeb(u8 val, unsigned long reg) 65633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham{ 66633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham *(volatile u8 *)reg = val; 67633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham} 68633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 69633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamvoid static inline au_writew(u16 val, unsigned long reg) 70633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham{ 71633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham *(volatile u16 *)reg = val; 72633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham} 73633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 74633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamvoid static inline au_writel(u32 val, unsigned long reg) 75633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham{ 76633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham *(volatile u32 *)reg = val; 77633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham} 78633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 79633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamstatic inline u8 au_readb(unsigned long reg) 80633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham{ 81633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham return *(volatile u8 *)reg; 82633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham} 83633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 84633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamstatic inline u16 au_readw(unsigned long reg) 85633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham{ 86633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham return *(volatile u16 *)reg; 87633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham} 88633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 89633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamstatic inline u32 au_readl(unsigned long reg) 90633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham{ 91633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham return *(volatile u32 *)reg; 92633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham} 93633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 94633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 95633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* arch/mips/au1000/common/clocks.c */ 96633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern void set_au1x00_speed(unsigned int new_freq); 97633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern unsigned int get_au1x00_speed(void); 98633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern void set_au1x00_uart_baud_base(unsigned long new_baud_base); 99633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern unsigned long get_au1x00_uart_baud_base(void); 100633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern void set_au1x00_lcd_clock(void); 101633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern unsigned int get_au1x00_lcd_clock(void); 102633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 103633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 104633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Every board describes its IRQ mapping with this table. 105633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 106633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamstruct au1xxx_irqmap { 107633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham int im_irq; 108633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham int im_type; 109633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham int im_request; 110633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham}; 111633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 112633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 113633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * init_IRQ looks for a table with this name. 114633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 115633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern struct au1xxx_irqmap au1xxx_irq_map[]; 116633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 117633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif /* !defined (_LANGUAGE_ASSEMBLY) */ 118633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 119633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 120633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * SDRAM register offsets 121633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 122633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \ 123633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham defined(CONFIG_SOC_AU1100) 124633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE0 0x0000 125633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE1 0x0004 126633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE2 0x0008 127633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDADDR0 0x000C 128633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDADDR1 0x0010 129633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDADDR2 0x0014 130633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDREFCFG 0x0018 131633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDPRECMD 0x001C 132633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDAUTOREF 0x0020 133633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDWRMD0 0x0024 134633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDWRMD1 0x0028 135633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDWRMD2 0x002C 136633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDSLEEP 0x0030 137633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDSMCKE 0x0034 138633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 139633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 140633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * MEM_SDMODE register content definitions 141633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 142633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE_F (1 << 22) 143633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE_SR (1 << 21) 144633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE_BS (1 << 20) 145633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE_RS (3 << 18) 146633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE_CS (7 << 15) 147633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE_TRAS (15 << 11) 148633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE_TMRD (3 << 9) 149633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE_TWR (3 << 7) 150633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE_TRP (3 << 5) 151633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE_TRCD (3 << 3) 152633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE_TCL (7 << 0) 153633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 154633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE_BS_2Bank (0 << 20) 155633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE_BS_4Bank (1 << 20) 156633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE_RS_11Row (0 << 18) 157633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE_RS_12Row (1 << 18) 158633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE_RS_13Row (2 << 18) 159633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE_RS_N(N) ((N) << 18) 160633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE_CS_7Col (0 << 15) 161633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE_CS_8Col (1 << 15) 162633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE_CS_9Col (2 << 15) 163633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE_CS_10Col (3 << 15) 164633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE_CS_11Col (4 << 15) 165633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE_CS_N(N) ((N) << 15) 166633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE_TRAS_N(N) ((N) << 11) 167633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE_TMRD_N(N) ((N) << 9) 168633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE_TWR_N(N) ((N) << 7) 169633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE_TRP_N(N) ((N) << 5) 170633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE_TRCD_N(N) ((N) << 3) 171633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE_TCL_N(N) ((N) << 0) 172633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 173633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 174633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * MEM_SDADDR register contents definitions 175633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 176633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDADDR_E (1 << 20) 177633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDADDR_CSBA (0x03FF << 10) 178633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDADDR_CSMASK (0x03FF << 0) 179633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12) 180633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22) 181633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 182633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 183633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * MEM_SDREFCFG register content definitions 184633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 185633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDREFCFG_TRC (15 << 28) 186633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDREFCFG_TRPM (3 << 26) 187633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDREFCFG_E (1 << 25) 188633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDREFCFG_RE (0x1ffffff << 0) 189633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC) 190633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM) 191633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDREFCFG_REF_N(N) (N) 192633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 193633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 194633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/***********************************************************************/ 195633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 196633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 197633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Au1550 SDRAM Register Offsets 198633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 199633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 200633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/***********************************************************************/ 201633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 202633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) 203633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE0 0x0800 204633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE1 0x0808 205633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDMODE2 0x0810 206633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDADDR0 0x0820 207633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDADDR1 0x0828 208633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDADDR2 0x0830 209633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDCONFIGA 0x0840 210633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDCONFIGB 0x0848 211633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDSTAT 0x0850 212633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDERRADDR 0x0858 213633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDSTRIDE0 0x0860 214633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDSTRIDE1 0x0868 215633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDSTRIDE2 0x0870 216633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDWRMD0 0x0880 217633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDWRMD1 0x0888 218633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDWRMD2 0x0890 219633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDPRECMD 0x08C0 220633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDAUTOREF 0x08C8 221633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDSREF 0x08D0 222633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_SDSLEEP MEM_SDSREF 223633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 224633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 225633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 226633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 227633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Physical base addresses for integrated peripherals 228633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 229633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 230633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifdef CONFIG_SOC_AU1000 231633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_PHYS_ADDR 0x14000000 232633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define STATIC_MEM_PHYS_ADDR 0x14001000 233633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define DMA0_PHYS_ADDR 0x14002000 234633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define DMA1_PHYS_ADDR 0x14002100 235633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define DMA2_PHYS_ADDR 0x14002200 236633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define DMA3_PHYS_ADDR 0x14002300 237633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define DMA4_PHYS_ADDR 0x14002400 238633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define DMA5_PHYS_ADDR 0x14002500 239633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define DMA6_PHYS_ADDR 0x14002600 240633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define DMA7_PHYS_ADDR 0x14002700 241633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC0_PHYS_ADDR 0x10400000 242633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC1_PHYS_ADDR 0x11800000 243633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define AC97_PHYS_ADDR 0x10000000 244633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBH_PHYS_ADDR 0x10100000 245633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBD_PHYS_ADDR 0x10200000 246633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IRDA_PHYS_ADDR 0x10300000 247633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC0_PHYS_ADDR 0x10500000 248633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC1_PHYS_ADDR 0x10510000 249633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEN_PHYS_ADDR 0x10520000 250633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACDMA0_PHYS_ADDR 0x14004000 251633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACDMA1_PHYS_ADDR 0x14004200 252633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define I2S_PHYS_ADDR 0x11000000 253633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART0_PHYS_ADDR 0x11100000 254633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART1_PHYS_ADDR 0x11200000 255633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART2_PHYS_ADDR 0x11300000 256633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART3_PHYS_ADDR 0x11400000 257633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI0_PHYS_ADDR 0x11600000 258633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI1_PHYS_ADDR 0x11680000 259633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PHYS_ADDR 0x11900000 260633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL 261633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL 262633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL 263633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 264633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 265633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/********************************************************************/ 266633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 267633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifdef CONFIG_SOC_AU1500 268633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_PHYS_ADDR 0x14000000 269633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define STATIC_MEM_PHYS_ADDR 0x14001000 270633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define DMA0_PHYS_ADDR 0x14002000 271633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define DMA1_PHYS_ADDR 0x14002100 272633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define DMA2_PHYS_ADDR 0x14002200 273633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define DMA3_PHYS_ADDR 0x14002300 274633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define DMA4_PHYS_ADDR 0x14002400 275633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define DMA5_PHYS_ADDR 0x14002500 276633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define DMA6_PHYS_ADDR 0x14002600 277633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define DMA7_PHYS_ADDR 0x14002700 278633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC0_PHYS_ADDR 0x10400000 279633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC1_PHYS_ADDR 0x11800000 280633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define AC97_PHYS_ADDR 0x10000000 281633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBH_PHYS_ADDR 0x10100000 282633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBD_PHYS_ADDR 0x10200000 283633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCI_PHYS_ADDR 0x14005000 284633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC0_PHYS_ADDR 0x11500000 285633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC1_PHYS_ADDR 0x11510000 286633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEN_PHYS_ADDR 0x11520000 287633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACDMA0_PHYS_ADDR 0x14004000 288633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACDMA1_PHYS_ADDR 0x14004200 289633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define I2S_PHYS_ADDR 0x11000000 290633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART0_PHYS_ADDR 0x11100000 291633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART3_PHYS_ADDR 0x11400000 292633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define GPIO2_PHYS_ADDR 0x11700000 293633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PHYS_ADDR 0x11900000 294633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCI_MEM_PHYS_ADDR 0x400000000ULL 295633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCI_IO_PHYS_ADDR 0x500000000ULL 296633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL 297633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL 298633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL 299633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL 300633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL 301633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 302633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 303633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/********************************************************************/ 304633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 305633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifdef CONFIG_SOC_AU1100 306633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_PHYS_ADDR 0x14000000 307633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define STATIC_MEM_PHYS_ADDR 0x14001000 308633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define DMA0_PHYS_ADDR 0x14002000 309633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define DMA1_PHYS_ADDR 0x14002100 310633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define DMA2_PHYS_ADDR 0x14002200 311633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define DMA3_PHYS_ADDR 0x14002300 312633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define DMA4_PHYS_ADDR 0x14002400 313633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define DMA5_PHYS_ADDR 0x14002500 314633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define DMA6_PHYS_ADDR 0x14002600 315633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define DMA7_PHYS_ADDR 0x14002700 316633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC0_PHYS_ADDR 0x10400000 317633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SD0_PHYS_ADDR 0x10600000 318633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SD1_PHYS_ADDR 0x10680000 319633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC1_PHYS_ADDR 0x11800000 320633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define AC97_PHYS_ADDR 0x10000000 321633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBH_PHYS_ADDR 0x10100000 322633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBD_PHYS_ADDR 0x10200000 323633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IRDA_PHYS_ADDR 0x10300000 324633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC0_PHYS_ADDR 0x10500000 325633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEN_PHYS_ADDR 0x10520000 326633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACDMA0_PHYS_ADDR 0x14004000 327633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACDMA1_PHYS_ADDR 0x14004200 328633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define I2S_PHYS_ADDR 0x11000000 329633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART0_PHYS_ADDR 0x11100000 330633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART1_PHYS_ADDR 0x11200000 331633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART3_PHYS_ADDR 0x11400000 332633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI0_PHYS_ADDR 0x11600000 333633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI1_PHYS_ADDR 0x11680000 334633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define GPIO2_PHYS_ADDR 0x11700000 335633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PHYS_ADDR 0x11900000 336633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LCD_PHYS_ADDR 0x15000000 337633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL 338633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL 339633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL 340633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 341633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 342633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/***********************************************************************/ 343633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 344633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifdef CONFIG_SOC_AU1550 345633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_PHYS_ADDR 0x14000000 346633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define STATIC_MEM_PHYS_ADDR 0x14001000 347633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC0_PHYS_ADDR 0x10400000 348633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC1_PHYS_ADDR 0x11800000 349633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBH_PHYS_ADDR 0x14020000 350633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBD_PHYS_ADDR 0x10200000 351633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCI_PHYS_ADDR 0x14005000 352633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC0_PHYS_ADDR 0x10500000 353633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC1_PHYS_ADDR 0x10510000 354633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEN_PHYS_ADDR 0x10520000 355633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACDMA0_PHYS_ADDR 0x14004000 356633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACDMA1_PHYS_ADDR 0x14004200 357633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART0_PHYS_ADDR 0x11100000 358633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART1_PHYS_ADDR 0x11200000 359633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART3_PHYS_ADDR 0x11400000 360633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define GPIO2_PHYS_ADDR 0x11700000 361633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PHYS_ADDR 0x11900000 362633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define DDMA_PHYS_ADDR 0x14002000 363633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PE_PHYS_ADDR 0x14008000 364633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PSC0_PHYS_ADDR 0x11A00000 365633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PSC1_PHYS_ADDR 0x11B00000 366633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PSC2_PHYS_ADDR 0x10A00000 367633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PSC3_PHYS_ADDR 0x10B00000 368633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCI_MEM_PHYS_ADDR 0x400000000ULL 369633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCI_IO_PHYS_ADDR 0x500000000ULL 370633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL 371633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL 372633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL 373633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL 374633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL 375633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 376633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 377633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/***********************************************************************/ 378633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 379633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifdef CONFIG_SOC_AU1200 380633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_PHYS_ADDR 0x14000000 381633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define STATIC_MEM_PHYS_ADDR 0x14001000 382633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define AES_PHYS_ADDR 0x10300000 383633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define CIM_PHYS_ADDR 0x14004000 384633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC0_PHYS_ADDR 0x10400000 385633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC1_PHYS_ADDR 0x11800000 386633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBM_PHYS_ADDR 0x14020000 387633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBH_PHYS_ADDR 0x14020100 388633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART0_PHYS_ADDR 0x11100000 389633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART1_PHYS_ADDR 0x11200000 390633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define GPIO2_PHYS_ADDR 0x11700000 391633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PHYS_ADDR 0x11900000 392633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define DDMA_PHYS_ADDR 0x14002000 393633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PSC0_PHYS_ADDR 0x11A00000 394633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PSC1_PHYS_ADDR 0x11B00000 395633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SD0_PHYS_ADDR 0x10600000 396633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SD1_PHYS_ADDR 0x10680000 397633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define LCD_PHYS_ADDR 0x15000000 398633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SWCNT_PHYS_ADDR 0x1110010C 399633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAEFE_PHYS_ADDR 0x14012000 400633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAEBE_PHYS_ADDR 0x14010000 401633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL 402633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL 403633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL 404633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 405633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 406633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* Static Bus Controller */ 407633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_STCFG0 0xB4001000 408633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_STTIME0 0xB4001004 409633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_STADDR0 0xB4001008 410633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 411633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_STCFG1 0xB4001010 412633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_STTIME1 0xB4001014 413633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_STADDR1 0xB4001018 414633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 415633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_STCFG2 0xB4001020 416633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_STTIME2 0xB4001024 417633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_STADDR2 0xB4001028 418633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 419633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_STCFG3 0xB4001030 420633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_STTIME3 0xB4001034 421633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_STADDR3 0xB4001038 422633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 423633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) 424633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_STNDCTL 0xB4001100 425633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_STSTAT 0xB4001104 426633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 427633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_STNAND_CMD 0x0 428633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_STNAND_ADDR 0x4 429633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MEM_STNAND_DATA 0x20 430633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 431633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 432633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* Interrupt Controller 0 */ 433633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC0_CFG0RD 0xB0400040 434633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC0_CFG0SET 0xB0400040 435633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC0_CFG0CLR 0xB0400044 436633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 437633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC0_CFG1RD 0xB0400048 438633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC0_CFG1SET 0xB0400048 439633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC0_CFG1CLR 0xB040004C 440633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 441633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC0_CFG2RD 0xB0400050 442633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC0_CFG2SET 0xB0400050 443633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC0_CFG2CLR 0xB0400054 444633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 445633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC0_REQ0INT 0xB0400054 446633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC0_SRCRD 0xB0400058 447633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC0_SRCSET 0xB0400058 448633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC0_SRCCLR 0xB040005C 449633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC0_REQ1INT 0xB040005C 450633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 451633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC0_ASSIGNRD 0xB0400060 452633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC0_ASSIGNSET 0xB0400060 453633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC0_ASSIGNCLR 0xB0400064 454633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 455633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC0_WAKERD 0xB0400068 456633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC0_WAKESET 0xB0400068 457633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC0_WAKECLR 0xB040006C 458633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 459633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC0_MASKRD 0xB0400070 460633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC0_MASKSET 0xB0400070 461633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC0_MASKCLR 0xB0400074 462633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 463633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC0_RISINGRD 0xB0400078 464633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC0_RISINGCLR 0xB0400078 465633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC0_FALLINGRD 0xB040007C 466633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC0_FALLINGCLR 0xB040007C 467633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 468633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC0_TESTBIT 0xB0400080 469633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 470633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* Interrupt Controller 1 */ 471633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC1_CFG0RD 0xB1800040 472633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC1_CFG0SET 0xB1800040 473633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC1_CFG0CLR 0xB1800044 474633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 475633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC1_CFG1RD 0xB1800048 476633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC1_CFG1SET 0xB1800048 477633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC1_CFG1CLR 0xB180004C 478633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 479633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC1_CFG2RD 0xB1800050 480633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC1_CFG2SET 0xB1800050 481633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC1_CFG2CLR 0xB1800054 482633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 483633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC1_REQ0INT 0xB1800054 484633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC1_SRCRD 0xB1800058 485633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC1_SRCSET 0xB1800058 486633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC1_SRCCLR 0xB180005C 487633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC1_REQ1INT 0xB180005C 488633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 489633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC1_ASSIGNRD 0xB1800060 490633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC1_ASSIGNSET 0xB1800060 491633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC1_ASSIGNCLR 0xB1800064 492633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 493633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC1_WAKERD 0xB1800068 494633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC1_WAKESET 0xB1800068 495633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC1_WAKECLR 0xB180006C 496633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 497633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC1_MASKRD 0xB1800070 498633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC1_MASKSET 0xB1800070 499633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC1_MASKCLR 0xB1800074 500633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 501633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC1_RISINGRD 0xB1800078 502633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC1_RISINGCLR 0xB1800078 503633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC1_FALLINGRD 0xB180007C 504633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC1_FALLINGCLR 0xB180007C 505633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 506633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IC1_TESTBIT 0xB1800080 507633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 508633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* Interrupt Configuration Modes */ 509633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INTC_INT_DISABLED 0x0 510633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INTC_INT_RISE_EDGE 0x1 511633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INTC_INT_FALL_EDGE 0x2 512633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INTC_INT_RISE_AND_FALL_EDGE 0x3 513633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INTC_INT_HIGH_LEVEL 0x5 514633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INTC_INT_LOW_LEVEL 0x6 515633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INTC_INT_HIGH_AND_LOW_LEVEL 0x7 516633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 517633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* Interrupt Numbers */ 518633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* Au1000 */ 519633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifdef CONFIG_SOC_AU1000 520633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamenum soc_au1000_ints { 521633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, 522633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_UART0_INT = AU1000_FIRST_INT, 523633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_UART1_INT, /* au1000 */ 524633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_UART2_INT, /* au1000 */ 525633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_UART3_INT, 526633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_SSI0_INT, /* au1000 */ 527633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_SSI1_INT, /* au1000 */ 528633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_DMA_INT_BASE, 529633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 530633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_TOY_INT = AU1000_FIRST_INT + 14, 531633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_TOY_MATCH0_INT, 532633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_TOY_MATCH1_INT, 533633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_TOY_MATCH2_INT, 534633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_RTC_INT, 535633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_RTC_MATCH0_INT, 536633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_RTC_MATCH1_INT, 537633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_RTC_MATCH2_INT, 538633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_IRDA_TX_INT, /* au1000 */ 539633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_IRDA_RX_INT, /* au1000 */ 540633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_USB_DEV_REQ_INT, 541633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_USB_DEV_SUS_INT, 542633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_USB_HOST_INT, 543633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_ACSYNC_INT, 544633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_MAC0_DMA_INT, 545633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_MAC1_DMA_INT, 546633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_I2S_UO_INT, /* au1000 */ 547633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_AC97C_INT, 548633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_0, 549633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_1, 550633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_2, 551633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_3, 552633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_4, 553633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_5, 554633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_6, 555633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_7, 556633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_8, 557633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_9, 558633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_10, 559633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_11, 560633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_12, 561633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_13, 562633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_14, 563633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_15, 564633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_16, 565633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_17, 566633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_18, 567633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_19, 568633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_20, 569633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_21, 570633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_22, 571633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_23, 572633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_24, 573633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_25, 574633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_26, 575633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_27, 576633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_28, 577633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_29, 578633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_30, 579633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_31, 580633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham}; 581633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 582633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART0_ADDR 0xB1100000 583633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART1_ADDR 0xB1200000 584633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART2_ADDR 0xB1300000 585633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART3_ADDR 0xB1400000 586633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 587633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ 588633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USB_HOST_CONFIG 0xB017FFFC 589633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 590633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define AU1000_ETH0_BASE 0xB0500000 591633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define AU1000_ETH1_BASE 0xB0510000 592633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define AU1000_MAC0_ENABLE 0xB0520000 593633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define AU1000_MAC1_ENABLE 0xB0520004 594633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define NUM_ETH_INTERFACES 2 595633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif /* CONFIG_SOC_AU1000 */ 596633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 597633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* Au1500 */ 598633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifdef CONFIG_SOC_AU1500 599633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamenum soc_au1500_ints { 600633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, 601633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_UART0_INT = AU1500_FIRST_INT, 602633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_PCI_INTA, /* au1500 */ 603633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_PCI_INTB, /* au1500 */ 604633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_UART3_INT, 605633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_PCI_INTC, /* au1500 */ 606633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_PCI_INTD, /* au1500 */ 607633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_DMA_INT_BASE, 608633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 609633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_TOY_INT = AU1500_FIRST_INT + 14, 610633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_TOY_MATCH0_INT, 611633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_TOY_MATCH1_INT, 612633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_TOY_MATCH2_INT, 613633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_RTC_INT, 614633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_RTC_MATCH0_INT, 615633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_RTC_MATCH1_INT, 616633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_RTC_MATCH2_INT, 617633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_PCI_ERR_INT, 618633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_RESERVED_INT, 619633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_USB_DEV_REQ_INT, 620633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_USB_DEV_SUS_INT, 621633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_USB_HOST_INT, 622633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_ACSYNC_INT, 623633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_MAC0_DMA_INT, 624633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_MAC1_DMA_INT, 625633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_AC97C_INT = AU1500_FIRST_INT + 31, 626633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_0, 627633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_1, 628633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_2, 629633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_3, 630633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_4, 631633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_5, 632633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_6, 633633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_7, 634633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_8, 635633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_9, 636633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_10, 637633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_11, 638633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_12, 639633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_13, 640633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_14, 641633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_15, 642633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_GPIO_200, 643633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_GPIO_201, 644633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_GPIO_202, 645633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_GPIO_203, 646633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_GPIO_20, 647633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_GPIO_204, 648633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_GPIO_205, 649633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_GPIO_23, 650633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_GPIO_24, 651633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_GPIO_25, 652633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_GPIO_26, 653633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_GPIO_27, 654633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_GPIO_28, 655633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_GPIO_206, 656633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_GPIO_207, 657633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_GPIO_208_215, 658633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham}; 659633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 660633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* shortcuts */ 661633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INTA AU1000_PCI_INTA 662633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INTB AU1000_PCI_INTB 663633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INTC AU1000_PCI_INTC 664633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INTD AU1000_PCI_INTD 665633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 666633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART0_ADDR 0xB1100000 667633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART3_ADDR 0xB1400000 668633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 669633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ 670633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USB_HOST_CONFIG 0xB017fffc 671633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 672633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define AU1500_ETH0_BASE 0xB1500000 673633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define AU1500_ETH1_BASE 0xB1510000 674633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define AU1500_MAC0_ENABLE 0xB1520000 675633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define AU1500_MAC1_ENABLE 0xB1520004 676633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define NUM_ETH_INTERFACES 2 677633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif /* CONFIG_SOC_AU1500 */ 678633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 679633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* Au1100 */ 680633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifdef CONFIG_SOC_AU1100 681633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamenum soc_au1100_ints { 682633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1100_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, 683633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1100_UART0_INT, 684633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1100_UART1_INT, 685633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1100_SD_INT, 686633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1100_UART3_INT, 687633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_SSI0_INT, 688633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_SSI1_INT, 689633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_DMA_INT_BASE, 690633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 691633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_TOY_INT = AU1100_FIRST_INT + 14, 692633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_TOY_MATCH0_INT, 693633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_TOY_MATCH1_INT, 694633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_TOY_MATCH2_INT, 695633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_RTC_INT, 696633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_RTC_MATCH0_INT, 697633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_RTC_MATCH1_INT, 698633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_RTC_MATCH2_INT, 699633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_IRDA_TX_INT, 700633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_IRDA_RX_INT, 701633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_USB_DEV_REQ_INT, 702633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_USB_DEV_SUS_INT, 703633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_USB_HOST_INT, 704633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_ACSYNC_INT, 705633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1100_MAC0_DMA_INT, 706633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1100_GPIO_208_215, 707633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1100_LCD_INT, 708633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_AC97C_INT, 709633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_0, 710633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_1, 711633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_2, 712633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_3, 713633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_4, 714633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_5, 715633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_6, 716633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_7, 717633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_8, 718633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_9, 719633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_10, 720633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_11, 721633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_12, 722633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_13, 723633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_14, 724633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_15, 725633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_16, 726633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_17, 727633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_18, 728633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_19, 729633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_20, 730633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_21, 731633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_22, 732633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_23, 733633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_24, 734633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_25, 735633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_26, 736633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_27, 737633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_28, 738633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_29, 739633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_30, 740633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_31, 741633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham}; 742633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 743633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART0_ADDR 0xB1100000 744633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART1_ADDR 0xB1200000 745633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART3_ADDR 0xB1400000 746633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 747633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ 748633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USB_HOST_CONFIG 0xB017FFFC 749633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 750633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define AU1100_ETH0_BASE 0xB0500000 751633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define AU1100_MAC0_ENABLE 0xB0520000 752633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define NUM_ETH_INTERFACES 1 753633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif /* CONFIG_SOC_AU1100 */ 754633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 755633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifdef CONFIG_SOC_AU1550 756633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamenum soc_au1550_ints { 757633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1550_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, 758633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1550_UART0_INT = AU1550_FIRST_INT, 759633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1550_PCI_INTA, 760633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1550_PCI_INTB, 761633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1550_DDMA_INT, 762633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1550_CRYPTO_INT, 763633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1550_PCI_INTC, 764633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1550_PCI_INTD, 765633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1550_PCI_RST_INT, 766633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1550_UART1_INT, 767633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1550_UART3_INT, 768633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1550_PSC0_INT, 769633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1550_PSC1_INT, 770633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1550_PSC2_INT, 771633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1550_PSC3_INT, 772633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_TOY_INT, 773633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_TOY_MATCH0_INT, 774633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_TOY_MATCH1_INT, 775633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_TOY_MATCH2_INT, 776633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_RTC_INT, 777633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_RTC_MATCH0_INT, 778633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_RTC_MATCH1_INT, 779633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_RTC_MATCH2_INT, 780633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 781633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1550_NAND_INT = AU1550_FIRST_INT + 23, 782633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1550_USB_DEV_REQ_INT, 783633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_USB_DEV_REQ_INT = AU1550_USB_DEV_REQ_INT, 784633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1550_USB_DEV_SUS_INT, 785633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_USB_DEV_SUS_INT = AU1550_USB_DEV_SUS_INT, 786633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1550_USB_HOST_INT, 787633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_USB_HOST_INT = AU1550_USB_HOST_INT, 788633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1550_MAC0_DMA_INT, 789633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1550_MAC1_DMA_INT, 790633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_0 = AU1550_FIRST_INT + 32, 791633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_1, 792633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_2, 793633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_3, 794633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_4, 795633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_5, 796633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_6, 797633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_7, 798633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_8, 799633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_9, 800633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_10, 801633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_11, 802633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_12, 803633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_13, 804633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_14, 805633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_15, 806633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1550_GPIO_200, 807633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_GPIO_201_205, /* Logical or of GPIO201:205 */ 808633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_GPIO_16, 809633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_GPIO_17, 810633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_GPIO_20, 811633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_GPIO_21, 812633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_GPIO_22, 813633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_GPIO_23, 814633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_GPIO_24, 815633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_GPIO_25, 816633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_GPIO_26, 817633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_GPIO_27, 818633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_GPIO_28, 819633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_GPIO_206, 820633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_GPIO_207, 821633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1500_GPIO_208_218, /* Logical or of GPIO208:218 */ 822633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham}; 823633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 824633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* shortcuts */ 825633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INTA AU1550_PCI_INTA 826633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INTB AU1550_PCI_INTB 827633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INTC AU1550_PCI_INTC 828633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INTD AU1550_PCI_INTD 829633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 830633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART0_ADDR 0xB1100000 831633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART1_ADDR 0xB1200000 832633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART3_ADDR 0xB1400000 833633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 834633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */ 835633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USB_OHCI_LEN 0x00060000 836633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USB_HOST_CONFIG 0xB4027ffc 837633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 838633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define AU1550_ETH0_BASE 0xB0500000 839633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define AU1550_ETH1_BASE 0xB0510000 840633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define AU1550_MAC0_ENABLE 0xB0520000 841633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define AU1550_MAC1_ENABLE 0xB0520004 842633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define NUM_ETH_INTERFACES 2 843633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif /* CONFIG_SOC_AU1550 */ 844633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 845633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifdef CONFIG_SOC_AU1200 846633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamenum soc_au1200_ints { 847633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1200_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, 848633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1200_UART0_INT = AU1200_FIRST_INT, 849633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1200_SWT_INT, 850633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1200_SD_INT, 851633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1200_DDMA_INT, 852633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1200_MAE_BE_INT, 853633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1200_GPIO_200, 854633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1200_GPIO_201, 855633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1200_GPIO_202, 856633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1200_UART1_INT, 857633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1200_MAE_FE_INT, 858633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1200_PSC0_INT, 859633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1200_PSC1_INT, 860633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1200_AES_INT, 861633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1200_CAMERA_INT, 862633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_TOY_INT, 863633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_TOY_MATCH0_INT, 864633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_TOY_MATCH1_INT, 865633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_TOY_MATCH2_INT, 866633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_RTC_INT, 867633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_RTC_MATCH0_INT, 868633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_RTC_MATCH1_INT, 869633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_RTC_MATCH2_INT, 870633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 871633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1200_NAND_INT = AU1200_FIRST_INT + 23, 872633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1200_GPIO_204, 873633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1200_GPIO_205, 874633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1200_GPIO_206, 875633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1200_GPIO_207, 876633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1200_GPIO_208_215, /* Logical OR of 208:215 */ 877633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1200_USB_INT, 878633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_USB_HOST_INT = AU1200_USB_INT, 879633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1200_LCD_INT, 880633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1200_MAE_BOTH_INT, 881633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_0, 882633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_1, 883633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_2, 884633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_3, 885633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_4, 886633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_5, 887633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_6, 888633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_7, 889633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_8, 890633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_9, 891633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_10, 892633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_11, 893633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_12, 894633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_13, 895633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_14, 896633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_15, 897633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_16, 898633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_17, 899633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_18, 900633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_19, 901633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_20, 902633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_21, 903633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_22, 904633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_23, 905633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_24, 906633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_25, 907633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_26, 908633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_27, 909633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_28, 910633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_29, 911633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_30, 912633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham AU1000_GPIO_31, 913633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham}; 914633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 915633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART0_ADDR 0xB1100000 916633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART1_ADDR 0xB1200000 917633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 918633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USB_UOC_BASE 0x14020020 919633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USB_UOC_LEN 0x20 920633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USB_OHCI_BASE 0x14020100 921633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USB_OHCI_LEN 0x100 922633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USB_EHCI_BASE 0x14020200 923633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USB_EHCI_LEN 0x100 924633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USB_UDC_BASE 0x14022000 925633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USB_UDC_LEN 0x2000 926633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USB_MSR_BASE 0xB4020000 927633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USB_MSR_MCFG 4 928633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBMSRMCFG_OMEMEN 0 929633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBMSRMCFG_OBMEN 1 930633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBMSRMCFG_EMEMEN 2 931633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBMSRMCFG_EBMEN 3 932633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBMSRMCFG_DMEMEN 4 933633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBMSRMCFG_DBMEN 5 934633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBMSRMCFG_GMEMEN 6 935633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBMSRMCFG_OHCCLKEN 16 936633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBMSRMCFG_EHCCLKEN 17 937633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBMSRMCFG_UDCCLKEN 18 938633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBMSRMCFG_PHYPLLEN 19 939633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBMSRMCFG_RDCOMB 30 940633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBMSRMCFG_PFEN 31 941633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 942633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif /* CONFIG_SOC_AU1200 */ 943633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 944633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8) 945633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31) 946633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_BASE + 32) 947633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31) 948633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 949633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST 950633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INTX 0xFF /* not valid */ 951633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 952633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* Programmable Counters 0 and 1 */ 953633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_BASE 0xB1900000 954633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) 955633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CNTRL_E1S (1 << 23) 956633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CNTRL_T1S (1 << 20) 957633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CNTRL_M21 (1 << 19) 958633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CNTRL_M11 (1 << 18) 959633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CNTRL_M01 (1 << 17) 960633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CNTRL_C1S (1 << 16) 961633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CNTRL_BP (1 << 14) 962633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CNTRL_EN1 (1 << 13) 963633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CNTRL_BT1 (1 << 12) 964633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CNTRL_EN0 (1 << 11) 965633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CNTRL_BT0 (1 << 10) 966633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CNTRL_E0 (1 << 8) 967633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CNTRL_E0S (1 << 7) 968633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CNTRL_32S (1 << 5) 969633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CNTRL_T0S (1 << 4) 970633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CNTRL_M20 (1 << 3) 971633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CNTRL_M10 (1 << 2) 972633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CNTRL_M00 (1 << 1) 973633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CNTRL_C0S (1 << 0) 974633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 975633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* Programmable Counter 0 Registers */ 976633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_TOYTRIM (SYS_BASE + 0) 977633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_TOYWRITE (SYS_BASE + 4) 978633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_TOYMATCH0 (SYS_BASE + 8) 979633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_TOYMATCH1 (SYS_BASE + 0xC) 980633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_TOYMATCH2 (SYS_BASE + 0x10) 981633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_TOYREAD (SYS_BASE + 0x40) 982633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 983633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* Programmable Counter 1 Registers */ 984633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_RTCTRIM (SYS_BASE + 0x44) 985633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_RTCWRITE (SYS_BASE + 0x48) 986633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_RTCMATCH0 (SYS_BASE + 0x4C) 987633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_RTCMATCH1 (SYS_BASE + 0x50) 988633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_RTCMATCH2 (SYS_BASE + 0x54) 989633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_RTCREAD (SYS_BASE + 0x58) 990633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 991633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* I2S Controller */ 992633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define I2S_DATA 0xB1000000 993633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define I2S_DATA_MASK 0xffffff 994633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define I2S_CONFIG 0xB1000004 995633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define I2S_CONFIG_XU (1 << 25) 996633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define I2S_CONFIG_XO (1 << 24) 997633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define I2S_CONFIG_RU (1 << 23) 998633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define I2S_CONFIG_RO (1 << 22) 999633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define I2S_CONFIG_TR (1 << 21) 1000633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define I2S_CONFIG_TE (1 << 20) 1001633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define I2S_CONFIG_TF (1 << 19) 1002633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define I2S_CONFIG_RR (1 << 18) 1003633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define I2S_CONFIG_RE (1 << 17) 1004633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define I2S_CONFIG_RF (1 << 16) 1005633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define I2S_CONFIG_PD (1 << 11) 1006633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define I2S_CONFIG_LB (1 << 10) 1007633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define I2S_CONFIG_IC (1 << 9) 1008633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define I2S_CONFIG_FM_BIT 7 1009633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT) 1010633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT) 1011633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT) 1012633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT) 1013633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define I2S_CONFIG_TN (1 << 6) 1014633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define I2S_CONFIG_RN (1 << 5) 1015633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define I2S_CONFIG_SZ_BIT 0 1016633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT) 1017633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1018633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define I2S_CONTROL 0xB1000008 1019633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define I2S_CONTROL_D (1 << 1) 1020633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define I2S_CONTROL_CE (1 << 0) 1021633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1022633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* USB Host Controller */ 1023633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifndef USB_OHCI_LEN 1024633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USB_OHCI_LEN 0x00100000 1025633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 1026633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1027633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifndef CONFIG_SOC_AU1200 1028633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1029633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* USB Device Controller */ 1030633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBD_EP0RD 0xB0200000 1031633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBD_EP0WR 0xB0200004 1032633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBD_EP2WR 0xB0200008 1033633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBD_EP3WR 0xB020000C 1034633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBD_EP4RD 0xB0200010 1035633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBD_EP5RD 0xB0200014 1036633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBD_INTEN 0xB0200018 1037633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBD_INTSTAT 0xB020001C 1038633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define USBDEV_INT_SOF (1 << 12) 1039633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define USBDEV_INT_HF_BIT 6 1040633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) 1041633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define USBDEV_INT_CMPLT_BIT 0 1042633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) 1043633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBD_CONFIG 0xB0200020 1044633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBD_EP0CS 0xB0200024 1045633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBD_EP2CS 0xB0200028 1046633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBD_EP3CS 0xB020002C 1047633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBD_EP4CS 0xB0200030 1048633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBD_EP5CS 0xB0200034 1049633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define USBDEV_CS_SU (1 << 14) 1050633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define USBDEV_CS_NAK (1 << 13) 1051633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define USBDEV_CS_ACK (1 << 12) 1052633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define USBDEV_CS_BUSY (1 << 11) 1053633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define USBDEV_CS_TSIZE_BIT 1 1054633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) 1055633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define USBDEV_CS_STALL (1 << 0) 1056633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBD_EP0RDSTAT 0xB0200040 1057633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBD_EP0WRSTAT 0xB0200044 1058633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBD_EP2WRSTAT 0xB0200048 1059633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBD_EP3WRSTAT 0xB020004C 1060633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBD_EP4RDSTAT 0xB0200050 1061633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBD_EP5RDSTAT 0xB0200054 1062633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define USBDEV_FSTAT_FLUSH (1 << 6) 1063633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define USBDEV_FSTAT_UF (1 << 5) 1064633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define USBDEV_FSTAT_OF (1 << 4) 1065633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define USBDEV_FSTAT_FCNT_BIT 0 1066633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) 1067633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define USBD_ENABLE 0xB0200058 1068633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define USBDEV_ENABLE (1 << 1) 1069633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define USBDEV_CE (1 << 0) 1070633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1071633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif /* !CONFIG_SOC_AU1200 */ 1072633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1073633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* Ethernet Controllers */ 1074633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1075633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 4 byte offsets from AU1000_ETH_BASE */ 1076633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC_CONTROL 0x0 1077633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_RX_ENABLE (1 << 2) 1078633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_TX_ENABLE (1 << 3) 1079633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_DEF_CHECK (1 << 5) 1080633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_SET_BL(X) (((X) & 0x3) << 6) 1081633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_AUTO_PAD (1 << 8) 1082633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_DISABLE_RETRY (1 << 10) 1083633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_DISABLE_BCAST (1 << 11) 1084633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_LATE_COL (1 << 12) 1085633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_HASH_MODE (1 << 13) 1086633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_HASH_ONLY (1 << 15) 1087633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_PASS_ALL (1 << 16) 1088633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_INVERSE_FILTER (1 << 17) 1089633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_PROMISCUOUS (1 << 18) 1090633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_PASS_ALL_MULTI (1 << 19) 1091633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_FULL_DUPLEX (1 << 20) 1092633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_NORMAL_MODE 0 1093633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_INT_LOOPBACK (1 << 21) 1094633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_EXT_LOOPBACK (1 << 22) 1095633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_DISABLE_RX_OWN (1 << 23) 1096633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_BIG_ENDIAN (1 << 30) 1097633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_RX_ALL (1 << 31) 1098633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC_ADDRESS_HIGH 0x4 1099633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC_ADDRESS_LOW 0x8 1100633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC_MCAST_HIGH 0xC 1101633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC_MCAST_LOW 0x10 1102633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC_MII_CNTRL 0x14 1103633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_MII_BUSY (1 << 0) 1104633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_MII_READ 0 1105633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_MII_WRITE (1 << 1) 1106633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6) 1107633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11) 1108633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC_MII_DATA 0x18 1109633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC_FLOW_CNTRL 0x1C 1110633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_FLOW_CNTRL_BUSY (1 << 0) 1111633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_FLOW_CNTRL_ENABLE (1 << 1) 1112633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_PASS_CONTROL (1 << 2) 1113633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16) 1114633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC_VLAN1_TAG 0x20 1115633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC_VLAN2_TAG 0x24 1116633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1117633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* Ethernet Controller Enable */ 1118633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1119633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_EN_CLOCK_ENABLE (1 << 0) 1120633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_EN_RESET0 (1 << 1) 1121633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_EN_TOSS (0 << 2) 1122633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_EN_CACHEABLE (1 << 3) 1123633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_EN_RESET1 (1 << 4) 1124633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_EN_RESET2 (1 << 5) 1125633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define MAC_DMA_RESET (1 << 6) 1126633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1127633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* Ethernet Controller DMA Channels */ 1128633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1129633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC0_TX_DMA_ADDR 0xB4004000 1130633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC1_TX_DMA_ADDR 0xB4004200 1131633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* offsets from MAC_TX_RING_ADDR address */ 1132633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC_TX_BUFF0_STATUS 0x0 1133633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define TX_FRAME_ABORTED (1 << 0) 1134633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define TX_JAB_TIMEOUT (1 << 1) 1135633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define TX_NO_CARRIER (1 << 2) 1136633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define TX_LOSS_CARRIER (1 << 3) 1137633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define TX_EXC_DEF (1 << 4) 1138633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define TX_LATE_COLL_ABORT (1 << 5) 1139633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define TX_EXC_COLL (1 << 6) 1140633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define TX_UNDERRUN (1 << 7) 1141633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define TX_DEFERRED (1 << 8) 1142633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define TX_LATE_COLL (1 << 9) 1143633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define TX_COLL_CNT_MASK (0xF << 10) 1144633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define TX_PKT_RETRY (1 << 31) 1145633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC_TX_BUFF0_ADDR 0x4 1146633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define TX_DMA_ENABLE (1 << 0) 1147633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define TX_T_DONE (1 << 1) 1148633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3) 1149633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC_TX_BUFF0_LEN 0x8 1150633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC_TX_BUFF1_STATUS 0x10 1151633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC_TX_BUFF1_ADDR 0x14 1152633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC_TX_BUFF1_LEN 0x18 1153633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC_TX_BUFF2_STATUS 0x20 1154633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC_TX_BUFF2_ADDR 0x24 1155633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC_TX_BUFF2_LEN 0x28 1156633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC_TX_BUFF3_STATUS 0x30 1157633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC_TX_BUFF3_ADDR 0x34 1158633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC_TX_BUFF3_LEN 0x38 1159633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1160633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC0_RX_DMA_ADDR 0xB4004100 1161633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC1_RX_DMA_ADDR 0xB4004300 1162633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* offsets from MAC_RX_RING_ADDR */ 1163633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC_RX_BUFF0_STATUS 0x0 1164633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define RX_FRAME_LEN_MASK 0x3fff 1165633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define RX_WDOG_TIMER (1 << 14) 1166633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define RX_RUNT (1 << 15) 1167633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define RX_OVERLEN (1 << 16) 1168633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define RX_COLL (1 << 17) 1169633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define RX_ETHER (1 << 18) 1170633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define RX_MII_ERROR (1 << 19) 1171633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define RX_DRIBBLING (1 << 20) 1172633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define RX_CRC_ERROR (1 << 21) 1173633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define RX_VLAN1 (1 << 22) 1174633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define RX_VLAN2 (1 << 23) 1175633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define RX_LEN_ERROR (1 << 24) 1176633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define RX_CNTRL_FRAME (1 << 25) 1177633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define RX_U_CNTRL_FRAME (1 << 26) 1178633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define RX_MCAST_FRAME (1 << 27) 1179633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define RX_BCAST_FRAME (1 << 28) 1180633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define RX_FILTER_FAIL (1 << 29) 1181633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define RX_PACKET_FILTER (1 << 30) 1182633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define RX_MISSED_FRAME (1 << 31) 1183633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1184633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ 1185633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ 1186633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) 1187633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC_RX_BUFF0_ADDR 0x4 1188633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define RX_DMA_ENABLE (1 << 0) 1189633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define RX_T_DONE (1 << 1) 1190633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3) 1191633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0) 1192633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC_RX_BUFF1_STATUS 0x10 1193633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC_RX_BUFF1_ADDR 0x14 1194633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC_RX_BUFF2_STATUS 0x20 1195633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC_RX_BUFF2_ADDR 0x24 1196633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC_RX_BUFF3_STATUS 0x30 1197633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MAC_RX_BUFF3_ADDR 0x34 1198633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1199633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* UARTS 0-3 */ 1200633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_BASE UART0_ADDR 1201633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifdef CONFIG_SOC_AU1200 1202633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_DEBUG_BASE UART1_ADDR 1203633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#else 1204633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_DEBUG_BASE UART3_ADDR 1205633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 1206633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1207633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_RX 0 /* Receive buffer */ 1208633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_TX 4 /* Transmit buffer */ 1209633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_IER 8 /* Interrupt Enable Register */ 1210633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_IIR 0xC /* Interrupt ID Register */ 1211633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_FCR 0x10 /* FIFO Control Register */ 1212633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_LCR 0x14 /* Line Control Register */ 1213633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_MCR 0x18 /* Modem Control Register */ 1214633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_LSR 0x1C /* Line Status Register */ 1215633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_MSR 0x20 /* Modem Status Register */ 1216633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_CLK 0x28 /* Baud Rate Clock Divider */ 1217633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_MOD_CNTRL 0x100 /* Module Control */ 1218633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1219633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ 1220633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ 1221633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ 1222633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ 1223633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */ 1224633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */ 1225633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */ 1226633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */ 1227633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */ 1228633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */ 1229633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */ 1230633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */ 1231633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */ 1232633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1233633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 1234633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * These are the definitions for the Line Control Register 1235633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 1236633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_LCR_SBC 0x40 /* Set break control */ 1237633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_LCR_SPAR 0x20 /* Stick parity (?) */ 1238633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_LCR_EPAR 0x10 /* Even parity select */ 1239633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_LCR_PARITY 0x08 /* Parity Enable */ 1240633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */ 1241633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ 1242633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ 1243633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ 1244633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ 1245633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1246633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 1247633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * These are the definitions for the Line Status Register 1248633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 1249633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_LSR_TEMT 0x40 /* Transmitter empty */ 1250633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ 1251633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_LSR_BI 0x10 /* Break interrupt indicator */ 1252633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_LSR_FE 0x08 /* Frame error indicator */ 1253633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_LSR_PE 0x04 /* Parity error indicator */ 1254633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_LSR_OE 0x02 /* Overrun error indicator */ 1255633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_LSR_DR 0x01 /* Receiver data ready */ 1256633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1257633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 1258633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * These are the definitions for the Interrupt Identification Register 1259633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 1260633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ 1261633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ 1262633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_IIR_MSI 0x00 /* Modem status interrupt */ 1263633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ 1264633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ 1265633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ 1266633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1267633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 1268633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * These are the definitions for the Interrupt Enable Register 1269633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 1270633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ 1271633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ 1272633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ 1273633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ 1274633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1275633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 1276633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * These are the definitions for the Modem Control Register 1277633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 1278633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ 1279633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_MCR_OUT2 0x08 /* Out2 complement */ 1280633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_MCR_OUT1 0x04 /* Out1 complement */ 1281633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_MCR_RTS 0x02 /* RTS complement */ 1282633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_MCR_DTR 0x01 /* DTR complement */ 1283633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1284633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 1285633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * These are the definitions for the Modem Status Register 1286633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 1287633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ 1288633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_MSR_RI 0x40 /* Ring Indicator */ 1289633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_MSR_DSR 0x20 /* Data Set Ready */ 1290633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_MSR_CTS 0x10 /* Clear to Send */ 1291633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_MSR_DDCD 0x08 /* Delta DCD */ 1292633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ 1293633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_MSR_DDSR 0x02 /* Delta DSR */ 1294633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_MSR_DCTS 0x01 /* Delta CTS */ 1295633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ 1296633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1297633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* SSIO */ 1298633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI0_STATUS 0xB1600000 1299633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SSI_STATUS_BF (1 << 4) 1300633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SSI_STATUS_OF (1 << 3) 1301633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SSI_STATUS_UF (1 << 2) 1302633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SSI_STATUS_D (1 << 1) 1303633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SSI_STATUS_B (1 << 0) 1304633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI0_INT 0xB1600004 1305633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SSI_INT_OI (1 << 3) 1306633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SSI_INT_UI (1 << 2) 1307633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SSI_INT_DI (1 << 1) 1308633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI0_INT_ENABLE 0xB1600008 1309633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SSI_INTE_OIE (1 << 3) 1310633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SSI_INTE_UIE (1 << 2) 1311633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SSI_INTE_DIE (1 << 1) 1312633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI0_CONFIG 0xB1600020 1313633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SSI_CONFIG_AO (1 << 24) 1314633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SSI_CONFIG_DO (1 << 23) 1315633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SSI_CONFIG_ALEN_BIT 20 1316633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SSI_CONFIG_ALEN_MASK (0x7 << 20) 1317633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SSI_CONFIG_DLEN_BIT 16 1318633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SSI_CONFIG_DLEN_MASK (0x7 << 16) 1319633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SSI_CONFIG_DD (1 << 11) 1320633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SSI_CONFIG_AD (1 << 10) 1321633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SSI_CONFIG_BM_BIT 8 1322633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SSI_CONFIG_BM_MASK (0x3 << 8) 1323633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SSI_CONFIG_CE (1 << 7) 1324633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SSI_CONFIG_DP (1 << 6) 1325633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SSI_CONFIG_DL (1 << 5) 1326633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SSI_CONFIG_EP (1 << 4) 1327633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI0_ADATA 0xB1600024 1328633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SSI_AD_D (1 << 24) 1329633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SSI_AD_ADDR_BIT 16 1330633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SSI_AD_ADDR_MASK (0xff << 16) 1331633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SSI_AD_DATA_BIT 0 1332633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SSI_AD_DATA_MASK (0xfff << 0) 1333633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI0_CLKDIV 0xB1600028 1334633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI0_CONTROL 0xB1600100 1335633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SSI_CONTROL_CD (1 << 1) 1336633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SSI_CONTROL_E (1 << 0) 1337633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1338633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* SSI1 */ 1339633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI1_STATUS 0xB1680000 1340633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI1_INT 0xB1680004 1341633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI1_INT_ENABLE 0xB1680008 1342633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI1_CONFIG 0xB1680020 1343633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI1_ADATA 0xB1680024 1344633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI1_CLKDIV 0xB1680028 1345633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI1_ENABLE 0xB1680100 1346633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1347633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 1348633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Register content definitions 1349633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 1350633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI_STATUS_BF (1 << 4) 1351633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI_STATUS_OF (1 << 3) 1352633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI_STATUS_UF (1 << 2) 1353633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI_STATUS_D (1 << 1) 1354633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI_STATUS_B (1 << 0) 1355633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1356633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* SSI_INT */ 1357633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI_INT_OI (1 << 3) 1358633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI_INT_UI (1 << 2) 1359633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI_INT_DI (1 << 1) 1360633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1361633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* SSI_INTEN */ 1362633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI_INTEN_OIE (1 << 3) 1363633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI_INTEN_UIE (1 << 2) 1364633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI_INTEN_DIE (1 << 1) 1365633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1366633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI_CONFIG_AO (1 << 24) 1367633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI_CONFIG_DO (1 << 23) 1368633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI_CONFIG_ALEN (7 << 20) 1369633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI_CONFIG_DLEN (15 << 16) 1370633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI_CONFIG_DD (1 << 11) 1371633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI_CONFIG_AD (1 << 10) 1372633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI_CONFIG_BM (3 << 8) 1373633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI_CONFIG_CE (1 << 7) 1374633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI_CONFIG_DP (1 << 6) 1375633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI_CONFIG_DL (1 << 5) 1376633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI_CONFIG_EP (1 << 4) 1377633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI_CONFIG_ALEN_N(N) ((N-1) << 20) 1378633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI_CONFIG_DLEN_N(N) ((N-1) << 16) 1379633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI_CONFIG_BM_HI (0 << 8) 1380633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI_CONFIG_BM_LO (1 << 8) 1381633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI_CONFIG_BM_CY (2 << 8) 1382633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1383633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI_ADATA_D (1 << 24) 1384633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI_ADATA_ADDR (0xFF << 16) 1385633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI_ADATA_DATA 0x0FFF 1386633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI_ADATA_ADDR_N(N) (N << 16) 1387633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1388633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI_ENABLE_CD (1 << 1) 1389633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSI_ENABLE_E (1 << 0) 1390633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1391633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* IrDA Controller */ 1392633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IRDA_BASE 0xB0300000 1393633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IR_RING_PTR_STATUS (IRDA_BASE + 0x00) 1394633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IR_RING_BASE_ADDR_H (IRDA_BASE + 0x04) 1395633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IR_RING_BASE_ADDR_L (IRDA_BASE + 0x08) 1396633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IR_RING_SIZE (IRDA_BASE + 0x0C) 1397633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IR_RING_PROMPT (IRDA_BASE + 0x10) 1398633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IR_RING_ADDR_CMPR (IRDA_BASE + 0x14) 1399633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IR_INT_CLEAR (IRDA_BASE + 0x18) 1400633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IR_CONFIG_1 (IRDA_BASE + 0x20) 1401633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define IR_RX_INVERT_LED (1 << 0) 1402633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define IR_TX_INVERT_LED (1 << 1) 1403633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define IR_ST (1 << 2) 1404633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define IR_SF (1 << 3) 1405633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define IR_SIR (1 << 4) 1406633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define IR_MIR (1 << 5) 1407633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define IR_FIR (1 << 6) 1408633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define IR_16CRC (1 << 7) 1409633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define IR_TD (1 << 8) 1410633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define IR_RX_ALL (1 << 9) 1411633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define IR_DMA_ENABLE (1 << 10) 1412633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define IR_RX_ENABLE (1 << 11) 1413633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define IR_TX_ENABLE (1 << 12) 1414633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define IR_LOOPBACK (1 << 14) 1415633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ 1416633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) 1417633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IR_SIR_FLAGS (IRDA_BASE + 0x24) 1418633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IR_ENABLE (IRDA_BASE + 0x28) 1419633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define IR_RX_STATUS (1 << 9) 1420633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define IR_TX_STATUS (1 << 10) 1421633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IR_READ_PHY_CONFIG (IRDA_BASE + 0x2C) 1422633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IR_WRITE_PHY_CONFIG (IRDA_BASE + 0x30) 1423633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IR_MAX_PKT_LEN (IRDA_BASE + 0x34) 1424633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IR_RX_BYTE_CNT (IRDA_BASE + 0x38) 1425633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IR_CONFIG_2 (IRDA_BASE + 0x3C) 1426633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define IR_MODE_INV (1 << 0) 1427633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define IR_ONE_PIN (1 << 1) 1428633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IR_INTERFACE_CONFIG (IRDA_BASE + 0x40) 1429633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1430633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* GPIO */ 1431633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PINFUNC 0xB190002C 1432633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_USB (1 << 15) /* 2nd USB device/host */ 1433633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_U3 (1 << 14) /* GPIO23/U3TXD */ 1434633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_U2 (1 << 13) /* GPIO22/U2TXD */ 1435633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_U1 (1 << 12) /* GPIO21/U1TXD */ 1436633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_SRC (1 << 11) /* GPIO6/SROMCKE */ 1437633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_CK5 (1 << 10) /* GPIO3/CLK5 */ 1438633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_CK4 (1 << 9) /* GPIO2/CLK4 */ 1439633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_IRF (1 << 8) /* GPIO15/IRFIRSEL */ 1440633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_UR3 (1 << 7) /* GPIO[14:9]/UART3 */ 1441633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_I2D (1 << 6) /* GPIO8/I2SDI */ 1442633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_I2S (1 << 5) /* I2S/GPIO[29:31] */ 1443633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_NI2 (1 << 4) /* NI2/GPIO[24:28] */ 1444633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_U0 (1 << 3) /* U0TXD/GPIO20 */ 1445633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_RD (1 << 2) /* IRTXD/GPIO19 */ 1446633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_A97 (1 << 1) /* AC97/SSL1 */ 1447633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_S0 (1 << 0) /* SSI_0/GPIO[16:18] */ 1448633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1449633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* Au1100 only */ 1450633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_PC (1 << 18) /* PCMCIA/GPIO[207:204] */ 1451633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_LCD (1 << 17) /* extern lcd/GPIO[203:200] */ 1452633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_CS (1 << 16) /* EXTCLK0/32KHz to gpio2 */ 1453633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_EX0 (1 << 9) /* GPIO2/clock */ 1454633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1455633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* Au1550 only. Redefines lots of pins */ 1456633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_PSC2_MASK (7 << 17) 1457633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_PSC2_AC97 0 1458633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_PSC2_SPI 0 1459633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_PSC2_I2S (1 << 17) 1460633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_PSC2_SMBUS (3 << 17) 1461633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_PSC2_GPIO (7 << 17) 1462633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_PSC3_MASK (7 << 20) 1463633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_PSC3_AC97 0 1464633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_PSC3_SPI 0 1465633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_PSC3_I2S (1 << 20) 1466633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_PSC3_SMBUS (3 << 20) 1467633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_PSC3_GPIO (7 << 20) 1468633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_PSC1_S1 (1 << 1) 1469633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) 1470633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1471633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* Au1200 only */ 1472633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifdef CONFIG_SOC_AU1200 1473633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PINFUNC_DMA (1 << 31) 1474633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PINFUNC_S0A (1 << 30) 1475633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PINFUNC_S1A (1 << 29) 1476633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PINFUNC_LP0 (1 << 28) 1477633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PINFUNC_LP1 (1 << 27) 1478633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PINFUNC_LD16 (1 << 26) 1479633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PINFUNC_LD8 (1 << 25) 1480633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PINFUNC_LD1 (1 << 24) 1481633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PINFUNC_LD0 (1 << 23) 1482633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PINFUNC_P1A (3 << 21) 1483633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PINFUNC_P1B (1 << 20) 1484633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PINFUNC_FS3 (1 << 19) 1485633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PINFUNC_P0A (3 << 17) 1486633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PINFUNC_CS (1 << 16) 1487633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PINFUNC_CIM (1 << 15) 1488633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PINFUNC_P1C (1 << 14) 1489633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PINFUNC_U1T (1 << 12) 1490633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PINFUNC_U1R (1 << 11) 1491633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PINFUNC_EX1 (1 << 10) 1492633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PINFUNC_EX0 (1 << 9) 1493633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PINFUNC_U0R (1 << 8) 1494633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PINFUNC_MC (1 << 7) 1495633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PINFUNC_S0B (1 << 6) 1496633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PINFUNC_S0C (1 << 5) 1497633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PINFUNC_P0B (1 << 4) 1498633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PINFUNC_U0T (1 << 3) 1499633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PINFUNC_S1B (1 << 2) 1500633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 1501633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1502633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_TRIOUTRD 0xB1900100 1503633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_TRIOUTCLR 0xB1900100 1504633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_OUTPUTRD 0xB1900108 1505633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_OUTPUTSET 0xB1900108 1506633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_OUTPUTCLR 0xB190010C 1507633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PINSTATERD 0xB1900110 1508633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_PININPUTEN 0xB1900110 1509633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1510633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* GPIO2, Au1500, Au1550 only */ 1511633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define GPIO2_BASE 0xB1700000 1512633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define GPIO2_DIR (GPIO2_BASE + 0) 1513633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define GPIO2_OUTPUT (GPIO2_BASE + 8) 1514633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define GPIO2_PINSTATE (GPIO2_BASE + 0xC) 1515633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define GPIO2_INTENABLE (GPIO2_BASE + 0x10) 1516633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define GPIO2_ENABLE (GPIO2_BASE + 0x14) 1517633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1518633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* Power Management */ 1519633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_SCRATCH0 0xB1900018 1520633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_SCRATCH1 0xB190001C 1521633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_WAKEMSK 0xB1900034 1522633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_ENDIAN 0xB1900038 1523633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_POWERCTRL 0xB190003C 1524633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_WAKESRC 0xB190005C 1525633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_SLPPWR 0xB1900078 1526633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_SLEEP 0xB190007C 1527633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1528633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* Clock Controller */ 1529633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_FREQCTRL0 0xB1900020 1530633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_FC_FRDIV2_BIT 22 1531633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT) 1532633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_FC_FE2 (1 << 21) 1533633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_FC_FS2 (1 << 20) 1534633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_FC_FRDIV1_BIT 12 1535633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT) 1536633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_FC_FE1 (1 << 11) 1537633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_FC_FS1 (1 << 10) 1538633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_FC_FRDIV0_BIT 2 1539633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT) 1540633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_FC_FE0 (1 << 1) 1541633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_FC_FS0 (1 << 0) 1542633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_FREQCTRL1 0xB1900024 1543633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_FC_FRDIV5_BIT 22 1544633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT) 1545633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_FC_FE5 (1 << 21) 1546633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_FC_FS5 (1 << 20) 1547633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_FC_FRDIV4_BIT 12 1548633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT) 1549633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_FC_FE4 (1 << 11) 1550633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_FC_FS4 (1 << 10) 1551633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_FC_FRDIV3_BIT 2 1552633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT) 1553633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_FC_FE3 (1 << 1) 1554633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_FC_FS3 (1 << 0) 1555633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_CLKSRC 0xB1900028 1556633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_ME1_BIT 27 1557633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT) 1558633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_DE1 (1 << 26) 1559633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_CE1 (1 << 25) 1560633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_ME0_BIT 22 1561633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT) 1562633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_DE0 (1 << 21) 1563633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_CE0 (1 << 20) 1564633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_MI2_BIT 17 1565633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT) 1566633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_DI2 (1 << 16) 1567633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_CI2 (1 << 15) 1568633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifdef CONFIG_SOC_AU1100 1569633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_ML_BIT 7 1570633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT) 1571633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_DL (1 << 6) 1572633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_CL (1 << 5) 1573633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#else 1574633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_MUH_BIT 12 1575633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT) 1576633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_DUH (1 << 11) 1577633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_CUH (1 << 10) 1578633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_MUD_BIT 7 1579633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT) 1580633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_DUD (1 << 6) 1581633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_CUD (1 << 5) 1582633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 1583633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_MIR_BIT 2 1584633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT) 1585633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_DIR (1 << 1) 1586633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_CIR (1 << 0) 1587633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1588633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_MUX_AUX 0x1 1589633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_MUX_FQ0 0x2 1590633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_MUX_FQ1 0x3 1591633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_MUX_FQ2 0x4 1592633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_MUX_FQ3 0x5 1593633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_MUX_FQ4 0x6 1594633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define SYS_CS_MUX_FQ5 0x7 1595633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_CPUPLL 0xB1900060 1596633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SYS_AUXPLL 0xB1900064 1597633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1598633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* AC97 Controller */ 1599633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define AC97C_CONFIG 0xB0000000 1600633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define AC97C_RECV_SLOTS_BIT 13 1601633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT) 1602633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define AC97C_XMIT_SLOTS_BIT 3 1603633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT) 1604633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define AC97C_SG (1 << 2) 1605633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define AC97C_SYNC (1 << 1) 1606633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define AC97C_RESET (1 << 0) 1607633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define AC97C_STATUS 0xB0000004 1608633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define AC97C_XU (1 << 11) 1609633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define AC97C_XO (1 << 10) 1610633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define AC97C_RU (1 << 9) 1611633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define AC97C_RO (1 << 8) 1612633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define AC97C_READY (1 << 7) 1613633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define AC97C_CP (1 << 6) 1614633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define AC97C_TR (1 << 5) 1615633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define AC97C_TE (1 << 4) 1616633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define AC97C_TF (1 << 3) 1617633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define AC97C_RR (1 << 2) 1618633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define AC97C_RE (1 << 1) 1619633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define AC97C_RF (1 << 0) 1620633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define AC97C_DATA 0xB0000008 1621633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define AC97C_CMD 0xB000000C 1622633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define AC97C_WD_BIT 16 1623633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define AC97C_READ (1 << 7) 1624633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define AC97C_INDEX_MASK 0x7f 1625633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define AC97C_CNTRL 0xB0000010 1626633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define AC97C_RS (1 << 1) 1627633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define AC97C_CE (1 << 0) 1628633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1629633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* Secure Digital (SD) Controller */ 1630633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SD0_XMIT_FIFO 0xB0600000 1631633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SD0_RECV_FIFO 0xB0600004 1632633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SD1_XMIT_FIFO 0xB0680000 1633633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SD1_RECV_FIFO 0xB0680004 1634633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1635633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) 1636633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* Au1500 PCI Controller */ 1637633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define Au1500_CFG_BASE 0xB4005000 /* virtual, KSEG1 addr */ 1638633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0) 1639633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4) 1640633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham# define PCI_ERROR ((1 << 22) | (1 << 23) | (1 << 24) | \ 1641633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham (1 << 25) | (1 << 26) | (1 << 27)) 1642633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8) 1643633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC) 1644633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10) 1645633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14) 1646633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18) 1647633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C) 1648633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20) 1649633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100) 1650633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104) 1651633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108) 1652633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C) 1653633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110) 1654633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1655633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define Au1500_PCI_HDR 0xB4005100 /* virtual, KSEG1 addr */ 1656633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1657633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 1658633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * All of our structures, like PCI resource, have 32-bit members. 1659633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Drivers are expected to do an ioremap on the PCI MEM resource, but it's 1660633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * hard to store 0x4 0000 0000 in a 32-bit type. We require a small patch 1661633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and 1662633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * (u32)Au1500_PCI_MEM_END and change those to the full 36-bit PCI MEM 1663633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * addresses. For PCI I/O, it's simpler because we get to do the ioremap 1664633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * ourselves and then adjust the device's resources. 1665633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 1666633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define Au1500_EXT_CFG 0x600000000ULL 1667633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define Au1500_EXT_CFG_TYPE1 0x680000000ULL 1668633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define Au1500_PCI_IO_START 0x500000000ULL 1669633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define Au1500_PCI_IO_END 0x5000FFFFFULL 1670633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define Au1500_PCI_MEM_START 0x440000000ULL 1671633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define Au1500_PCI_MEM_END 0x44FFFFFFFULL 1672633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1673633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCI_IO_START 0x00001000 1674633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCI_IO_END 0x000FFFFF 1675633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCI_MEM_START 0x40000000 1676633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCI_MEM_END 0x4FFFFFFF 1677633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1678633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCI_FIRST_DEVFN (0 << 3) 1679633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCI_LAST_DEVFN (19 << 3) 1680633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1681633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */ 1682633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOPORT_RESOURCE_END 0xffffffff 1683633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOMEM_RESOURCE_START 0x10000000 1684633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOMEM_RESOURCE_END 0xffffffff 1685633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1686633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#else /* Au1000 and Au1100 and Au1200 */ 1687633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1688633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* Don't allow any legacy ports probing */ 1689633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOPORT_RESOURCE_START 0x10000000 1690633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOPORT_RESOURCE_END 0xffffffff 1691633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOMEM_RESOURCE_START 0x10000000 1692633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOMEM_RESOURCE_END 0xffffffff 1693633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1694633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCI_IO_START 0 1695633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCI_IO_END 0 1696633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCI_MEM_START 0 1697633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCI_MEM_END 0 1698633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCI_FIRST_DEVFN 0 1699633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCI_LAST_DEVFN 0 1700633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1701633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 1702633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1703633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifndef _LANGUAGE_ASSEMBLY 1704633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamtypedef volatile struct { 1705633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x0000 */ u32 toytrim; 1706633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x0004 */ u32 toywrite; 1707633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x0008 */ u32 toymatch0; 1708633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x000C */ u32 toymatch1; 1709633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x0010 */ u32 toymatch2; 1710633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x0014 */ u32 cntrctrl; 1711633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x0018 */ u32 scratch0; 1712633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x001C */ u32 scratch1; 1713633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x0020 */ u32 freqctrl0; 1714633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x0024 */ u32 freqctrl1; 1715633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x0028 */ u32 clksrc; 1716633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x002C */ u32 pinfunc; 1717633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x0030 */ u32 reserved0; 1718633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x0034 */ u32 wakemsk; 1719633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x0038 */ u32 endian; 1720633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x003C */ u32 powerctrl; 1721633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x0040 */ u32 toyread; 1722633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x0044 */ u32 rtctrim; 1723633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x0048 */ u32 rtcwrite; 1724633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x004C */ u32 rtcmatch0; 1725633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x0050 */ u32 rtcmatch1; 1726633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x0054 */ u32 rtcmatch2; 1727633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x0058 */ u32 rtcread; 1728633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x005C */ u32 wakesrc; 1729633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x0060 */ u32 cpupll; 1730633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x0064 */ u32 auxpll; 1731633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x0068 */ u32 reserved1; 1732633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x006C */ u32 reserved2; 1733633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x0070 */ u32 reserved3; 1734633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x0074 */ u32 reserved4; 1735633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x0078 */ u32 slppwr; 1736633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x007C */ u32 sleep; 1737633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x0080 */ u32 reserved5[32]; 1738633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x0100 */ u32 trioutrd; 1739633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define trioutclr trioutrd 1740633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x0104 */ u32 reserved6; 1741633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x0108 */ u32 outputrd; 1742633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define outputset outputrd 1743633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x010C */ u32 outputclr; 1744633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0x0110 */ u32 pinstaterd; 1745633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define pininputen pinstaterd 1746633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham} AU1X00_SYS; 1747633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1748633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamstatic AU1X00_SYS * const sys = (AU1X00_SYS *)SYS_BASE; 1749633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1750633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 1751633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1752633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 1753633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Processor information based on PRID. 1754633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Copied from PowerPC. 1755633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 1756633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifndef _LANGUAGE_ASSEMBLY 1757633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamstruct cpu_spec { 1758633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* CPU is matched via (PRID & prid_mask) == prid_value */ 1759633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham unsigned int prid_mask; 1760633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham unsigned int prid_value; 1761633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1762633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham char *cpu_name; 1763633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham unsigned char cpu_od; /* Set Config[OD] */ 1764633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham unsigned char cpu_bclk; /* Enable BCLK switching */ 1765633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham unsigned char cpu_pll_wo; /* sys_cpupll reg. write-only */ 1766633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham}; 1767633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1768633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern struct cpu_spec cpu_specs[]; 1769633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern struct cpu_spec *cur_cpu_spec[]; 1770633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 1771633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 1772633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif 1773