1c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru/* 2c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru * pci_regs.h 3c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru * 4c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru * PCI standard defines 5c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru * Copyright 1994, Drew Eckhardt 6c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru * Copyright 1997--1999 Martin Mares <mj@ucw.cz> 7c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru * 8c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru * For more information, please consult the following manuals (look at 9c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru * http://www.pcisig.com/ for how to get them): 10c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru * 11c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru * PCI BIOS Specification 12c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru * PCI Local Bus Specification 13c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru * PCI to PCI Bridge Specification 14c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru * PCI System Design Guide 15c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru */ 16c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 17c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#ifndef LINUX_PCI_REGS_H 18c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define LINUX_PCI_REGS_H 19c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 20c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru/* 21c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru * Under PCI, each device has 256 bytes of configuration address space, 22c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru * of which the first 64 bytes are standardized as follows: 23c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru */ 24c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_VENDOR_ID 0x00 /* 16 bits */ 25c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_DEVICE_ID 0x02 /* 16 bits */ 26c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_COMMAND 0x04 /* 16 bits */ 27c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ 28c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ 29c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ 30c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ 31c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ 32c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ 33c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ 34c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ 35c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_COMMAND_SERR 0x100 /* Enable SERR */ 36c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ 37c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ 38c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 39c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_STATUS 0x06 /* 16 bits */ 40c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ 41c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ 42c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ 43c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ 44c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_STATUS_PARITY 0x100 /* Detected parity error */ 45c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ 46c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_STATUS_DEVSEL_FAST 0x000 47c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_STATUS_DEVSEL_MEDIUM 0x200 48c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_STATUS_DEVSEL_SLOW 0x400 49c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ 50c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ 51c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ 52c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ 53c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ 54c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 55c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */ 56c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_REVISION_ID 0x08 /* Revision ID */ 57c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ 58c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CLASS_DEVICE 0x0a /* Device class */ 59c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 60c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ 61c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_LATENCY_TIMER 0x0d /* 8 bits */ 62c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_HEADER_TYPE 0x0e /* 8 bits */ 63c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_HEADER_TYPE_NORMAL 0 64c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_HEADER_TYPE_BRIDGE 1 65c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_HEADER_TYPE_CARDBUS 2 66c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 67c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_BIST 0x0f /* 8 bits */ 68c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_BIST_CODE_MASK 0x0f /* Return result */ 69c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ 70c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ 71c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 72c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru/* 73c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru * Base addresses specify locations in memory or I/O space. 74c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru * Decoded size can be determined by writing a value of 75c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru * 0xffffffff to the register, and reading it back. Only 76c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru * 1 bits are decoded. 77c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru */ 78c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ 79c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ 80c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ 81c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ 82c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ 83c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ 84c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ 85c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_BASE_ADDRESS_SPACE_IO 0x01 86c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 87c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 88c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ 89c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ 90c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ 91c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ 92c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) 93c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) 94c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru/* bit 1 is reserved if address_space = 1 */ 95c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 96c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru/* Header type 0 (normal devices) */ 97c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CARDBUS_CIS 0x28 98c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_SUBSYSTEM_VENDOR_ID 0x2c 99c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_SUBSYSTEM_ID 0x2e 100c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ 101c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ROM_ADDRESS_ENABLE 0x01 102c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ROM_ADDRESS_MASK (~0x7ffUL) 103c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 104c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ 105c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 106c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru/* 0x35-0x3b are reserved */ 107c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ 108c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ 109c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_MIN_GNT 0x3e /* 8 bits */ 110c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_MAX_LAT 0x3f /* 8 bits */ 111c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 112c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru/* Header type 1 (PCI-to-PCI bridges) */ 113c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ 114c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ 115c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ 116c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ 117c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ 118c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_IO_LIMIT 0x1d 119c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O bridging type */ 120c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_IO_RANGE_TYPE_16 0x00 121c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_IO_RANGE_TYPE_32 0x01 122c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_IO_RANGE_MASK (~0x0fUL) 123c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ 124c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_MEMORY_BASE 0x20 /* Memory range behind */ 125c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_MEMORY_LIMIT 0x22 126c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL 127c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_MEMORY_RANGE_MASK (~0x0fUL) 128c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ 129c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PREF_MEMORY_LIMIT 0x26 130c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PREF_RANGE_TYPE_MASK 0x0fUL 131c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PREF_RANGE_TYPE_32 0x00 132c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PREF_RANGE_TYPE_64 0x01 133c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PREF_RANGE_MASK (~0x0fUL) 134c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ 135c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PREF_LIMIT_UPPER32 0x2c 136c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ 137c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_IO_LIMIT_UPPER16 0x32 138c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru/* 0x34 same as for htype 0 */ 139c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru/* 0x35-0x3b is reserved */ 140c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ 141c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru/* 0x3c-0x3d are same as for htype 0 */ 142c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_BRIDGE_CONTROL 0x3e 143c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ 144c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ 145c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ 146c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ 147c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ 148c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ 149c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ 150c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 151c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru/* Header type 2 (CardBus bridges) */ 152c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CB_CAPABILITY_LIST 0x14 153c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru/* 0x15 reserved */ 154c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ 155c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ 156c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ 157c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ 158c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ 159c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CB_MEMORY_BASE_0 0x1c 160c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CB_MEMORY_LIMIT_0 0x20 161c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CB_MEMORY_BASE_1 0x24 162c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CB_MEMORY_LIMIT_1 0x28 163c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CB_IO_BASE_0 0x2c 164c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CB_IO_BASE_0_HI 0x2e 165c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CB_IO_LIMIT_0 0x30 166c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CB_IO_LIMIT_0_HI 0x32 167c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CB_IO_BASE_1 0x34 168c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CB_IO_BASE_1_HI 0x36 169c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CB_IO_LIMIT_1 0x38 170c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CB_IO_LIMIT_1_HI 0x3a 171c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CB_IO_RANGE_MASK (~0x03UL) 172c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru/* 0x3c-0x3d are same as for htype 0 */ 173c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CB_BRIDGE_CONTROL 0x3e 174c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ 175c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CB_BRIDGE_CTL_SERR 0x02 176c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CB_BRIDGE_CTL_ISA 0x04 177c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CB_BRIDGE_CTL_VGA 0x08 178c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 179c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ 180c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ 181c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ 182c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 183c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 184c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 185c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CB_SUBSYSTEM_ID 0x42 186c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ 187c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru/* 0x48-0x7f reserved */ 188c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 189c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru/* Capability lists */ 190c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 191c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CAP_LIST_ID 0 /* Capability ID */ 192c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CAP_ID_PM 0x01 /* Power Management */ 193c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ 194c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ 195c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ 196c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ 197c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ 198c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ 199c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CAP_ID_HT_IRQCONF 0x08 /* HyperTransport IRQ Configuration */ 200c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CAP_ID_VNDR 0x09 /* Vendor specific capability */ 201c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ 202c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CAP_ID_EXP 0x10 /* PCI Express */ 203c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ 204c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ 205c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ 206c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CAP_SIZEOF 4 207c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 208c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru/* Power Management Registers */ 209c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 210c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PM_PMC 2 /* PM Capabilities Register */ 211c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ 212c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ 213c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */ 214c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ 215c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */ 216c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ 217c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ 218c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ 219c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */ 220c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */ 221c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */ 222c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */ 223c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */ 224c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */ 225c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PM_CTRL 4 /* PM control and status register */ 226c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ 227c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PM_CTRL_NO_SOFT_RESET 0x0004 /* No reset for D3hot->D0 */ 228c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ 229c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ 230c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ 231c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ 232c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ 233c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ 234c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ 235c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PM_DATA_REGISTER 7 /* (??) */ 236c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PM_SIZEOF 8 237c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 238c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru/* AGP registers */ 239c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 240c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_AGP_VERSION 2 /* BCD version number */ 241c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_AGP_RFU 3 /* Rest of capability flags */ 242c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_AGP_STATUS 4 /* Status register */ 243c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ 244c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ 245c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ 246c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ 247c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ 248c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ 249c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ 250c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_AGP_COMMAND 8 /* Control register */ 251c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ 252c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ 253c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ 254c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ 255c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ 256c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ 257c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */ 258c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */ 259c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_AGP_SIZEOF 12 260c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 261c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru/* Vital Product Data */ 262c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 263c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */ 264c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */ 265c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */ 266c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_VPD_DATA 4 /* 32-bits of data returned here */ 267c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 268c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru/* Slot Identification */ 269c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 270c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_SID_ESR 2 /* Expansion Slot Register */ 271c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ 272c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ 273c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ 274c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 275c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru/* Message Signalled Interrupts registers */ 276c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 277c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_MSI_FLAGS 2 /* Various flags */ 278c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */ 279c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */ 280c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */ 281c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */ 282c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_MSI_FLAGS_MASKBIT 0x100 /* 64-bit mask bits allowed */ 283c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_MSI_RFU 3 /* Rest of capability flags */ 284c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ 285c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ 286c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ 287c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ 288c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_MSI_MASK_BIT 16 /* Mask bits register */ 289c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 290c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru/* CompactPCI Hotswap Register */ 291c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 292c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CHSWP_CSR 2 /* Control and Status Register */ 293c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */ 294c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */ 295c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */ 296c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CHSWP_LOO 0x08 /* LED On / Off */ 297c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CHSWP_PI 0x30 /* Programming Interface */ 298c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */ 299c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */ 300c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 301c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru/* PCI-X registers */ 302c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 303c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_X_CMD 2 /* Modes & Features */ 304c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ 305c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ 306c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */ 307c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */ 308c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ 309c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_X_STATUS 4 /* PCI-X capabilities */ 310c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */ 311c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */ 312c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */ 313c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */ 314c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */ 315c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */ 316c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity */ 317c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count */ 318c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */ 319c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */ 320c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */ 321c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */ 322c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */ 323c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 324c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru/* PCI Express capability registers */ 325c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 326c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_FLAGS 2 /* Capabilities register */ 327c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */ 328c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ 329c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */ 330c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */ 331c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ 332c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */ 333c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ 334c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */ 335c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */ 336c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */ 337c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_DEVCAP 4 /* Device capabilities */ 338c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */ 339c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */ 340c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */ 341c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */ 342c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */ 343c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */ 344c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */ 345c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */ 346c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */ 347c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */ 348c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_DEVCTL 8 /* Device Control */ 349c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */ 350c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */ 351c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */ 352c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */ 353c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */ 354c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */ 355c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */ 356c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */ 357c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */ 358c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */ 359c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */ 360c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_DEVSTA 10 /* Device Status */ 361c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */ 362c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */ 363c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */ 364c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */ 365c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */ 366c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */ 367c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ 368c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_LNKCTL 16 /* Link Control */ 369c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_LNKSTA 18 /* Link Status */ 370c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ 371c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_SLTCTL 24 /* Slot Control */ 372c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_SLTSTA 26 /* Slot Status */ 373c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_RTCTL 28 /* Root Control */ 374c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_RTCTL_SECEE 0x01 /* System Error on Correctable Error */ 375c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_RTCTL_SENFEE 0x02 /* System Error on Non-Fatal Error */ 376c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_RTCTL_SEFEE 0x04 /* System Error on Fatal Error */ 377c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_RTCTL_PMEIE 0x08 /* PME Interrupt Enable */ 378c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */ 379c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_RTCAP 30 /* Root Capabilities */ 380c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXP_RTSTA 32 /* Root Status */ 381c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 382c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru/* Extended Capabilities (PCI-X 2.0 and Express) */ 383c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) 384c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) 385c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) 386c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 387c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXT_CAP_ID_ERR 1 388c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXT_CAP_ID_VC 2 389c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXT_CAP_ID_DSN 3 390c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_EXT_CAP_ID_PWR 4 391c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 392c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru/* Advanced Error Reporting */ 393c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ 394c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */ 395c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */ 396c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */ 397c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */ 398c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */ 399c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */ 400c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */ 401c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */ 402c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */ 403c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */ 404c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */ 405c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */ 406c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru /* Same bits as above */ 407c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */ 408c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru /* Same bits as above */ 409c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */ 410c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */ 411c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */ 412c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */ 413c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */ 414c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */ 415c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */ 416c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru /* Same bits as above */ 417c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_CAP 24 /* Advanced Error Capabilities */ 418c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */ 419c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */ 420c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */ 421c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */ 422c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */ 423c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */ 424c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */ 425c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru/* Correctable Err Reporting Enable */ 426c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 427c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru/* Non-fatal Err Reporting Enable */ 428c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 429c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru/* Fatal Err Reporting Enable */ 430c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 431c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_ROOT_STATUS 48 432c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */ 433c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru/* Multi ERR_COR Received */ 434c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 435c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru/* ERR_FATAL/NONFATAL Recevied */ 436c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 437c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru/* Multi ERR_FATAL/NONFATAL Recevied */ 438c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 439c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First Fatal */ 440c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */ 441c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */ 442c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_ROOT_COR_SRC 52 443c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_ERR_ROOT_SRC 54 444c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 445c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru/* Virtual Channel */ 446c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_VC_PORT_REG1 4 447c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_VC_PORT_REG2 8 448c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_VC_PORT_CTRL 12 449c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_VC_PORT_STATUS 14 450c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_VC_RES_CAP 16 451c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_VC_RES_CTRL 20 452c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_VC_RES_STATUS 26 453c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 454c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru/* Power Budgeting */ 455c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PWR_DSR 4 /* Data Select Register */ 456c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PWR_DATA 8 /* Data Register */ 457c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */ 458c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */ 459c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */ 460c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */ 461c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */ 462c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */ 463c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PWR_CAP 12 /* Capability */ 464c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ 465c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru 466c559cd81139f97cecad1ad91a0b2e25a5936d53Jean-Baptiste Queru#endif /* LINUX_PCI_REGS_H */ 467