FastISel.h revision 11609451a5e9921d02dea5f1b6c6cd362a3cd676 
1//===-- FastISel.h - Definition of the FastISel class ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the FastISel class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_FASTISEL_H
15#define LLVM_CODEGEN_FASTISEL_H
16
17#include "llvm/ADT/DenseMap.h"
18#ifndef NDEBUG
19#include "llvm/ADT/SmallSet.h"
20#endif
21
22namespace llvm {
23
24class AllocaInst;
25class ConstantFP;
26class Instruction;
27class MachineBasicBlock;
28class MachineConstantPool;
29class MachineFunction;
30class MachineFrameInfo;
31class MachineRegisterInfo;
32class TargetData;
33class TargetInstrInfo;
34class TargetLowering;
35class TargetMachine;
36class TargetRegisterClass;
37
38/// FastISel - This is a fast-path instruction selection class that
39/// generates poor code and doesn't support illegal types or non-trivial
40/// lowering, but runs quickly.
41class FastISel {
42protected:
43  MachineBasicBlock *MBB;
44  DenseMap<const Value *, unsigned> LocalValueMap;
45  DenseMap<const Value *, unsigned> &ValueMap;
46  DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap;
47  DenseMap<const AllocaInst *, int> &StaticAllocaMap;
48#ifndef NDEBUG
49  SmallSet<Instruction*, 8> &CatchInfoLost;
50#endif
51  MachineFunction &MF;
52  MachineRegisterInfo &MRI;
53  MachineFrameInfo &MFI;
54  MachineConstantPool &MCP;
55  DebugLoc DL;
56  const TargetMachine &TM;
57  const TargetData &TD;
58  const TargetInstrInfo &TII;
59  const TargetLowering &TLI;
60
61public:
62  /// startNewBlock - Set the current block to which generated machine
63  /// instructions will be appended, and clear the local CSE map.
64  ///
65  void startNewBlock(MachineBasicBlock *mbb) {
66    setCurrentBlock(mbb);
67    LocalValueMap.clear();
68  }
69
70  /// setCurrentBlock - Set the current block to which generated machine
71  /// instructions will be appended.
72  ///
73  void setCurrentBlock(MachineBasicBlock *mbb) {
74    MBB = mbb;
75  }
76
77  /// setCurDebugLoc - Set the current debug location information, which is used
78  /// when creating a machine instruction.
79  ///
80  void setCurDebugLoc(DebugLoc dl) { DL = dl; }
81
82  /// getCurDebugLoc() - Return current debug location information.
83  DebugLoc getCurDebugLoc() const { return DL; }
84
85  /// SelectInstruction - Do "fast" instruction selection for the given
86  /// LLVM IR instruction, and append generated machine instructions to
87  /// the current block. Return true if selection was successful.
88  ///
89  bool SelectInstruction(Instruction *I);
90
91  /// SelectOperator - Do "fast" instruction selection for the given
92  /// LLVM IR operator (Instruction or ConstantExpr), and append
93  /// generated machine instructions to the current block. Return true
94  /// if selection was successful.
95  ///
96  bool SelectOperator(User *I, unsigned Opcode);
97
98  /// getRegForValue - Create a virtual register and arrange for it to
99  /// be assigned the value for the given LLVM value.
100  unsigned getRegForValue(Value *V);
101
102  /// lookUpRegForValue - Look up the value to see if its value is already
103  /// cached in a register. It may be defined by instructions across blocks or
104  /// defined locally.
105  unsigned lookUpRegForValue(Value *V);
106
107  /// getRegForGEPIndex - This is a wrapper around getRegForValue that also
108  /// takes care of truncating or sign-extending the given getelementptr
109  /// index value.
110  unsigned getRegForGEPIndex(Value *V);
111
112  virtual ~FastISel();
113
114protected:
115  FastISel(MachineFunction &mf,
116           DenseMap<const Value *, unsigned> &vm,
117           DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
118           DenseMap<const AllocaInst *, int> &am
119#ifndef NDEBUG
120           , SmallSet<Instruction*, 8> &cil
121#endif
122           );
123
124  /// TargetSelectInstruction - This method is called by target-independent
125  /// code when the normal FastISel process fails to select an instruction.
126  /// This gives targets a chance to emit code for anything that doesn't
127  /// fit into FastISel's framework. It returns true if it was successful.
128  ///
129  virtual bool
130  TargetSelectInstruction(Instruction *I) = 0;
131
132  /// FastEmit_r - This method is called by target-independent code
133  /// to request that an instruction with the given type and opcode
134  /// be emitted.
135  virtual unsigned FastEmit_(MVT VT,
136                             MVT RetVT,
137                             unsigned Opcode);
138
139  /// FastEmit_r - This method is called by target-independent code
140  /// to request that an instruction with the given type, opcode, and
141  /// register operand be emitted.
142  ///
143  virtual unsigned FastEmit_r(MVT VT,
144                              MVT RetVT,
145                              unsigned Opcode, unsigned Op0);
146
147  /// FastEmit_rr - This method is called by target-independent code
148  /// to request that an instruction with the given type, opcode, and
149  /// register operands be emitted.
150  ///
151  virtual unsigned FastEmit_rr(MVT VT,
152                               MVT RetVT,
153                               unsigned Opcode,
154                               unsigned Op0, unsigned Op1);
155
156  /// FastEmit_ri - This method is called by target-independent code
157  /// to request that an instruction with the given type, opcode, and
158  /// register and immediate operands be emitted.
159  ///
160  virtual unsigned FastEmit_ri(MVT VT,
161                               MVT RetVT,
162                               unsigned Opcode,
163                               unsigned Op0, uint64_t Imm);
164
165  /// FastEmit_rf - This method is called by target-independent code
166  /// to request that an instruction with the given type, opcode, and
167  /// register and floating-point immediate operands be emitted.
168  ///
169  virtual unsigned FastEmit_rf(MVT VT,
170                               MVT RetVT,
171                               unsigned Opcode,
172                               unsigned Op0, ConstantFP *FPImm);
173
174  /// FastEmit_rri - This method is called by target-independent code
175  /// to request that an instruction with the given type, opcode, and
176  /// register and immediate operands be emitted.
177  ///
178  virtual unsigned FastEmit_rri(MVT VT,
179                                MVT RetVT,
180                                unsigned Opcode,
181                                unsigned Op0, unsigned Op1, uint64_t Imm);
182
183  /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
184  /// to emit an instruction with an immediate operand using FastEmit_ri.
185  /// If that fails, it materializes the immediate into a register and try
186  /// FastEmit_rr instead.
187  unsigned FastEmit_ri_(MVT VT,
188                        unsigned Opcode,
189                        unsigned Op0, uint64_t Imm,
190                        MVT ImmType);
191
192  /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
193  /// to emit an instruction with an immediate operand using FastEmit_rf.
194  /// If that fails, it materializes the immediate into a register and try
195  /// FastEmit_rr instead.
196  unsigned FastEmit_rf_(MVT VT,
197                        unsigned Opcode,
198                        unsigned Op0, ConstantFP *FPImm,
199                        MVT ImmType);
200
201  /// FastEmit_i - This method is called by target-independent code
202  /// to request that an instruction with the given type, opcode, and
203  /// immediate operand be emitted.
204  virtual unsigned FastEmit_i(MVT VT,
205                              MVT RetVT,
206                              unsigned Opcode,
207                              uint64_t Imm);
208
209  /// FastEmit_f - This method is called by target-independent code
210  /// to request that an instruction with the given type, opcode, and
211  /// floating-point immediate operand be emitted.
212  virtual unsigned FastEmit_f(MVT VT,
213                              MVT RetVT,
214                              unsigned Opcode,
215                              ConstantFP *FPImm);
216
217  /// FastEmitInst_ - Emit a MachineInstr with no operands and a
218  /// result register in the given register class.
219  ///
220  unsigned FastEmitInst_(unsigned MachineInstOpcode,
221                         const TargetRegisterClass *RC);
222
223  /// FastEmitInst_r - Emit a MachineInstr with one register operand
224  /// and a result register in the given register class.
225  ///
226  unsigned FastEmitInst_r(unsigned MachineInstOpcode,
227                          const TargetRegisterClass *RC,
228                          unsigned Op0);
229
230  /// FastEmitInst_rr - Emit a MachineInstr with two register operands
231  /// and a result register in the given register class.
232  ///
233  unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
234                           const TargetRegisterClass *RC,
235                           unsigned Op0, unsigned Op1);
236
237  /// FastEmitInst_ri - Emit a MachineInstr with two register operands
238  /// and a result register in the given register class.
239  ///
240  unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
241                           const TargetRegisterClass *RC,
242                           unsigned Op0, uint64_t Imm);
243
244  /// FastEmitInst_rf - Emit a MachineInstr with two register operands
245  /// and a result register in the given register class.
246  ///
247  unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
248                           const TargetRegisterClass *RC,
249                           unsigned Op0, ConstantFP *FPImm);
250
251  /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
252  /// an immediate, and a result register in the given register class.
253  ///
254  unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
255                            const TargetRegisterClass *RC,
256                            unsigned Op0, unsigned Op1, uint64_t Imm);
257
258  /// FastEmitInst_i - Emit a MachineInstr with a single immediate
259  /// operand, and a result register in the given register class.
260  unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
261                          const TargetRegisterClass *RC,
262                          uint64_t Imm);
263
264  /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
265  /// from a specified index of a superregister to a specified type.
266  unsigned FastEmitInst_extractsubreg(MVT RetVT,
267                                      unsigned Op0, uint32_t Idx);
268
269  /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
270  /// with all but the least significant bit set to zero.
271  unsigned FastEmitZExtFromI1(MVT VT,
272                              unsigned Op);
273
274  /// FastEmitBranch - Emit an unconditional branch to the given block,
275  /// unless it is the immediate (fall-through) successor, and update
276  /// the CFG.
277  void FastEmitBranch(MachineBasicBlock *MBB);
278
279  unsigned UpdateValueMap(Value* I, unsigned Reg);
280
281  unsigned createResultReg(const TargetRegisterClass *RC);
282
283  /// TargetMaterializeConstant - Emit a constant in a register using
284  /// target-specific logic, such as constant pool loads.
285  virtual unsigned TargetMaterializeConstant(Constant* C) {
286    return 0;
287  }
288
289  /// TargetMaterializeAlloca - Emit an alloca address in a register using
290  /// target-specific logic.
291  virtual unsigned TargetMaterializeAlloca(AllocaInst* C) {
292    return 0;
293  }
294
295private:
296  bool SelectBinaryOp(User *I, unsigned ISDOpcode);
297
298  bool SelectFNeg(User *I);
299
300  bool SelectGetElementPtr(User *I);
301
302  bool SelectCall(User *I);
303
304  bool SelectBitCast(User *I);
305
306  bool SelectCast(User *I, unsigned Opcode);
307};
308
309}
310
311#endif
312