FastISel.h revision 2dd50e656f048d222aaaa57168688326fa52421b 
1//===-- FastISel.h - Definition of the FastISel class ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the FastISel class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_FASTISEL_H
15#define LLVM_CODEGEN_FASTISEL_H
16
17#include "llvm/ADT/DenseMap.h"
18#ifndef NDEBUG
19#include "llvm/ADT/SmallSet.h"
20#endif
21#include "llvm/CodeGen/ValueTypes.h"
22#include "llvm/CodeGen/MachineBasicBlock.h"
23
24namespace llvm {
25
26class AllocaInst;
27class ConstantFP;
28class FunctionLoweringInfo;
29class Instruction;
30class MachineBasicBlock;
31class MachineConstantPool;
32class MachineFunction;
33class MachineInstr;
34class MachineFrameInfo;
35class MachineRegisterInfo;
36class TargetData;
37class TargetInstrInfo;
38class TargetLowering;
39class TargetMachine;
40class TargetRegisterClass;
41class TargetRegisterInfo;
42
43/// FastISel - This is a fast-path instruction selection class that
44/// generates poor code and doesn't support illegal types or non-trivial
45/// lowering, but runs quickly.
46class FastISel {
47protected:
48  DenseMap<const Value *, unsigned> LocalValueMap;
49  FunctionLoweringInfo &FuncInfo;
50  MachineRegisterInfo &MRI;
51  MachineFrameInfo &MFI;
52  MachineConstantPool &MCP;
53  DebugLoc DL;
54  const TargetMachine &TM;
55  const TargetData &TD;
56  const TargetInstrInfo &TII;
57  const TargetLowering &TLI;
58  const TargetRegisterInfo &TRI;
59  MachineInstr *LastLocalValue;
60
61public:
62  /// getLastLocalValue - Return the position of the last instruction
63  /// emitted for materializing constants for use in the current block.
64  MachineInstr *getLastLocalValue() { return LastLocalValue; }
65
66  /// setLastLocalValue - Update the position of the last instruction
67  /// emitted for materializing constants for use in the current block.
68  void setLastLocalValue(MachineInstr *I) { LastLocalValue = I; }
69
70  /// startNewBlock - Set the current block to which generated machine
71  /// instructions will be appended, and clear the local CSE map.
72  ///
73  void startNewBlock();
74
75  /// getCurDebugLoc() - Return current debug location information.
76  DebugLoc getCurDebugLoc() const { return DL; }
77
78  /// SelectInstruction - Do "fast" instruction selection for the given
79  /// LLVM IR instruction, and append generated machine instructions to
80  /// the current block. Return true if selection was successful.
81  ///
82  bool SelectInstruction(const Instruction *I);
83
84  /// SelectOperator - Do "fast" instruction selection for the given
85  /// LLVM IR operator (Instruction or ConstantExpr), and append
86  /// generated machine instructions to the current block. Return true
87  /// if selection was successful.
88  ///
89  bool SelectOperator(const User *I, unsigned Opcode);
90
91  /// getRegForValue - Create a virtual register and arrange for it to
92  /// be assigned the value for the given LLVM value.
93  unsigned getRegForValue(const Value *V);
94
95  /// lookUpRegForValue - Look up the value to see if its value is already
96  /// cached in a register. It may be defined by instructions across blocks or
97  /// defined locally.
98  unsigned lookUpRegForValue(const Value *V);
99
100  /// getRegForGEPIndex - This is a wrapper around getRegForValue that also
101  /// takes care of truncating or sign-extending the given getelementptr
102  /// index value.
103  std::pair<unsigned, bool> getRegForGEPIndex(const Value *V);
104
105  /// recomputeInsertPt - Reset InsertPt to prepare for insterting instructions
106  /// into the current block.
107  void recomputeInsertPt();
108
109  struct SavePoint {
110    MachineBasicBlock::iterator InsertPt;
111    DebugLoc DL;
112  };
113
114  /// enterLocalValueArea - Prepare InsertPt to begin inserting instructions
115  /// into the local value area and return the old insert position.
116  SavePoint enterLocalValueArea();
117
118  /// leaveLocalValueArea - Reset InsertPt to the given old insert position.
119  void leaveLocalValueArea(SavePoint Old);
120
121  virtual ~FastISel();
122
123protected:
124  explicit FastISel(FunctionLoweringInfo &funcInfo);
125
126  /// TargetSelectInstruction - This method is called by target-independent
127  /// code when the normal FastISel process fails to select an instruction.
128  /// This gives targets a chance to emit code for anything that doesn't
129  /// fit into FastISel's framework. It returns true if it was successful.
130  ///
131  virtual bool
132  TargetSelectInstruction(const Instruction *I) = 0;
133
134  /// FastEmit_r - This method is called by target-independent code
135  /// to request that an instruction with the given type and opcode
136  /// be emitted.
137  virtual unsigned FastEmit_(MVT VT,
138                             MVT RetVT,
139                             unsigned Opcode);
140
141  /// FastEmit_r - This method is called by target-independent code
142  /// to request that an instruction with the given type, opcode, and
143  /// register operand be emitted.
144  ///
145  virtual unsigned FastEmit_r(MVT VT,
146                              MVT RetVT,
147                              unsigned Opcode,
148                              unsigned Op0, bool Op0IsKill);
149
150  /// FastEmit_rr - This method is called by target-independent code
151  /// to request that an instruction with the given type, opcode, and
152  /// register operands be emitted.
153  ///
154  virtual unsigned FastEmit_rr(MVT VT,
155                               MVT RetVT,
156                               unsigned Opcode,
157                               unsigned Op0, bool Op0IsKill,
158                               unsigned Op1, bool Op1IsKill);
159
160  /// FastEmit_ri - This method is called by target-independent code
161  /// to request that an instruction with the given type, opcode, and
162  /// register and immediate operands be emitted.
163  ///
164  virtual unsigned FastEmit_ri(MVT VT,
165                               MVT RetVT,
166                               unsigned Opcode,
167                               unsigned Op0, bool Op0IsKill,
168                               uint64_t Imm);
169
170  /// FastEmit_rf - This method is called by target-independent code
171  /// to request that an instruction with the given type, opcode, and
172  /// register and floating-point immediate operands be emitted.
173  ///
174  virtual unsigned FastEmit_rf(MVT VT,
175                               MVT RetVT,
176                               unsigned Opcode,
177                               unsigned Op0, bool Op0IsKill,
178                               const ConstantFP *FPImm);
179
180  /// FastEmit_rri - This method is called by target-independent code
181  /// to request that an instruction with the given type, opcode, and
182  /// register and immediate operands be emitted.
183  ///
184  virtual unsigned FastEmit_rri(MVT VT,
185                                MVT RetVT,
186                                unsigned Opcode,
187                                unsigned Op0, bool Op0IsKill,
188                                unsigned Op1, bool Op1IsKill,
189                                uint64_t Imm);
190
191  /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
192  /// to emit an instruction with an immediate operand using FastEmit_ri.
193  /// If that fails, it materializes the immediate into a register and try
194  /// FastEmit_rr instead.
195  unsigned FastEmit_ri_(MVT VT,
196                        unsigned Opcode,
197                        unsigned Op0, bool Op0IsKill,
198                        uint64_t Imm, MVT ImmType);
199
200  /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
201  /// to emit an instruction with an immediate operand using FastEmit_rf.
202  /// If that fails, it materializes the immediate into a register and try
203  /// FastEmit_rr instead.
204  unsigned FastEmit_rf_(MVT VT,
205                        unsigned Opcode,
206                        unsigned Op0, bool Op0IsKill,
207                        const ConstantFP *FPImm, MVT ImmType);
208
209  /// FastEmit_i - This method is called by target-independent code
210  /// to request that an instruction with the given type, opcode, and
211  /// immediate operand be emitted.
212  virtual unsigned FastEmit_i(MVT VT,
213                              MVT RetVT,
214                              unsigned Opcode,
215                              uint64_t Imm);
216
217  /// FastEmit_f - This method is called by target-independent code
218  /// to request that an instruction with the given type, opcode, and
219  /// floating-point immediate operand be emitted.
220  virtual unsigned FastEmit_f(MVT VT,
221                              MVT RetVT,
222                              unsigned Opcode,
223                              const ConstantFP *FPImm);
224
225  /// FastEmitInst_ - Emit a MachineInstr with no operands and a
226  /// result register in the given register class.
227  ///
228  unsigned FastEmitInst_(unsigned MachineInstOpcode,
229                         const TargetRegisterClass *RC);
230
231  /// FastEmitInst_r - Emit a MachineInstr with one register operand
232  /// and a result register in the given register class.
233  ///
234  unsigned FastEmitInst_r(unsigned MachineInstOpcode,
235                          const TargetRegisterClass *RC,
236                          unsigned Op0, bool Op0IsKill);
237
238  /// FastEmitInst_rr - Emit a MachineInstr with two register operands
239  /// and a result register in the given register class.
240  ///
241  unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
242                           const TargetRegisterClass *RC,
243                           unsigned Op0, bool Op0IsKill,
244                           unsigned Op1, bool Op1IsKill);
245
246  /// FastEmitInst_ri - Emit a MachineInstr with two register operands
247  /// and a result register in the given register class.
248  ///
249  unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
250                           const TargetRegisterClass *RC,
251                           unsigned Op0, bool Op0IsKill,
252                           uint64_t Imm);
253
254  /// FastEmitInst_rf - Emit a MachineInstr with two register operands
255  /// and a result register in the given register class.
256  ///
257  unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
258                           const TargetRegisterClass *RC,
259                           unsigned Op0, bool Op0IsKill,
260                           const ConstantFP *FPImm);
261
262  /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
263  /// an immediate, and a result register in the given register class.
264  ///
265  unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
266                            const TargetRegisterClass *RC,
267                            unsigned Op0, bool Op0IsKill,
268                            unsigned Op1, bool Op1IsKill,
269                            uint64_t Imm);
270
271  /// FastEmitInst_i - Emit a MachineInstr with a single immediate
272  /// operand, and a result register in the given register class.
273  unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
274                          const TargetRegisterClass *RC,
275                          uint64_t Imm);
276
277  /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
278  /// from a specified index of a superregister to a specified type.
279  unsigned FastEmitInst_extractsubreg(MVT RetVT,
280                                      unsigned Op0, bool Op0IsKill,
281                                      uint32_t Idx);
282
283  /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
284  /// with all but the least significant bit set to zero.
285  unsigned FastEmitZExtFromI1(MVT VT,
286                              unsigned Op0, bool Op0IsKill);
287
288  /// FastEmitBranch - Emit an unconditional branch to the given block,
289  /// unless it is the immediate (fall-through) successor, and update
290  /// the CFG.
291  void FastEmitBranch(MachineBasicBlock *MBB, DebugLoc DL);
292
293  unsigned UpdateValueMap(const Value* I, unsigned Reg);
294
295  unsigned createResultReg(const TargetRegisterClass *RC);
296
297  /// TargetMaterializeConstant - Emit a constant in a register using
298  /// target-specific logic, such as constant pool loads.
299  virtual unsigned TargetMaterializeConstant(const Constant* C) {
300    return 0;
301  }
302
303  /// TargetMaterializeAlloca - Emit an alloca address in a register using
304  /// target-specific logic.
305  virtual unsigned TargetMaterializeAlloca(const AllocaInst* C) {
306    return 0;
307  }
308
309private:
310  bool SelectBinaryOp(const User *I, unsigned ISDOpcode);
311
312  bool SelectFNeg(const User *I);
313
314  bool SelectGetElementPtr(const User *I);
315
316  bool SelectCall(const User *I);
317
318  bool SelectBitCast(const User *I);
319
320  bool SelectCast(const User *I, unsigned Opcode);
321
322  /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks.
323  /// Emit code to ensure constants are copied into registers when needed.
324  /// Remember the virtual registers that need to be added to the Machine PHI
325  /// nodes as input.  We cannot just directly add them, because expansion
326  /// might result in multiple MBB's for one BB.  As such, the start of the
327  /// BB might correspond to a different MBB than the end.
328  bool HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
329
330  /// materializeRegForValue - Helper for getRegForVale. This function is
331  /// called when the value isn't already available in a register and must
332  /// be materialized with new instructions.
333  unsigned materializeRegForValue(const Value *V, MVT VT);
334
335  /// hasTrivialKill - Test whether the given value has exactly one use.
336  bool hasTrivialKill(const Value *V) const;
337};
338
339}
340
341#endif
342