FastISel.h revision 6d0c25ec3a7ca822e68f73a4481eee43eb5c9485 
1//===-- FastISel.h - Definition of the FastISel class ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the FastISel class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_FASTISEL_H
15#define LLVM_CODEGEN_FASTISEL_H
16
17#include "llvm/BasicBlock.h"
18#include "llvm/ADT/DenseMap.h"
19#include "llvm/CodeGen/SelectionDAGNodes.h"
20
21namespace llvm {
22
23class MachineBasicBlock;
24class MachineFunction;
25class MachineRegisterInfo;
26class TargetData;
27class TargetInstrInfo;
28class TargetLowering;
29class TargetMachine;
30class TargetRegisterClass;
31
32/// FastISel - This is a fast-path instruction selection class that
33/// generates poor code and doesn't support illegal types or non-trivial
34/// lowering, but runs quickly.
35class FastISel {
36protected:
37  MachineBasicBlock *MBB;
38  MachineFunction &MF;
39  MachineRegisterInfo &MRI;
40  const TargetMachine &TM;
41  const TargetData &TD;
42  const TargetInstrInfo &TII;
43  const TargetLowering &TLI;
44
45public:
46  /// SelectInstructions - Do "fast" instruction selection over the
47  /// LLVM IR instructions in the range [Begin, N) where N is either
48  /// End or the first unsupported instruction. Return N.
49  /// ValueMap is filled in with a mapping of LLVM IR Values to
50  /// virtual register numbers. MBB is a block to which to append
51  /// the generated MachineInstrs.
52  BasicBlock::iterator
53  SelectInstructions(BasicBlock::iterator Begin, BasicBlock::iterator End,
54                     DenseMap<const Value*, unsigned> &ValueMap,
55                     DenseMap<const BasicBlock*, MachineBasicBlock *> &MBBMap,
56                     MachineBasicBlock *MBB);
57
58  virtual ~FastISel();
59
60protected:
61  explicit FastISel(MachineFunction &mf);
62
63  /// FastEmit_r - This method is called by target-independent code
64  /// to request that an instruction with the given type and opcode
65  /// be emitted.
66  virtual unsigned FastEmit_(MVT::SimpleValueType VT,
67                             ISD::NodeType Opcode);
68
69  /// FastEmit_r - This method is called by target-independent code
70  /// to request that an instruction with the given type, opcode, and
71  /// register operand be emitted.
72  ///
73  virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
74                              ISD::NodeType Opcode, unsigned Op0);
75
76  /// FastEmit_rr - This method is called by target-independent code
77  /// to request that an instruction with the given type, opcode, and
78  /// register operands be emitted.
79  ///
80  virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
81                               ISD::NodeType Opcode,
82                               unsigned Op0, unsigned Op1);
83
84  /// FastEmit_ri - This method is called by target-independent code
85  /// to request that an instruction with the given type, opcode, and
86  /// register and immediate operands be emitted.
87  ///
88  virtual unsigned FastEmit_ri(MVT::SimpleValueType VT,
89                               ISD::NodeType Opcode,
90                               unsigned Op0, uint64_t Imm);
91
92  /// FastEmit_rri - This method is called by target-independent code
93  /// to request that an instruction with the given type, opcode, and
94  /// register and immediate operands be emitted.
95  ///
96  virtual unsigned FastEmit_rri(MVT::SimpleValueType VT,
97                                ISD::NodeType Opcode,
98                                unsigned Op0, unsigned Op1, uint64_t Imm);
99
100  /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
101  /// to emit an instruction with an immediate operand using FastEmit_ri.
102  /// If that fails, it materializes the immediate into a register and try
103  /// FastEmit_rr instead.
104  unsigned FastEmit_ri_(MVT::SimpleValueType VT,
105                        ISD::NodeType Opcode,
106                        unsigned Op0, uint64_t Imm,
107                        MVT::SimpleValueType ImmType);
108
109  /// FastEmit_i - This method is called by target-independent code
110  /// to request that an instruction with the given type, opcode, and
111  /// immediate operand be emitted.
112  virtual unsigned FastEmit_i(MVT::SimpleValueType VT,
113                              ISD::NodeType Opcode,
114                              uint64_t Imm);
115
116  /// FastEmitInst_ - Emit a MachineInstr with no operands and a
117  /// result register in the given register class.
118  ///
119  unsigned FastEmitInst_(unsigned MachineInstOpcode,
120                         const TargetRegisterClass *RC);
121
122  /// FastEmitInst_r - Emit a MachineInstr with one register operand
123  /// and a result register in the given register class.
124  ///
125  unsigned FastEmitInst_r(unsigned MachineInstOpcode,
126                          const TargetRegisterClass *RC,
127                          unsigned Op0);
128
129  /// FastEmitInst_rr - Emit a MachineInstr with two register operands
130  /// and a result register in the given register class.
131  ///
132  unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
133                           const TargetRegisterClass *RC,
134                           unsigned Op0, unsigned Op1);
135
136  /// FastEmitInst_ri - Emit a MachineInstr with two register operands
137  /// and a result register in the given register class.
138  ///
139  unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
140                           const TargetRegisterClass *RC,
141                           unsigned Op0, uint64_t Imm);
142
143  /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
144  /// an immediate, and a result register in the given register class.
145  ///
146  unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
147                            const TargetRegisterClass *RC,
148                            unsigned Op0, unsigned Op1, uint64_t Imm);
149
150  /// FastEmitInst_i - Emit a MachineInstr with a single immediate
151  /// operand, and a result register in the given register class.
152  unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
153                          const TargetRegisterClass *RC,
154                          uint64_t Imm);
155
156private:
157  unsigned createResultReg(const TargetRegisterClass *RC);
158
159  bool SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
160                      DenseMap<const Value*, unsigned> &ValueMap);
161
162  bool SelectGetElementPtr(Instruction *I,
163                           DenseMap<const Value*, unsigned> &ValueMap);
164};
165
166}
167
168#endif
169