FastISel.h revision a43abd102f123f6d3bd9ad92045f8119e3fb6153 
1//===-- FastISel.h - Definition of the FastISel class ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the FastISel class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_FASTISEL_H
15#define LLVM_CODEGEN_FASTISEL_H
16
17#include "llvm/BasicBlock.h"
18#include "llvm/ADT/DenseMap.h"
19#include "llvm/CodeGen/SelectionDAGNodes.h"
20
21namespace llvm {
22
23class AllocaInst;
24class ConstantFP;
25class MachineBasicBlock;
26class MachineConstantPool;
27class MachineFunction;
28class MachineFrameInfo;
29class MachineModuleInfo;
30class MachineRegisterInfo;
31class TargetData;
32class TargetInstrInfo;
33class TargetLowering;
34class TargetMachine;
35class TargetRegisterClass;
36
37/// FastISel - This is a fast-path instruction selection class that
38/// generates poor code and doesn't support illegal types or non-trivial
39/// lowering, but runs quickly.
40class FastISel {
41protected:
42  MachineBasicBlock *MBB;
43  DenseMap<const Value *, unsigned> LocalValueMap;
44  DenseMap<const Value *, unsigned> &ValueMap;
45  DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap;
46  DenseMap<const AllocaInst *, int> &StaticAllocaMap;
47  MachineFunction &MF;
48  MachineModuleInfo *MMI;
49  MachineRegisterInfo &MRI;
50  MachineFrameInfo &MFI;
51  MachineConstantPool &MCP;
52  const TargetMachine &TM;
53  const TargetData &TD;
54  const TargetInstrInfo &TII;
55  const TargetLowering &TLI;
56
57public:
58  /// setCurrentBlock - Set the current block, to which generated
59  /// machine instructions will be appended.
60  ///
61  void setCurrentBlock(MachineBasicBlock *mbb) {
62    MBB = mbb;
63    LocalValueMap.clear();
64  }
65
66  /// SelectInstruction - Do "fast" instruction selection for the given
67  /// LLVM IR instruction, and append generated machine instructions to
68  /// the current block. Return true if selection was successful.
69  ///
70  bool SelectInstruction(Instruction *I);
71
72  /// SelectInstruction - Do "fast" instruction selection for the given
73  /// LLVM IR operator (Instruction or ConstantExpr), and append
74  /// generated machine instructions to the current block. Return true
75  /// if selection was successful.
76  ///
77  bool SelectOperator(User *I, unsigned Opcode);
78
79  /// TargetSelectInstruction - This method is called by target-independent
80  /// code when the normal FastISel process fails to select an instruction.
81  /// This gives targets a chance to emit code for anything that doesn't
82  /// fit into FastISel's framework. It returns true if it was successful.
83  ///
84  virtual bool
85  TargetSelectInstruction(Instruction *I) = 0;
86
87  /// getRegForValue - Create a virtual register and arrange for it to
88  /// be assigned the value for the given LLVM value.
89  unsigned getRegForValue(Value *V);
90
91  /// lookUpRegForValue - Look up the value to see if its value is already
92  /// cached in a register. It may be defined by instructions across blocks or
93  /// defined locally.
94  unsigned lookUpRegForValue(Value *V);
95
96  virtual ~FastISel();
97
98protected:
99  FastISel(MachineFunction &mf,
100           MachineModuleInfo *mmi,
101           DenseMap<const Value *, unsigned> &vm,
102           DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
103           DenseMap<const AllocaInst *, int> &am);
104
105  /// FastEmit_r - This method is called by target-independent code
106  /// to request that an instruction with the given type and opcode
107  /// be emitted.
108  virtual unsigned FastEmit_(MVT::SimpleValueType VT,
109                             MVT::SimpleValueType RetVT,
110                             ISD::NodeType Opcode);
111
112  /// FastEmit_r - This method is called by target-independent code
113  /// to request that an instruction with the given type, opcode, and
114  /// register operand be emitted.
115  ///
116  virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
117                              MVT::SimpleValueType RetVT,
118                              ISD::NodeType Opcode, unsigned Op0);
119
120  /// FastEmit_rr - This method is called by target-independent code
121  /// to request that an instruction with the given type, opcode, and
122  /// register operands be emitted.
123  ///
124  virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
125                               MVT::SimpleValueType RetVT,
126                               ISD::NodeType Opcode,
127                               unsigned Op0, unsigned Op1);
128
129  /// FastEmit_ri - This method is called by target-independent code
130  /// to request that an instruction with the given type, opcode, and
131  /// register and immediate operands be emitted.
132  ///
133  virtual unsigned FastEmit_ri(MVT::SimpleValueType VT,
134                               MVT::SimpleValueType RetVT,
135                               ISD::NodeType Opcode,
136                               unsigned Op0, uint64_t Imm);
137
138  /// FastEmit_rf - This method is called by target-independent code
139  /// to request that an instruction with the given type, opcode, and
140  /// register and floating-point immediate operands be emitted.
141  ///
142  virtual unsigned FastEmit_rf(MVT::SimpleValueType VT,
143                               MVT::SimpleValueType RetVT,
144                               ISD::NodeType Opcode,
145                               unsigned Op0, ConstantFP *FPImm);
146
147  /// FastEmit_rri - This method is called by target-independent code
148  /// to request that an instruction with the given type, opcode, and
149  /// register and immediate operands be emitted.
150  ///
151  virtual unsigned FastEmit_rri(MVT::SimpleValueType VT,
152                                MVT::SimpleValueType RetVT,
153                                ISD::NodeType Opcode,
154                                unsigned Op0, unsigned Op1, uint64_t Imm);
155
156  /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
157  /// to emit an instruction with an immediate operand using FastEmit_ri.
158  /// If that fails, it materializes the immediate into a register and try
159  /// FastEmit_rr instead.
160  unsigned FastEmit_ri_(MVT::SimpleValueType VT,
161                        ISD::NodeType Opcode,
162                        unsigned Op0, uint64_t Imm,
163                        MVT::SimpleValueType ImmType);
164
165  /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
166  /// to emit an instruction with an immediate operand using FastEmit_rf.
167  /// If that fails, it materializes the immediate into a register and try
168  /// FastEmit_rr instead.
169  unsigned FastEmit_rf_(MVT::SimpleValueType VT,
170                        ISD::NodeType Opcode,
171                        unsigned Op0, ConstantFP *FPImm,
172                        MVT::SimpleValueType ImmType);
173
174  /// FastEmit_i - This method is called by target-independent code
175  /// to request that an instruction with the given type, opcode, and
176  /// immediate operand be emitted.
177  virtual unsigned FastEmit_i(MVT::SimpleValueType VT,
178                              MVT::SimpleValueType RetVT,
179                              ISD::NodeType Opcode,
180                              uint64_t Imm);
181
182  /// FastEmit_f - This method is called by target-independent code
183  /// to request that an instruction with the given type, opcode, and
184  /// floating-point immediate operand be emitted.
185  virtual unsigned FastEmit_f(MVT::SimpleValueType VT,
186                              MVT::SimpleValueType RetVT,
187                              ISD::NodeType Opcode,
188                              ConstantFP *FPImm);
189
190  /// FastEmitInst_ - Emit a MachineInstr with no operands and a
191  /// result register in the given register class.
192  ///
193  unsigned FastEmitInst_(unsigned MachineInstOpcode,
194                         const TargetRegisterClass *RC);
195
196  /// FastEmitInst_r - Emit a MachineInstr with one register operand
197  /// and a result register in the given register class.
198  ///
199  unsigned FastEmitInst_r(unsigned MachineInstOpcode,
200                          const TargetRegisterClass *RC,
201                          unsigned Op0);
202
203  /// FastEmitInst_rr - Emit a MachineInstr with two register operands
204  /// and a result register in the given register class.
205  ///
206  unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
207                           const TargetRegisterClass *RC,
208                           unsigned Op0, unsigned Op1);
209
210  /// FastEmitInst_ri - Emit a MachineInstr with two register operands
211  /// and a result register in the given register class.
212  ///
213  unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
214                           const TargetRegisterClass *RC,
215                           unsigned Op0, uint64_t Imm);
216
217  /// FastEmitInst_rf - Emit a MachineInstr with two register operands
218  /// and a result register in the given register class.
219  ///
220  unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
221                           const TargetRegisterClass *RC,
222                           unsigned Op0, ConstantFP *FPImm);
223
224  /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
225  /// an immediate, and a result register in the given register class.
226  ///
227  unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
228                            const TargetRegisterClass *RC,
229                            unsigned Op0, unsigned Op1, uint64_t Imm);
230
231  /// FastEmitInst_i - Emit a MachineInstr with a single immediate
232  /// operand, and a result register in the given register class.
233  unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
234                          const TargetRegisterClass *RC,
235                          uint64_t Imm);
236
237  /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
238  /// from a specified index of a superregister.
239  unsigned FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx);
240
241  void UpdateValueMap(Value* I, unsigned Reg);
242
243  unsigned createResultReg(const TargetRegisterClass *RC);
244
245  /// TargetMaterializeConstant - Emit a constant in a register using
246  /// target-specific logic, such as constant pool loads.
247  virtual unsigned TargetMaterializeConstant(Constant* C) {
248    return 0;
249  }
250
251  /// TargetMaterializeAlloca - Emit an alloca address in a register using
252  /// target-specific logic.
253  virtual unsigned TargetMaterializeAlloca(AllocaInst* C) {
254    return 0;
255  }
256
257private:
258  bool SelectBinaryOp(User *I, ISD::NodeType ISDOpcode);
259
260  bool SelectGetElementPtr(User *I);
261
262  bool SelectCall(User *I);
263
264  bool SelectBitCast(User *I);
265
266  bool SelectCast(User *I, ISD::NodeType Opcode);
267};
268
269}
270
271#endif
272