FastISel.h revision a6cb641f48df20f6f79018569b519e5a32e897a2 
1//===-- FastISel.h - Definition of the FastISel class ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the FastISel class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_FASTISEL_H
15#define LLVM_CODEGEN_FASTISEL_H
16
17#include "llvm/ADT/DenseMap.h"
18#ifndef NDEBUG
19#include "llvm/ADT/SmallSet.h"
20#endif
21#include "llvm/CodeGen/ValueTypes.h"
22
23namespace llvm {
24
25class AllocaInst;
26class ConstantFP;
27class Instruction;
28class MachineBasicBlock;
29class MachineConstantPool;
30class MachineFunction;
31class MachineInstr;
32class MachineFrameInfo;
33class MachineRegisterInfo;
34class TargetData;
35class TargetInstrInfo;
36class TargetLowering;
37class TargetMachine;
38class TargetRegisterClass;
39
40/// FastISel - This is a fast-path instruction selection class that
41/// generates poor code and doesn't support illegal types or non-trivial
42/// lowering, but runs quickly.
43class FastISel {
44protected:
45  MachineBasicBlock *MBB;
46  DenseMap<const Value *, unsigned> LocalValueMap;
47  DenseMap<const Value *, unsigned> &ValueMap;
48  DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap;
49  DenseMap<const AllocaInst *, int> &StaticAllocaMap;
50  std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate;
51#ifndef NDEBUG
52  SmallSet<const Instruction *, 8> &CatchInfoLost;
53#endif
54  MachineFunction &MF;
55  MachineRegisterInfo &MRI;
56  MachineFrameInfo &MFI;
57  MachineConstantPool &MCP;
58  DebugLoc DL;
59  const TargetMachine &TM;
60  const TargetData &TD;
61  const TargetInstrInfo &TII;
62  const TargetLowering &TLI;
63  bool IsBottomUp;
64
65public:
66  /// startNewBlock - Set the current block to which generated machine
67  /// instructions will be appended, and clear the local CSE map.
68  ///
69  void startNewBlock(MachineBasicBlock *mbb) {
70    setCurrentBlock(mbb);
71    LocalValueMap.clear();
72  }
73
74  /// setCurrentBlock - Set the current block to which generated machine
75  /// instructions will be appended.
76  ///
77  void setCurrentBlock(MachineBasicBlock *mbb) {
78    MBB = mbb;
79  }
80
81  /// getCurDebugLoc() - Return current debug location information.
82  DebugLoc getCurDebugLoc() const { return DL; }
83
84  /// SelectInstruction - Do "fast" instruction selection for the given
85  /// LLVM IR instruction, and append generated machine instructions to
86  /// the current block. Return true if selection was successful.
87  ///
88  bool SelectInstruction(const Instruction *I);
89
90  /// SelectOperator - Do "fast" instruction selection for the given
91  /// LLVM IR operator (Instruction or ConstantExpr), and append
92  /// generated machine instructions to the current block. Return true
93  /// if selection was successful.
94  ///
95  bool SelectOperator(const User *I, unsigned Opcode);
96
97  /// getRegForValue - Create a virtual register and arrange for it to
98  /// be assigned the value for the given LLVM value.
99  unsigned getRegForValue(const Value *V);
100
101  /// lookUpRegForValue - Look up the value to see if its value is already
102  /// cached in a register. It may be defined by instructions across blocks or
103  /// defined locally.
104  unsigned lookUpRegForValue(const Value *V);
105
106  /// getRegForGEPIndex - This is a wrapper around getRegForValue that also
107  /// takes care of truncating or sign-extending the given getelementptr
108  /// index value.
109  std::pair<unsigned, bool> getRegForGEPIndex(const Value *V);
110
111  virtual ~FastISel();
112
113protected:
114  FastISel(MachineFunction &mf,
115           DenseMap<const Value *, unsigned> &vm,
116           DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
117           DenseMap<const AllocaInst *, int> &am,
118           std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate
119#ifndef NDEBUG
120           , SmallSet<const Instruction *, 8> &cil
121#endif
122           );
123
124  /// TargetSelectInstruction - This method is called by target-independent
125  /// code when the normal FastISel process fails to select an instruction.
126  /// This gives targets a chance to emit code for anything that doesn't
127  /// fit into FastISel's framework. It returns true if it was successful.
128  ///
129  virtual bool
130  TargetSelectInstruction(const Instruction *I) = 0;
131
132  /// FastEmit_r - This method is called by target-independent code
133  /// to request that an instruction with the given type and opcode
134  /// be emitted.
135  virtual unsigned FastEmit_(MVT VT,
136                             MVT RetVT,
137                             unsigned Opcode);
138
139  /// FastEmit_r - This method is called by target-independent code
140  /// to request that an instruction with the given type, opcode, and
141  /// register operand be emitted.
142  ///
143  virtual unsigned FastEmit_r(MVT VT,
144                              MVT RetVT,
145                              unsigned Opcode,
146                              unsigned Op0, bool Op0IsKill);
147
148  /// FastEmit_rr - This method is called by target-independent code
149  /// to request that an instruction with the given type, opcode, and
150  /// register operands be emitted.
151  ///
152  virtual unsigned FastEmit_rr(MVT VT,
153                               MVT RetVT,
154                               unsigned Opcode,
155                               unsigned Op0, bool Op0IsKill,
156                               unsigned Op1, bool Op1IsKill);
157
158  /// FastEmit_ri - This method is called by target-independent code
159  /// to request that an instruction with the given type, opcode, and
160  /// register and immediate operands be emitted.
161  ///
162  virtual unsigned FastEmit_ri(MVT VT,
163                               MVT RetVT,
164                               unsigned Opcode,
165                               unsigned Op0, bool Op0IsKill,
166                               uint64_t Imm);
167
168  /// FastEmit_rf - This method is called by target-independent code
169  /// to request that an instruction with the given type, opcode, and
170  /// register and floating-point immediate operands be emitted.
171  ///
172  virtual unsigned FastEmit_rf(MVT VT,
173                               MVT RetVT,
174                               unsigned Opcode,
175                               unsigned Op0, bool Op0IsKill,
176                               const ConstantFP *FPImm);
177
178  /// FastEmit_rri - This method is called by target-independent code
179  /// to request that an instruction with the given type, opcode, and
180  /// register and immediate operands be emitted.
181  ///
182  virtual unsigned FastEmit_rri(MVT VT,
183                                MVT RetVT,
184                                unsigned Opcode,
185                                unsigned Op0, bool Op0IsKill,
186                                unsigned Op1, bool Op1IsKill,
187                                uint64_t Imm);
188
189  /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
190  /// to emit an instruction with an immediate operand using FastEmit_ri.
191  /// If that fails, it materializes the immediate into a register and try
192  /// FastEmit_rr instead.
193  unsigned FastEmit_ri_(MVT VT,
194                        unsigned Opcode,
195                        unsigned Op0, bool Op0IsKill,
196                        uint64_t Imm, MVT ImmType);
197
198  /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
199  /// to emit an instruction with an immediate operand using FastEmit_rf.
200  /// If that fails, it materializes the immediate into a register and try
201  /// FastEmit_rr instead.
202  unsigned FastEmit_rf_(MVT VT,
203                        unsigned Opcode,
204                        unsigned Op0, bool Op0IsKill,
205                        const ConstantFP *FPImm, MVT ImmType);
206
207  /// FastEmit_i - This method is called by target-independent code
208  /// to request that an instruction with the given type, opcode, and
209  /// immediate operand be emitted.
210  virtual unsigned FastEmit_i(MVT VT,
211                              MVT RetVT,
212                              unsigned Opcode,
213                              uint64_t Imm);
214
215  /// FastEmit_f - This method is called by target-independent code
216  /// to request that an instruction with the given type, opcode, and
217  /// floating-point immediate operand be emitted.
218  virtual unsigned FastEmit_f(MVT VT,
219                              MVT RetVT,
220                              unsigned Opcode,
221                              const ConstantFP *FPImm);
222
223  /// FastEmitInst_ - Emit a MachineInstr with no operands and a
224  /// result register in the given register class.
225  ///
226  unsigned FastEmitInst_(unsigned MachineInstOpcode,
227                         const TargetRegisterClass *RC);
228
229  /// FastEmitInst_r - Emit a MachineInstr with one register operand
230  /// and a result register in the given register class.
231  ///
232  unsigned FastEmitInst_r(unsigned MachineInstOpcode,
233                          const TargetRegisterClass *RC,
234                          unsigned Op0, bool Op0IsKill);
235
236  /// FastEmitInst_rr - Emit a MachineInstr with two register operands
237  /// and a result register in the given register class.
238  ///
239  unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
240                           const TargetRegisterClass *RC,
241                           unsigned Op0, bool Op0IsKill,
242                           unsigned Op1, bool Op1IsKill);
243
244  /// FastEmitInst_ri - Emit a MachineInstr with two register operands
245  /// and a result register in the given register class.
246  ///
247  unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
248                           const TargetRegisterClass *RC,
249                           unsigned Op0, bool Op0IsKill,
250                           uint64_t Imm);
251
252  /// FastEmitInst_rf - Emit a MachineInstr with two register operands
253  /// and a result register in the given register class.
254  ///
255  unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
256                           const TargetRegisterClass *RC,
257                           unsigned Op0, bool Op0IsKill,
258                           const ConstantFP *FPImm);
259
260  /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
261  /// an immediate, and a result register in the given register class.
262  ///
263  unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
264                            const TargetRegisterClass *RC,
265                            unsigned Op0, bool Op0IsKill,
266                            unsigned Op1, bool Op1IsKill,
267                            uint64_t Imm);
268
269  /// FastEmitInst_i - Emit a MachineInstr with a single immediate
270  /// operand, and a result register in the given register class.
271  unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
272                          const TargetRegisterClass *RC,
273                          uint64_t Imm);
274
275  /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
276  /// from a specified index of a superregister to a specified type.
277  unsigned FastEmitInst_extractsubreg(MVT RetVT,
278                                      unsigned Op0, bool Op0IsKill,
279                                      uint32_t Idx);
280
281  /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
282  /// with all but the least significant bit set to zero.
283  unsigned FastEmitZExtFromI1(MVT VT,
284                              unsigned Op0, bool Op0IsKill);
285
286  /// FastEmitBranch - Emit an unconditional branch to the given block,
287  /// unless it is the immediate (fall-through) successor, and update
288  /// the CFG.
289  void FastEmitBranch(MachineBasicBlock *MBB);
290
291  unsigned UpdateValueMap(const Value* I, unsigned Reg);
292
293  unsigned createResultReg(const TargetRegisterClass *RC);
294
295  /// TargetMaterializeConstant - Emit a constant in a register using
296  /// target-specific logic, such as constant pool loads.
297  virtual unsigned TargetMaterializeConstant(const Constant* C) {
298    return 0;
299  }
300
301  /// TargetMaterializeAlloca - Emit an alloca address in a register using
302  /// target-specific logic.
303  virtual unsigned TargetMaterializeAlloca(const AllocaInst* C) {
304    return 0;
305  }
306
307private:
308  bool SelectBinaryOp(const User *I, unsigned ISDOpcode);
309
310  bool SelectFNeg(const User *I);
311
312  bool SelectGetElementPtr(const User *I);
313
314  bool SelectCall(const User *I);
315
316  bool SelectBitCast(const User *I);
317
318  bool SelectCast(const User *I, unsigned Opcode);
319
320  /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks.
321  /// Emit code to ensure constants are copied into registers when needed.
322  /// Remember the virtual registers that need to be added to the Machine PHI
323  /// nodes as input.  We cannot just directly add them, because expansion
324  /// might result in multiple MBB's for one BB.  As such, the start of the
325  /// BB might correspond to a different MBB than the end.
326  bool HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
327
328  /// materializeRegForValue - Helper for getRegForVale. This function is
329  /// called when the value isn't already available in a register and must
330  /// be materialized with new instructions.
331  unsigned materializeRegForValue(const Value *V, MVT VT);
332
333  /// hasTrivialKill - Test whether the given value has exactly one use.
334  bool hasTrivialKill(const Value *V) const;
335};
336
337}
338
339#endif
340