FastISel.h revision df7d5d317096c342ee1c459139914965008fbcd7 
1//===-- FastISel.h - Definition of the FastISel class ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the FastISel class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_FASTISEL_H
15#define LLVM_CODEGEN_FASTISEL_H
16
17#include "llvm/ADT/DenseMap.h"
18#include "llvm/ADT/SmallSet.h"
19#include "llvm/CodeGen/DebugLoc.h"
20#include "llvm/CodeGen/SelectionDAGNodes.h"
21
22namespace llvm {
23
24class AllocaInst;
25class ConstantFP;
26class Instruction;
27class MachineBasicBlock;
28class MachineConstantPool;
29class MachineFunction;
30class MachineFrameInfo;
31class MachineModuleInfo;
32class DwarfWriter;
33class MachineRegisterInfo;
34class TargetData;
35class TargetInstrInfo;
36class TargetLowering;
37class TargetMachine;
38class TargetRegisterClass;
39
40/// FastISel - This is a fast-path instruction selection class that
41/// generates poor code and doesn't support illegal types or non-trivial
42/// lowering, but runs quickly.
43class FastISel {
44protected:
45  MachineBasicBlock *MBB;
46  DenseMap<const Value *, unsigned> LocalValueMap;
47  DenseMap<const Value *, unsigned> &ValueMap;
48  DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap;
49  DenseMap<const AllocaInst *, int> &StaticAllocaMap;
50#ifndef NDEBUG
51  SmallSet<Instruction*, 8> &CatchInfoLost;
52#endif
53  MachineFunction &MF;
54  MachineModuleInfo *MMI;
55  DwarfWriter *DW;
56  MachineRegisterInfo &MRI;
57  MachineFrameInfo &MFI;
58  MachineConstantPool &MCP;
59  DebugLoc DL;
60  const TargetMachine &TM;
61  const TargetData &TD;
62  const TargetInstrInfo &TII;
63  const TargetLowering &TLI;
64
65public:
66  /// startNewBlock - Set the current block to which generated machine
67  /// instructions will be appended, and clear the local CSE map.
68  ///
69  void startNewBlock(MachineBasicBlock *mbb) {
70    setCurrentBlock(mbb);
71    LocalValueMap.clear();
72  }
73
74  /// setCurrentBlock - Set the current block to which generated machine
75  /// instructions will be appended.
76  ///
77  void setCurrentBlock(MachineBasicBlock *mbb) {
78    MBB = mbb;
79  }
80
81  /// setCurDebugLoc - Set the current debug location information, which is used
82  /// when creating a machine instruction.
83  ///
84  void setCurDebugLoc(DebugLoc dl) { DL = dl; }
85
86  /// getCurDebugLoc() - Return current debug location information.
87  DebugLoc getCurDebugLoc() const { return DL; }
88
89  /// SelectInstruction - Do "fast" instruction selection for the given
90  /// LLVM IR instruction, and append generated machine instructions to
91  /// the current block. Return true if selection was successful.
92  ///
93  bool SelectInstruction(Instruction *I);
94
95  /// SelectInstruction - Do "fast" instruction selection for the given
96  /// LLVM IR operator (Instruction or ConstantExpr), and append
97  /// generated machine instructions to the current block. Return true
98  /// if selection was successful.
99  ///
100  bool SelectOperator(User *I, unsigned Opcode);
101
102  /// TargetSelectInstruction - This method is called by target-independent
103  /// code when the normal FastISel process fails to select an instruction.
104  /// This gives targets a chance to emit code for anything that doesn't
105  /// fit into FastISel's framework. It returns true if it was successful.
106  ///
107  virtual bool
108  TargetSelectInstruction(Instruction *I) = 0;
109
110  /// getRegForValue - Create a virtual register and arrange for it to
111  /// be assigned the value for the given LLVM value.
112  unsigned getRegForValue(Value *V);
113
114  /// lookUpRegForValue - Look up the value to see if its value is already
115  /// cached in a register. It may be defined by instructions across blocks or
116  /// defined locally.
117  unsigned lookUpRegForValue(Value *V);
118
119  /// getRegForGEPIndex - This is a wrapper around getRegForValue that also
120  /// takes care of truncating or sign-extending the given getelementptr
121  /// index value.
122  unsigned getRegForGEPIndex(Value *V);
123
124  virtual ~FastISel();
125
126protected:
127  FastISel(MachineFunction &mf,
128           MachineModuleInfo *mmi,
129           DwarfWriter *dw,
130           DenseMap<const Value *, unsigned> &vm,
131           DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
132           DenseMap<const AllocaInst *, int> &am
133#ifndef NDEBUG
134           , SmallSet<Instruction*, 8> &cil
135#endif
136           );
137
138  /// FastEmit_r - This method is called by target-independent code
139  /// to request that an instruction with the given type and opcode
140  /// be emitted.
141  virtual unsigned FastEmit_(MVT::SimpleValueType VT,
142                             MVT::SimpleValueType RetVT,
143                             ISD::NodeType Opcode);
144
145  /// FastEmit_r - This method is called by target-independent code
146  /// to request that an instruction with the given type, opcode, and
147  /// register operand be emitted.
148  ///
149  virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
150                              MVT::SimpleValueType RetVT,
151                              ISD::NodeType Opcode, unsigned Op0);
152
153  /// FastEmit_rr - This method is called by target-independent code
154  /// to request that an instruction with the given type, opcode, and
155  /// register operands be emitted.
156  ///
157  virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
158                               MVT::SimpleValueType RetVT,
159                               ISD::NodeType Opcode,
160                               unsigned Op0, unsigned Op1);
161
162  /// FastEmit_ri - This method is called by target-independent code
163  /// to request that an instruction with the given type, opcode, and
164  /// register and immediate operands be emitted.
165  ///
166  virtual unsigned FastEmit_ri(MVT::SimpleValueType VT,
167                               MVT::SimpleValueType RetVT,
168                               ISD::NodeType Opcode,
169                               unsigned Op0, uint64_t Imm);
170
171  /// FastEmit_rf - This method is called by target-independent code
172  /// to request that an instruction with the given type, opcode, and
173  /// register and floating-point immediate operands be emitted.
174  ///
175  virtual unsigned FastEmit_rf(MVT::SimpleValueType VT,
176                               MVT::SimpleValueType RetVT,
177                               ISD::NodeType Opcode,
178                               unsigned Op0, ConstantFP *FPImm);
179
180  /// FastEmit_rri - This method is called by target-independent code
181  /// to request that an instruction with the given type, opcode, and
182  /// register and immediate operands be emitted.
183  ///
184  virtual unsigned FastEmit_rri(MVT::SimpleValueType VT,
185                                MVT::SimpleValueType RetVT,
186                                ISD::NodeType Opcode,
187                                unsigned Op0, unsigned Op1, uint64_t Imm);
188
189  /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
190  /// to emit an instruction with an immediate operand using FastEmit_ri.
191  /// If that fails, it materializes the immediate into a register and try
192  /// FastEmit_rr instead.
193  unsigned FastEmit_ri_(MVT::SimpleValueType VT,
194                        ISD::NodeType Opcode,
195                        unsigned Op0, uint64_t Imm,
196                        MVT::SimpleValueType ImmType);
197
198  /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
199  /// to emit an instruction with an immediate operand using FastEmit_rf.
200  /// If that fails, it materializes the immediate into a register and try
201  /// FastEmit_rr instead.
202  unsigned FastEmit_rf_(MVT::SimpleValueType VT,
203                        ISD::NodeType Opcode,
204                        unsigned Op0, ConstantFP *FPImm,
205                        MVT::SimpleValueType ImmType);
206
207  /// FastEmit_i - This method is called by target-independent code
208  /// to request that an instruction with the given type, opcode, and
209  /// immediate operand be emitted.
210  virtual unsigned FastEmit_i(MVT::SimpleValueType VT,
211                              MVT::SimpleValueType RetVT,
212                              ISD::NodeType Opcode,
213                              uint64_t Imm);
214
215  /// FastEmit_f - This method is called by target-independent code
216  /// to request that an instruction with the given type, opcode, and
217  /// floating-point immediate operand be emitted.
218  virtual unsigned FastEmit_f(MVT::SimpleValueType VT,
219                              MVT::SimpleValueType RetVT,
220                              ISD::NodeType Opcode,
221                              ConstantFP *FPImm);
222
223  /// FastEmitInst_ - Emit a MachineInstr with no operands and a
224  /// result register in the given register class.
225  ///
226  unsigned FastEmitInst_(unsigned MachineInstOpcode,
227                         const TargetRegisterClass *RC);
228
229  /// FastEmitInst_r - Emit a MachineInstr with one register operand
230  /// and a result register in the given register class.
231  ///
232  unsigned FastEmitInst_r(unsigned MachineInstOpcode,
233                          const TargetRegisterClass *RC,
234                          unsigned Op0);
235
236  /// FastEmitInst_rr - Emit a MachineInstr with two register operands
237  /// and a result register in the given register class.
238  ///
239  unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
240                           const TargetRegisterClass *RC,
241                           unsigned Op0, unsigned Op1);
242
243  /// FastEmitInst_ri - Emit a MachineInstr with two register operands
244  /// and a result register in the given register class.
245  ///
246  unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
247                           const TargetRegisterClass *RC,
248                           unsigned Op0, uint64_t Imm);
249
250  /// FastEmitInst_rf - Emit a MachineInstr with two register operands
251  /// and a result register in the given register class.
252  ///
253  unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
254                           const TargetRegisterClass *RC,
255                           unsigned Op0, ConstantFP *FPImm);
256
257  /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
258  /// an immediate, and a result register in the given register class.
259  ///
260  unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
261                            const TargetRegisterClass *RC,
262                            unsigned Op0, unsigned Op1, uint64_t Imm);
263
264  /// FastEmitInst_i - Emit a MachineInstr with a single immediate
265  /// operand, and a result register in the given register class.
266  unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
267                          const TargetRegisterClass *RC,
268                          uint64_t Imm);
269
270  /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
271  /// from a specified index of a superregister to a specified type.
272  unsigned FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT,
273                                      unsigned Op0, uint32_t Idx);
274
275  /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
276  /// with all but the least significant bit set to zero.
277  unsigned FastEmitZExtFromI1(MVT::SimpleValueType VT,
278                              unsigned Op);
279
280  /// FastEmitBranch - Emit an unconditional branch to the given block,
281  /// unless it is the immediate (fall-through) successor, and update
282  /// the CFG.
283  void FastEmitBranch(MachineBasicBlock *MBB);
284
285  unsigned UpdateValueMap(Value* I, unsigned Reg);
286
287  unsigned createResultReg(const TargetRegisterClass *RC);
288
289  /// TargetMaterializeConstant - Emit a constant in a register using
290  /// target-specific logic, such as constant pool loads.
291  virtual unsigned TargetMaterializeConstant(Constant* C) {
292    return 0;
293  }
294
295  /// TargetMaterializeAlloca - Emit an alloca address in a register using
296  /// target-specific logic.
297  virtual unsigned TargetMaterializeAlloca(AllocaInst* C) {
298    return 0;
299  }
300
301private:
302  bool SelectBinaryOp(User *I, ISD::NodeType ISDOpcode);
303
304  bool SelectGetElementPtr(User *I);
305
306  bool SelectCall(User *I);
307
308  bool SelectBitCast(User *I);
309
310  bool SelectCast(User *I, ISD::NodeType Opcode);
311};
312
313}
314
315#endif
316