FastISel.h revision f59514152511694d46ca8b8d2db466d256ab5759 
1//===-- FastISel.h - Definition of the FastISel class ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the FastISel class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_FASTISEL_H
15#define LLVM_CODEGEN_FASTISEL_H
16
17#include "llvm/ADT/DenseMap.h"
18#ifndef NDEBUG
19#include "llvm/ADT/SmallSet.h"
20#endif
21#include "llvm/CodeGen/ValueTypes.h"
22
23namespace llvm {
24
25class AllocaInst;
26class ConstantFP;
27class FunctionLoweringInfo;
28class Instruction;
29class MachineBasicBlock;
30class MachineConstantPool;
31class MachineFunction;
32class MachineInstr;
33class MachineFrameInfo;
34class MachineRegisterInfo;
35class TargetData;
36class TargetInstrInfo;
37class TargetLowering;
38class TargetMachine;
39class TargetRegisterClass;
40class TargetRegisterInfo;
41
42/// FastISel - This is a fast-path instruction selection class that
43/// generates poor code and doesn't support illegal types or non-trivial
44/// lowering, but runs quickly.
45class FastISel {
46protected:
47  MachineBasicBlock *MBB;
48  DenseMap<const Value *, unsigned> LocalValueMap;
49  FunctionLoweringInfo &FuncInfo;
50  MachineRegisterInfo &MRI;
51  MachineFrameInfo &MFI;
52  MachineConstantPool &MCP;
53  DebugLoc DL;
54  const TargetMachine &TM;
55  const TargetData &TD;
56  const TargetInstrInfo &TII;
57  const TargetLowering &TLI;
58  const TargetRegisterInfo &TRI;
59  bool IsBottomUp;
60
61public:
62  /// startNewBlock - Set the current block to which generated machine
63  /// instructions will be appended, and clear the local CSE map.
64  ///
65  void startNewBlock(MachineBasicBlock *mbb) {
66    setCurrentBlock(mbb);
67    LocalValueMap.clear();
68  }
69
70  /// setCurrentBlock - Set the current block to which generated machine
71  /// instructions will be appended.
72  ///
73  void setCurrentBlock(MachineBasicBlock *mbb) {
74    MBB = mbb;
75  }
76
77  /// getCurDebugLoc() - Return current debug location information.
78  DebugLoc getCurDebugLoc() const { return DL; }
79
80  /// SelectInstruction - Do "fast" instruction selection for the given
81  /// LLVM IR instruction, and append generated machine instructions to
82  /// the current block. Return true if selection was successful.
83  ///
84  bool SelectInstruction(const Instruction *I);
85
86  /// SelectOperator - Do "fast" instruction selection for the given
87  /// LLVM IR operator (Instruction or ConstantExpr), and append
88  /// generated machine instructions to the current block. Return true
89  /// if selection was successful.
90  ///
91  bool SelectOperator(const User *I, unsigned Opcode);
92
93  /// getRegForValue - Create a virtual register and arrange for it to
94  /// be assigned the value for the given LLVM value.
95  unsigned getRegForValue(const Value *V);
96
97  /// lookUpRegForValue - Look up the value to see if its value is already
98  /// cached in a register. It may be defined by instructions across blocks or
99  /// defined locally.
100  unsigned lookUpRegForValue(const Value *V);
101
102  /// getRegForGEPIndex - This is a wrapper around getRegForValue that also
103  /// takes care of truncating or sign-extending the given getelementptr
104  /// index value.
105  std::pair<unsigned, bool> getRegForGEPIndex(const Value *V);
106
107  virtual ~FastISel();
108
109protected:
110  explicit FastISel(FunctionLoweringInfo &funcInfo);
111
112  /// TargetSelectInstruction - This method is called by target-independent
113  /// code when the normal FastISel process fails to select an instruction.
114  /// This gives targets a chance to emit code for anything that doesn't
115  /// fit into FastISel's framework. It returns true if it was successful.
116  ///
117  virtual bool
118  TargetSelectInstruction(const Instruction *I) = 0;
119
120  /// FastEmit_r - This method is called by target-independent code
121  /// to request that an instruction with the given type and opcode
122  /// be emitted.
123  virtual unsigned FastEmit_(MVT VT,
124                             MVT RetVT,
125                             unsigned Opcode);
126
127  /// FastEmit_r - This method is called by target-independent code
128  /// to request that an instruction with the given type, opcode, and
129  /// register operand be emitted.
130  ///
131  virtual unsigned FastEmit_r(MVT VT,
132                              MVT RetVT,
133                              unsigned Opcode,
134                              unsigned Op0, bool Op0IsKill);
135
136  /// FastEmit_rr - This method is called by target-independent code
137  /// to request that an instruction with the given type, opcode, and
138  /// register operands be emitted.
139  ///
140  virtual unsigned FastEmit_rr(MVT VT,
141                               MVT RetVT,
142                               unsigned Opcode,
143                               unsigned Op0, bool Op0IsKill,
144                               unsigned Op1, bool Op1IsKill);
145
146  /// FastEmit_ri - This method is called by target-independent code
147  /// to request that an instruction with the given type, opcode, and
148  /// register and immediate operands be emitted.
149  ///
150  virtual unsigned FastEmit_ri(MVT VT,
151                               MVT RetVT,
152                               unsigned Opcode,
153                               unsigned Op0, bool Op0IsKill,
154                               uint64_t Imm);
155
156  /// FastEmit_rf - This method is called by target-independent code
157  /// to request that an instruction with the given type, opcode, and
158  /// register and floating-point immediate operands be emitted.
159  ///
160  virtual unsigned FastEmit_rf(MVT VT,
161                               MVT RetVT,
162                               unsigned Opcode,
163                               unsigned Op0, bool Op0IsKill,
164                               const ConstantFP *FPImm);
165
166  /// FastEmit_rri - This method is called by target-independent code
167  /// to request that an instruction with the given type, opcode, and
168  /// register and immediate operands be emitted.
169  ///
170  virtual unsigned FastEmit_rri(MVT VT,
171                                MVT RetVT,
172                                unsigned Opcode,
173                                unsigned Op0, bool Op0IsKill,
174                                unsigned Op1, bool Op1IsKill,
175                                uint64_t Imm);
176
177  /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
178  /// to emit an instruction with an immediate operand using FastEmit_ri.
179  /// If that fails, it materializes the immediate into a register and try
180  /// FastEmit_rr instead.
181  unsigned FastEmit_ri_(MVT VT,
182                        unsigned Opcode,
183                        unsigned Op0, bool Op0IsKill,
184                        uint64_t Imm, MVT ImmType);
185
186  /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
187  /// to emit an instruction with an immediate operand using FastEmit_rf.
188  /// If that fails, it materializes the immediate into a register and try
189  /// FastEmit_rr instead.
190  unsigned FastEmit_rf_(MVT VT,
191                        unsigned Opcode,
192                        unsigned Op0, bool Op0IsKill,
193                        const ConstantFP *FPImm, MVT ImmType);
194
195  /// FastEmit_i - This method is called by target-independent code
196  /// to request that an instruction with the given type, opcode, and
197  /// immediate operand be emitted.
198  virtual unsigned FastEmit_i(MVT VT,
199                              MVT RetVT,
200                              unsigned Opcode,
201                              uint64_t Imm);
202
203  /// FastEmit_f - This method is called by target-independent code
204  /// to request that an instruction with the given type, opcode, and
205  /// floating-point immediate operand be emitted.
206  virtual unsigned FastEmit_f(MVT VT,
207                              MVT RetVT,
208                              unsigned Opcode,
209                              const ConstantFP *FPImm);
210
211  /// FastEmitInst_ - Emit a MachineInstr with no operands and a
212  /// result register in the given register class.
213  ///
214  unsigned FastEmitInst_(unsigned MachineInstOpcode,
215                         const TargetRegisterClass *RC);
216
217  /// FastEmitInst_r - Emit a MachineInstr with one register operand
218  /// and a result register in the given register class.
219  ///
220  unsigned FastEmitInst_r(unsigned MachineInstOpcode,
221                          const TargetRegisterClass *RC,
222                          unsigned Op0, bool Op0IsKill);
223
224  /// FastEmitInst_rr - Emit a MachineInstr with two register operands
225  /// and a result register in the given register class.
226  ///
227  unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
228                           const TargetRegisterClass *RC,
229                           unsigned Op0, bool Op0IsKill,
230                           unsigned Op1, bool Op1IsKill);
231
232  /// FastEmitInst_ri - Emit a MachineInstr with two register operands
233  /// and a result register in the given register class.
234  ///
235  unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
236                           const TargetRegisterClass *RC,
237                           unsigned Op0, bool Op0IsKill,
238                           uint64_t Imm);
239
240  /// FastEmitInst_rf - Emit a MachineInstr with two register operands
241  /// and a result register in the given register class.
242  ///
243  unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
244                           const TargetRegisterClass *RC,
245                           unsigned Op0, bool Op0IsKill,
246                           const ConstantFP *FPImm);
247
248  /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
249  /// an immediate, and a result register in the given register class.
250  ///
251  unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
252                            const TargetRegisterClass *RC,
253                            unsigned Op0, bool Op0IsKill,
254                            unsigned Op1, bool Op1IsKill,
255                            uint64_t Imm);
256
257  /// FastEmitInst_i - Emit a MachineInstr with a single immediate
258  /// operand, and a result register in the given register class.
259  unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
260                          const TargetRegisterClass *RC,
261                          uint64_t Imm);
262
263  /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
264  /// from a specified index of a superregister to a specified type.
265  unsigned FastEmitInst_extractsubreg(MVT RetVT,
266                                      unsigned Op0, bool Op0IsKill,
267                                      uint32_t Idx);
268
269  /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
270  /// with all but the least significant bit set to zero.
271  unsigned FastEmitZExtFromI1(MVT VT,
272                              unsigned Op0, bool Op0IsKill);
273
274  /// FastEmitBranch - Emit an unconditional branch to the given block,
275  /// unless it is the immediate (fall-through) successor, and update
276  /// the CFG.
277  void FastEmitBranch(MachineBasicBlock *MBB, DebugLoc DL);
278
279  unsigned UpdateValueMap(const Value* I, unsigned Reg);
280
281  unsigned createResultReg(const TargetRegisterClass *RC);
282
283  /// TargetMaterializeConstant - Emit a constant in a register using
284  /// target-specific logic, such as constant pool loads.
285  virtual unsigned TargetMaterializeConstant(const Constant* C) {
286    return 0;
287  }
288
289  /// TargetMaterializeAlloca - Emit an alloca address in a register using
290  /// target-specific logic.
291  virtual unsigned TargetMaterializeAlloca(const AllocaInst* C) {
292    return 0;
293  }
294
295private:
296  bool SelectLoad(const User *I);
297
298  bool SelectBinaryOp(const User *I, unsigned ISDOpcode);
299
300  bool SelectFNeg(const User *I);
301
302  bool SelectGetElementPtr(const User *I);
303
304  bool SelectCall(const User *I);
305
306  bool SelectBitCast(const User *I);
307
308  bool SelectCast(const User *I, unsigned Opcode);
309
310  /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks.
311  /// Emit code to ensure constants are copied into registers when needed.
312  /// Remember the virtual registers that need to be added to the Machine PHI
313  /// nodes as input.  We cannot just directly add them, because expansion
314  /// might result in multiple MBB's for one BB.  As such, the start of the
315  /// BB might correspond to a different MBB than the end.
316  bool HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
317
318  /// materializeRegForValue - Helper for getRegForVale. This function is
319  /// called when the value isn't already available in a register and must
320  /// be materialized with new instructions.
321  unsigned materializeRegForValue(const Value *V, MVT VT);
322
323  /// hasTrivialKill - Test whether the given value has exactly one use.
324  bool hasTrivialKill(const Value *V) const;
325};
326
327}
328
329#endif
330