MachineRegisterInfo.h revision e138b3dd1ff02d826233482831318708a166ed93
1//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the MachineRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 15#define LLVM_CODEGEN_MACHINEREGISTERINFO_H 16 17#include "llvm/Target/MRegisterInfo.h" 18#include "llvm/ADT/BitVector.h" 19#include "llvm/ADT/iterator" 20#include <vector> 21 22namespace llvm { 23 24/// MachineRegisterInfo - Keep track of information for each virtual register, 25/// including its register class. 26class MachineRegisterInfo { 27 /// VRegInfo - Information we keep for each virtual register. The entries in 28 /// this vector are actually converted to vreg numbers by adding the 29 /// MRegisterInfo::FirstVirtualRegister delta to their index. 30 /// 31 /// Each element in this list contains the register class of the vreg and the 32 /// start of the use/def list for the register. 33 std::vector<std::pair<const TargetRegisterClass*, MachineOperand*> > VRegInfo; 34 35 /// PhysRegUseDefLists - This is an array of the head of the use/def list for 36 /// physical registers. 37 MachineOperand **PhysRegUseDefLists; 38 39 /// UsedPhysRegs - This is a bit vector that is computed and set by the 40 /// register allocator, and must be kept up to date by passes that run after 41 /// register allocation (though most don't modify this). This is used 42 /// so that the code generator knows which callee save registers to save and 43 /// for other target specific uses. 44 BitVector UsedPhysRegs; 45 46 /// LiveIns/LiveOuts - Keep track of the physical registers that are 47 /// livein/liveout of the function. Live in values are typically arguments in 48 /// registers, live out values are typically return values in registers. 49 /// LiveIn values are allowed to have virtual registers associated with them, 50 /// stored in the second element. 51 std::vector<std::pair<unsigned, unsigned> > LiveIns; 52 std::vector<unsigned> LiveOuts; 53 54 MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT 55 void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT 56public: 57 MachineRegisterInfo(const MRegisterInfo &MRI); 58 ~MachineRegisterInfo(); 59 60 //===--------------------------------------------------------------------===// 61 // Register Info 62 //===--------------------------------------------------------------------===// 63 64 /// reg_begin/reg_end - Provide iteration support to walk over all definitions 65 /// and uses of a register within the MachineFunction that corresponds to this 66 /// MachineRegisterInfo object. 67 class reg_iterator; 68 reg_iterator reg_begin(unsigned RegNo) const { 69 return reg_iterator(getRegUseDefListHead(RegNo)); 70 } 71 static reg_iterator reg_end() { return reg_iterator(0); } 72 73 /// replaceRegWith - Replace all instances of FromReg with ToReg in the 74 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 75 /// except that it also changes any definitions of the register as well. 76 void replaceRegWith(unsigned FromReg, unsigned ToReg); 77 78 /// getRegUseDefListHead - Return the head pointer for the register use/def 79 /// list for the specified virtual or physical register. 80 MachineOperand *&getRegUseDefListHead(unsigned RegNo) { 81 if (RegNo < MRegisterInfo::FirstVirtualRegister) 82 return PhysRegUseDefLists[RegNo]; 83 RegNo -= MRegisterInfo::FirstVirtualRegister; 84 return VRegInfo[RegNo].second; 85 } 86 87 MachineOperand *getRegUseDefListHead(unsigned RegNo) const { 88 if (RegNo < MRegisterInfo::FirstVirtualRegister) 89 return PhysRegUseDefLists[RegNo]; 90 RegNo -= MRegisterInfo::FirstVirtualRegister; 91 return VRegInfo[RegNo].second; 92 } 93 94 //===--------------------------------------------------------------------===// 95 // Virtual Register Info 96 //===--------------------------------------------------------------------===// 97 98 /// getRegClass - Return the register class of the specified virtual register. 99 const TargetRegisterClass *getRegClass(unsigned Reg) { 100 Reg -= MRegisterInfo::FirstVirtualRegister; 101 assert(Reg < VRegInfo.size() && "Invalid vreg!"); 102 return VRegInfo[Reg].first; 103 } 104 105 /// createVirtualRegister - Create and return a new virtual register in the 106 /// function with the specified register class. 107 /// 108 unsigned createVirtualRegister(const TargetRegisterClass *RegClass) { 109 assert(RegClass && "Cannot create register without RegClass!"); 110 // Add a reg, but keep track of whether the vector reallocated or not. 111 void *ArrayBase = &VRegInfo[0]; 112 VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0)); 113 114 if (&VRegInfo[0] == ArrayBase) 115 return getLastVirtReg(); 116 117 // Otherwise, the vector reallocated, handle this now. 118 HandleVRegListReallocation(); 119 return getLastVirtReg(); 120 } 121 122 /// getLastVirtReg - Return the highest currently assigned virtual register. 123 /// 124 unsigned getLastVirtReg() const { 125 return VRegInfo.size()+MRegisterInfo::FirstVirtualRegister-1; 126 } 127 128 /// getVRegDef - Return the machine instr that defines the specified virtual 129 /// register or null if none is found. This assumes that the code is in SSA 130 /// form, so there should only be one definition. 131 MachineInstr *getVRegDef(unsigned Reg) const; 132 133 134 //===--------------------------------------------------------------------===// 135 // Physical Register Use Info 136 //===--------------------------------------------------------------------===// 137 138 /// isPhysRegUsed - Return true if the specified register is used in this 139 /// function. This only works after register allocation. 140 bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; } 141 142 /// setPhysRegUsed - Mark the specified register used in this function. 143 /// This should only be called during and after register allocation. 144 void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; } 145 146 /// setPhysRegUnused - Mark the specified register unused in this function. 147 /// This should only be called during and after register allocation. 148 void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; } 149 150 151 //===--------------------------------------------------------------------===// 152 // LiveIn/LiveOut Management 153 //===--------------------------------------------------------------------===// 154 155 /// addLiveIn/Out - Add the specified register as a live in/out. Note that it 156 /// is an error to add the same register to the same set more than once. 157 void addLiveIn(unsigned Reg, unsigned vreg = 0) { 158 LiveIns.push_back(std::make_pair(Reg, vreg)); 159 } 160 void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); } 161 162 // Iteration support for live in/out sets. These sets are kept in sorted 163 // order by their register number. 164 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator 165 livein_iterator; 166 typedef std::vector<unsigned>::const_iterator liveout_iterator; 167 livein_iterator livein_begin() const { return LiveIns.begin(); } 168 livein_iterator livein_end() const { return LiveIns.end(); } 169 bool livein_empty() const { return LiveIns.empty(); } 170 liveout_iterator liveout_begin() const { return LiveOuts.begin(); } 171 liveout_iterator liveout_end() const { return LiveOuts.end(); } 172 bool liveout_empty() const { return LiveOuts.empty(); } 173private: 174 void HandleVRegListReallocation(); 175 176public: 177 /// reg_iterator - This class provides iterator support for machine 178 /// operands in the function that use or define a specific register. 179 class reg_iterator : public forward_iterator<MachineInstr, ptrdiff_t> { 180 MachineOperand *Op; 181 reg_iterator(MachineOperand *op) : Op(op) {} 182 friend class MachineRegisterInfo; 183 public: 184 typedef forward_iterator<MachineInstr, ptrdiff_t>::reference reference; 185 typedef forward_iterator<MachineInstr, ptrdiff_t>::pointer pointer; 186 187 reg_iterator(const reg_iterator &I) : Op(I.Op) {} 188 reg_iterator() : Op(0) {} 189 190 bool operator==(const reg_iterator &x) const { 191 return Op == x.Op; 192 } 193 bool operator!=(const reg_iterator &x) const { 194 return !operator==(x); 195 } 196 197 /// atEnd - return true if this iterator is equal to reg_end() on the value. 198 bool atEnd() const { return Op == 0; } 199 200 // Iterator traversal: forward iteration only 201 reg_iterator &operator++() { // Preincrement 202 assert(Op && "Cannot increment end iterator!"); 203 Op = Op->getNextOperandForReg(); 204 return *this; 205 } 206 reg_iterator operator++(int) { // Postincrement 207 reg_iterator tmp = *this; ++*this; return tmp; 208 } 209 210 MachineOperand &getOperand() const { 211 assert(Op && "Cannot dereference end iterator!"); 212 return *Op; 213 } 214 215 /// getOperandNo - Return the operand # of this MachineOperand in its 216 /// MachineInstr. 217 unsigned getOperandNo() const { 218 assert(Op && "Cannot dereference end iterator!"); 219 return Op - &Op->getParent()->getOperand(0); 220 } 221 222 // Retrieve a reference to the current operand. 223 MachineInstr &operator*() const { 224 assert(Op && "Cannot dereference end iterator!"); 225 return *Op->getParent(); 226 } 227 228 MachineInstr *operator->() const { 229 assert(Op && "Cannot dereference end iterator!"); 230 return Op->getParent(); 231 } 232 }; 233 234}; 235 236} // End llvm namespace 237 238#endif 239