TargetInstrInfo.h revision 58dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instructions to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/Target/TargetInstrDesc.h" 18#include "llvm/CodeGen/MachineFunction.h" 19 20namespace llvm { 21 22class TargetRegisterClass; 23class LiveVariables; 24class CalleeSavedInfo; 25class SDNode; 26class SelectionDAG; 27 28template<class T> class SmallVectorImpl; 29 30 31//--------------------------------------------------------------------------- 32/// 33/// TargetInstrInfo - Interface to description of machine instructions 34/// 35class TargetInstrInfo { 36 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n 37 unsigned NumOpcodes; // Number of entries in the desc array 38 39 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 40 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 41public: 42 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes); 43 virtual ~TargetInstrInfo(); 44 45 // Invariant opcodes: All instruction sets have these as their low opcodes. 46 enum { 47 PHI = 0, 48 INLINEASM = 1, 49 LABEL = 2, 50 DECLARE = 3, 51 EXTRACT_SUBREG = 4, 52 INSERT_SUBREG = 5, 53 IMPLICIT_DEF = 6, 54 SUBREG_TO_REG = 7 55 }; 56 57 unsigned getNumOpcodes() const { return NumOpcodes; } 58 59 /// get - Return the machine instruction descriptor that corresponds to the 60 /// specified instruction opcode. 61 /// 62 const TargetInstrDesc &get(unsigned Opcode) const { 63 assert(Opcode < NumOpcodes && "Invalid opcode!"); 64 return Descriptors[Opcode]; 65 } 66 67 /// isTriviallyReMaterializable - Return true if the instruction is trivially 68 /// rematerializable, meaning it has no side effects and requires no operands 69 /// that aren't always available. 70 bool isTriviallyReMaterializable(const MachineInstr *MI) const { 71 return MI->getDesc().isRematerializable() && 72 isReallyTriviallyReMaterializable(MI); 73 } 74 75protected: 76 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 77 /// which the M_REMATERIALIZABLE flag is set, this function tests whether the 78 /// instruction itself is actually trivially rematerializable, considering 79 /// its operands. This is used for targets that have instructions that are 80 /// only trivially rematerializable for specific uses. This predicate must 81 /// return false if the instruction has any side effects other than 82 /// producing a value, or if it requres any address registers that are not 83 /// always available. 84 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const { 85 return true; 86 } 87 88public: 89 /// Return true if the instruction is a register to register move 90 /// and leave the source and dest operands in the passed parameters. 91 virtual bool isMoveInstr(const MachineInstr& MI, 92 unsigned& sourceReg, 93 unsigned& destReg) const { 94 return false; 95 } 96 97 /// isLoadFromStackSlot - If the specified machine instruction is a direct 98 /// load from a stack slot, return the virtual or physical register number of 99 /// the destination along with the FrameIndex of the loaded stack slot. If 100 /// not, return 0. This predicate must return 0 if the instruction has 101 /// any side effects other than loading from the stack slot. 102 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{ 103 return 0; 104 } 105 106 /// isStoreToStackSlot - If the specified machine instruction is a direct 107 /// store to a stack slot, return the virtual or physical register number of 108 /// the source reg along with the FrameIndex of the loaded stack slot. If 109 /// not, return 0. This predicate must return 0 if the instruction has 110 /// any side effects other than storing to the stack slot. 111 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { 112 return 0; 113 } 114 115 /// reMaterialize - Re-issue the specified 'original' instruction at the 116 /// specific location targeting a new destination register. 117 virtual void reMaterialize(MachineBasicBlock &MBB, 118 MachineBasicBlock::iterator MI, 119 unsigned DestReg, 120 const MachineInstr *Orig) const = 0; 121 122 /// isInvariantLoad - Return true if the specified instruction (which is 123 /// marked mayLoad) is loading from a location whose value is invariant across 124 /// the function. For example, loading a value from the constant pool or from 125 /// from the argument area of a function if it does not change. This should 126 /// only return true of *all* loads the instruction does are invariant (if it 127 /// does multiple loads). 128 virtual bool isInvariantLoad(MachineInstr *MI) const { 129 return false; 130 } 131 132 /// convertToThreeAddress - This method must be implemented by targets that 133 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 134 /// may be able to convert a two-address instruction into one or more true 135 /// three-address instructions on demand. This allows the X86 target (for 136 /// example) to convert ADD and SHL instructions into LEA instructions if they 137 /// would require register copies due to two-addressness. 138 /// 139 /// This method returns a null pointer if the transformation cannot be 140 /// performed, otherwise it returns the last new instruction. 141 /// 142 virtual MachineInstr * 143 convertToThreeAddress(MachineFunction::iterator &MFI, 144 MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const { 145 return 0; 146 } 147 148 /// commuteInstruction - If a target has any instructions that are commutable, 149 /// but require converting to a different instruction or making non-trivial 150 /// changes to commute them, this method can overloaded to do this. The 151 /// default implementation of this method simply swaps the first two operands 152 /// of MI and returns it. 153 /// 154 /// If a target wants to make more aggressive changes, they can construct and 155 /// return a new machine instruction. If an instruction cannot commute, it 156 /// can also return null. 157 /// 158 /// If NewMI is true, then a new machine instruction must be created. 159 /// 160 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 161 bool NewMI = false) const = 0; 162 163 /// CommuteChangesDestination - Return true if commuting the specified 164 /// instruction will also changes the destination operand. Also return the 165 /// current operand index of the would be new destination register by 166 /// reference. This can happen when the commutable instruction is also a 167 /// two-address instruction. 168 virtual bool CommuteChangesDestination(MachineInstr *MI, 169 unsigned &OpIdx) const = 0; 170 171 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 172 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 173 /// implemented for a target). Upon success, this returns false and returns 174 /// with the following information in various cases: 175 /// 176 /// 1. If this block ends with no branches (it just falls through to its succ) 177 /// just return false, leaving TBB/FBB null. 178 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 179 /// the destination block. 180 /// 3. If this block ends with an conditional branch and it falls through to 181 /// an successor block, it sets TBB to be the branch destination block and a 182 /// list of operands that evaluate the condition. These 183 /// operands can be passed to other TargetInstrInfo methods to create new 184 /// branches. 185 /// 4. If this block ends with an conditional branch and an unconditional 186 /// block, it returns the 'true' destination in TBB, the 'false' destination 187 /// in FBB, and a list of operands that evaluate the condition. These 188 /// operands can be passed to other TargetInstrInfo methods to create new 189 /// branches. 190 /// 191 /// Note that RemoveBranch and InsertBranch must be implemented to support 192 /// cases where this method returns success. 193 /// 194 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 195 MachineBasicBlock *&FBB, 196 std::vector<MachineOperand> &Cond) const { 197 return true; 198 } 199 200 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 201 /// this is only invoked in cases where AnalyzeBranch returns success. It 202 /// returns the number of instructions that were removed. 203 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 204 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 205 return 0; 206 } 207 208 /// InsertBranch - Insert a branch into the end of the specified 209 /// MachineBasicBlock. This operands to this method are the same as those 210 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch 211 /// returns success and when an unconditional branch (TBB is non-null, FBB is 212 /// null, Cond is empty) needs to be inserted. It returns the number of 213 /// instructions inserted. 214 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 215 MachineBasicBlock *FBB, 216 const std::vector<MachineOperand> &Cond) const { 217 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 218 return 0; 219 } 220 221 /// copyRegToReg - Add a copy between a pair of registers 222 virtual void copyRegToReg(MachineBasicBlock &MBB, 223 MachineBasicBlock::iterator MI, 224 unsigned DestReg, unsigned SrcReg, 225 const TargetRegisterClass *DestRC, 226 const TargetRegisterClass *SrcRC) const { 227 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!"); 228 } 229 230 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 231 MachineBasicBlock::iterator MI, 232 unsigned SrcReg, bool isKill, int FrameIndex, 233 const TargetRegisterClass *RC) const { 234 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 235 } 236 237 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 238 SmallVectorImpl<MachineOperand> &Addr, 239 const TargetRegisterClass *RC, 240 SmallVectorImpl<MachineInstr*> &NewMIs) const { 241 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!"); 242 } 243 244 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 245 MachineBasicBlock::iterator MI, 246 unsigned DestReg, int FrameIndex, 247 const TargetRegisterClass *RC) const { 248 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 249 } 250 251 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 252 SmallVectorImpl<MachineOperand> &Addr, 253 const TargetRegisterClass *RC, 254 SmallVectorImpl<MachineInstr*> &NewMIs) const { 255 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!"); 256 } 257 258 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee 259 /// saved registers and returns true if it isn't possible / profitable to do 260 /// so by issuing a series of store instructions via 261 /// storeRegToStackSlot(). Returns false otherwise. 262 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 263 MachineBasicBlock::iterator MI, 264 const std::vector<CalleeSavedInfo> &CSI) const { 265 return false; 266 } 267 268 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee 269 /// saved registers and returns true if it isn't possible / profitable to do 270 /// so by issuing a series of load instructions via loadRegToStackSlot(). 271 /// Returns false otherwise. 272 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 273 MachineBasicBlock::iterator MI, 274 const std::vector<CalleeSavedInfo> &CSI) const { 275 return false; 276 } 277 278 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 279 /// slot into the specified machine instruction for the specified operand(s). 280 /// If this is possible, a new instruction is returned with the specified 281 /// operand folded, otherwise NULL is returned. The client is responsible for 282 /// removing the old instruction and adding the new one in the instruction 283 /// stream. 284 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, 285 MachineInstr* MI, 286 SmallVectorImpl<unsigned> &Ops, 287 int FrameIndex) const { 288 return 0; 289 } 290 291 /// foldMemoryOperand - Same as the previous version except it allows folding 292 /// of any load and store from / to any address, not just from a specific 293 /// stack slot. 294 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF, 295 MachineInstr* MI, 296 SmallVectorImpl<unsigned> &Ops, 297 MachineInstr* LoadMI) const { 298 return 0; 299 } 300 301 /// canFoldMemoryOperand - Returns true if the specified load / store is 302 /// folding is possible. 303 virtual 304 bool canFoldMemoryOperand(MachineInstr *MI, 305 SmallVectorImpl<unsigned> &Ops) const{ 306 return false; 307 } 308 309 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 310 /// a store or a load and a store into two or more instruction. If this is 311 /// possible, returns true as well as the new instructions by reference. 312 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 313 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 314 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 315 return false; 316 } 317 318 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 319 SmallVectorImpl<SDNode*> &NewNodes) const { 320 return false; 321 } 322 323 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 324 /// instruction after load / store are unfolded from an instruction of the 325 /// specified opcode. It returns zero if the specified unfolding is not 326 /// possible. 327 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 328 bool UnfoldLoad, bool UnfoldStore) const { 329 return 0; 330 } 331 332 /// BlockHasNoFallThrough - Return true if the specified block does not 333 /// fall-through into its successor block. This is primarily used when a 334 /// branch is unanalyzable. It is useful for things like unconditional 335 /// indirect branches (jump tables). 336 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const { 337 return false; 338 } 339 340 /// ReverseBranchCondition - Reverses the branch condition of the specified 341 /// condition list, returning false on success and true if it cannot be 342 /// reversed. 343 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const { 344 return true; 345 } 346 347 /// insertNoop - Insert a noop into the instruction stream at the specified 348 /// point. 349 virtual void insertNoop(MachineBasicBlock &MBB, 350 MachineBasicBlock::iterator MI) const { 351 assert(0 && "Target didn't implement insertNoop!"); 352 abort(); 353 } 354 355 /// isPredicated - Returns true if the instruction is already predicated. 356 /// 357 virtual bool isPredicated(const MachineInstr *MI) const { 358 return false; 359 } 360 361 /// isUnpredicatedTerminator - Returns true if the instruction is a 362 /// terminator instruction that has not been predicated. 363 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 364 365 /// PredicateInstruction - Convert the instruction into a predicated 366 /// instruction. It returns true if the operation was successful. 367 virtual 368 bool PredicateInstruction(MachineInstr *MI, 369 const std::vector<MachineOperand> &Pred) const = 0; 370 371 /// SubsumesPredicate - Returns true if the first specified predicate 372 /// subsumes the second, e.g. GE subsumes GT. 373 virtual 374 bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1, 375 const std::vector<MachineOperand> &Pred2) const { 376 return false; 377 } 378 379 /// DefinesPredicate - If the specified instruction defines any predicate 380 /// or condition code register(s) used for predication, returns true as well 381 /// as the definition predicate(s) by reference. 382 virtual bool DefinesPredicate(MachineInstr *MI, 383 std::vector<MachineOperand> &Pred) const { 384 return false; 385 } 386 387 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 388 /// values. 389 virtual const TargetRegisterClass *getPointerRegClass() const { 390 assert(0 && "Target didn't implement getPointerRegClass!"); 391 abort(); 392 return 0; // Must return a value in order to compile with VS 2005 393 } 394 395 /// GetInstSize - Returns the size of the specified Instruction. 396 /// 397 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const { 398 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!"); 399 return 0; 400 } 401 402 /// GetFunctionSizeInBytes - Returns the size of the specified MachineFunction. 403 /// 404 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0; 405 406}; 407 408/// TargetInstrInfoImpl - This is the default implementation of 409/// TargetInstrInfo, which just provides a couple of default implementations 410/// for various methods. This separated out because it is implemented in 411/// libcodegen, not in libtarget. 412class TargetInstrInfoImpl : public TargetInstrInfo { 413protected: 414 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes) 415 : TargetInstrInfo(desc, NumOpcodes) {} 416public: 417 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 418 bool NewMI = false) const; 419 virtual bool CommuteChangesDestination(MachineInstr *MI, 420 unsigned &OpIdx) const; 421 virtual bool PredicateInstruction(MachineInstr *MI, 422 const std::vector<MachineOperand> &Pred) const; 423 virtual void reMaterialize(MachineBasicBlock &MBB, 424 MachineBasicBlock::iterator MI, 425 unsigned DestReg, 426 const MachineInstr *Orig) const; 427 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const; 428}; 429 430} // End llvm namespace 431 432#endif 433