TargetInstrInfo.h revision ae72f4a642192abab5a2d10592200a94fcba61de
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instructions to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/CodeGen/MachineBasicBlock.h" 18#include "llvm/Support/DataTypes.h" 19#include <vector> 20#include <cassert> 21 22namespace llvm { 23 24class MachineInstr; 25class TargetMachine; 26class Value; 27class Type; 28class Instruction; 29class Constant; 30class Function; 31class MachineCodeForInstruction; 32class TargetRegisterClass; 33 34//--------------------------------------------------------------------------- 35// Data types used to define information about a single machine instruction 36//--------------------------------------------------------------------------- 37 38typedef short MachineOpCode; 39typedef unsigned InstrSchedClass; 40 41//--------------------------------------------------------------------------- 42// struct TargetInstrDescriptor: 43// Predefined information about each machine instruction. 44// Designed to initialized statically. 45// 46 47const unsigned M_NOP_FLAG = 1 << 0; 48const unsigned M_BRANCH_FLAG = 1 << 1; 49const unsigned M_CALL_FLAG = 1 << 2; 50const unsigned M_RET_FLAG = 1 << 3; 51const unsigned M_BARRIER_FLAG = 1 << 4; 52const unsigned M_DELAY_SLOT_FLAG = 1 << 5; 53const unsigned M_CC_FLAG = 1 << 6; 54const unsigned M_LOAD_FLAG = 1 << 7; 55const unsigned M_STORE_FLAG = 1 << 8; 56 57// M_2_ADDR_FLAG - 3-addr instructions which really work like 2-addr ones. 58const unsigned M_2_ADDR_FLAG = 1 << 9; 59 60// M_CONVERTIBLE_TO_3_ADDR - This is a M_2_ADDR_FLAG instruction which can be 61// changed into a 3-address instruction if the first two operands cannot be 62// assigned to the same register. The target must implement the 63// TargetInstrInfo::convertToThreeAddress method for this instruction. 64const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 10; 65 66// This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y, 67// Z), which produces the same result if Y and Z are exchanged. 68const unsigned M_COMMUTABLE = 1 << 11; 69 70// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic 71// block? Typically this is things like return and branch instructions. 72// Various passes use this to insert code into the bottom of a basic block, but 73// before control flow occurs. 74const unsigned M_TERMINATOR_FLAG = 1 << 12; 75 76/// TargetOperandInfo - This holds information about one operand of a machine 77/// instruction, indicating the register class for register operands, etc. 78/// 79class TargetOperandInfo { 80public: 81 /// RegClass - This specifies the register class of the operand if the 82 /// operand is a register. If not, this contains null. 83 const TargetRegisterClass *RegClass; 84 85 /// Currently no other information. 86}; 87 88 89class TargetInstrDescriptor { 90public: 91 const char * Name; // Assembly language mnemonic for the opcode. 92 int numOperands; // Number of args; -1 if variable #args 93 int resultPos; // Position of the result; -1 if no result 94 unsigned maxImmedConst; // Largest +ve constant in IMMED field or 0. 95 bool immedIsSignExtended; // Is IMMED field sign-extended? If so, 96 // smallest -ve value is -(maxImmedConst+1). 97 unsigned numDelaySlots; // Number of delay slots after instruction 98 unsigned latency; // Latency in machine cycles 99 InstrSchedClass schedClass; // enum identifying instr sched class 100 unsigned Flags; // flags identifying machine instr class 101 unsigned TSFlags; // Target Specific Flag values 102 const unsigned *ImplicitUses; // Registers implicitly read by this instr 103 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 104 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands. 105}; 106 107 108//--------------------------------------------------------------------------- 109/// 110/// TargetInstrInfo - Interface to description of machine instructions 111/// 112class TargetInstrInfo { 113 const TargetInstrDescriptor* desc; // raw array to allow static init'n 114 unsigned NumOpcodes; // number of entries in the desc array 115 unsigned numRealOpCodes; // number of non-dummy op codes 116 117 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 118 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 119public: 120 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes); 121 virtual ~TargetInstrInfo(); 122 123 // Invariant: All instruction sets use opcode #0 as the PHI instruction 124 enum { PHI = 0 }; 125 126 unsigned getNumOpcodes() const { return NumOpcodes; } 127 128 /// get - Return the machine instruction descriptor that corresponds to the 129 /// specified instruction opcode. 130 /// 131 const TargetInstrDescriptor& get(MachineOpCode Opcode) const { 132 assert((unsigned)Opcode < NumOpcodes); 133 return desc[Opcode]; 134 } 135 136 const char *getName(MachineOpCode Opcode) const { 137 return get(Opcode).Name; 138 } 139 140 int getNumOperands(MachineOpCode Opcode) const { 141 return get(Opcode).numOperands; 142 } 143 144 145 InstrSchedClass getSchedClass(MachineOpCode Opcode) const { 146 return get(Opcode).schedClass; 147 } 148 149 const unsigned *getImplicitUses(MachineOpCode Opcode) const { 150 return get(Opcode).ImplicitUses; 151 } 152 153 const unsigned *getImplicitDefs(MachineOpCode Opcode) const { 154 return get(Opcode).ImplicitDefs; 155 } 156 157 158 // 159 // Query instruction class flags according to the machine-independent 160 // flags listed above. 161 // 162 bool isReturn(MachineOpCode Opcode) const { 163 return get(Opcode).Flags & M_RET_FLAG; 164 } 165 166 bool isTwoAddrInstr(MachineOpCode Opcode) const { 167 return get(Opcode).Flags & M_2_ADDR_FLAG; 168 } 169 bool isTerminatorInstr(unsigned Opcode) const { 170 return get(Opcode).Flags & M_TERMINATOR_FLAG; 171 } 172 173 /// Return true if the instruction is a register to register move 174 /// and leave the source and dest operands in the passed parameters. 175 virtual bool isMoveInstr(const MachineInstr& MI, 176 unsigned& sourceReg, 177 unsigned& destReg) const { 178 return false; 179 } 180 181 /// convertToThreeAddress - This method must be implemented by targets that 182 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 183 /// may be able to convert a two-address instruction into a true 184 /// three-address instruction on demand. This allows the X86 target (for 185 /// example) to convert ADD and SHL instructions into LEA instructions if they 186 /// would require register copies due to two-addressness. 187 /// 188 /// This method returns a null pointer if the transformation cannot be 189 /// performed, otherwise it returns the new instruction. 190 /// 191 virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const { 192 return 0; 193 } 194 195 /// commuteInstruction - If a target has any instructions that are commutable, 196 /// but require converting to a different instruction or making non-trivial 197 /// changes to commute them, this method can overloaded to do this. The 198 /// default implementation of this method simply swaps the first two operands 199 /// of MI and returns it. 200 /// 201 /// If a target wants to make more aggressive changes, they can construct and 202 /// return a new machine instruction. If an instruction cannot commute, it 203 /// can also return null. 204 /// 205 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 206 207 /// Insert a goto (unconditional branch) sequence to TMBB, at the 208 /// end of MBB 209 virtual void insertGoto(MachineBasicBlock& MBB, 210 MachineBasicBlock& TMBB) const { 211 assert(0 && "Target didn't implement insertGoto!"); 212 } 213 214 /// Reverses the branch condition of the MachineInstr pointed by 215 /// MI. The instruction is replaced and the new MI is returned. 216 virtual MachineBasicBlock::iterator 217 reverseBranchCondition(MachineBasicBlock::iterator MI) const { 218 assert(0 && "Target didn't implement reverseBranchCondition!"); 219 abort(); 220 return MI; 221 } 222 223 //------------------------------------------------------------------------- 224 // Code generation support for creating individual machine instructions 225 // 226 // WARNING: These methods are Sparc specific 227 // 228 // DO NOT USE ANY OF THESE METHODS THEY ARE DEPRECATED! 229 // 230 //------------------------------------------------------------------------- 231 232 unsigned getNumDelaySlots(MachineOpCode Opcode) const { 233 return get(Opcode).numDelaySlots; 234 } 235 bool isCCInstr(MachineOpCode Opcode) const { 236 return get(Opcode).Flags & M_CC_FLAG; 237 } 238 bool isNop(MachineOpCode Opcode) const { 239 return get(Opcode).Flags & M_NOP_FLAG; 240 } 241 bool isBranch(MachineOpCode Opcode) const { 242 return get(Opcode).Flags & M_BRANCH_FLAG; 243 } 244 /// isBarrier - Returns true if the specified instruction stops control flow 245 /// from executing the instruction immediately following it. Examples include 246 /// unconditional branches and return instructions. 247 bool isBarrier(MachineOpCode Opcode) const { 248 return get(Opcode).Flags & M_BARRIER_FLAG; 249 } 250 251 bool isCall(MachineOpCode Opcode) const { 252 return get(Opcode).Flags & M_CALL_FLAG; 253 } 254 bool isLoad(MachineOpCode Opcode) const { 255 return get(Opcode).Flags & M_LOAD_FLAG; 256 } 257 bool isStore(MachineOpCode Opcode) const { 258 return get(Opcode).Flags & M_STORE_FLAG; 259 } 260 261 /// hasDelaySlot - Returns true if the specified instruction has a delay slot 262 /// which must be filled by the code generator. 263 bool hasDelaySlot(unsigned Opcode) const { 264 return get(Opcode).Flags & M_DELAY_SLOT_FLAG; 265 } 266 267 virtual bool hasResultInterlock(MachineOpCode Opcode) const { 268 return true; 269 } 270 271 // 272 // Latencies for individual instructions and instruction pairs 273 // 274 virtual int minLatency(MachineOpCode Opcode) const { 275 return get(Opcode).latency; 276 } 277 278 virtual int maxLatency(MachineOpCode Opcode) const { 279 return get(Opcode).latency; 280 } 281 282 // 283 // Which operand holds an immediate constant? Returns -1 if none 284 // 285 virtual int getImmedConstantPos(MachineOpCode Opcode) const { 286 return -1; // immediate position is machine specific, so say -1 == "none" 287 } 288 289 // Check if the specified constant fits in the immediate field 290 // of this machine instruction 291 // 292 virtual bool constantFitsInImmedField(MachineOpCode Opcode, 293 int64_t intValue) const; 294 295 // Return the largest positive constant that can be held in the IMMED field 296 // of this machine instruction. 297 // isSignExtended is set to true if the value is sign-extended before use 298 // (this is true for all immediate fields in SPARC instructions). 299 // Return 0 if the instruction has no IMMED field. 300 // 301 virtual uint64_t maxImmedConstant(MachineOpCode Opcode, 302 bool &isSignExtended) const { 303 isSignExtended = get(Opcode).immedIsSignExtended; 304 return get(Opcode).maxImmedConst; 305 } 306}; 307 308} // End llvm namespace 309 310#endif 311