MachineSink.cpp revision d13db2c59cc94162d6cf0a04187d408bfef6d4a7
1//===-- MachineSink.cpp - Sinking for machine instructions ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass moves instructions into successor blocks when possible, so that 11// they aren't executed on paths where their results aren't needed. 12// 13// This pass is not intended to be a replacement or a complete alternative 14// for an LLVM-IR-level sinking pass. It is only designed to sink simple 15// constructs that are not exposed before lowering and instruction selection. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "machine-sink" 20#include "llvm/CodeGen/Passes.h" 21#include "llvm/CodeGen/MachineRegisterInfo.h" 22#include "llvm/CodeGen/MachineDominators.h" 23#include "llvm/CodeGen/MachineLoopInfo.h" 24#include "llvm/Analysis/AliasAnalysis.h" 25#include "llvm/Target/TargetRegisterInfo.h" 26#include "llvm/Target/TargetInstrInfo.h" 27#include "llvm/Target/TargetMachine.h" 28#include "llvm/ADT/Statistic.h" 29#include "llvm/Support/Debug.h" 30#include "llvm/Support/raw_ostream.h" 31using namespace llvm; 32 33STATISTIC(NumSunk, "Number of machine instructions sunk"); 34 35namespace { 36 class MachineSinking : public MachineFunctionPass { 37 const TargetInstrInfo *TII; 38 const TargetRegisterInfo *TRI; 39 MachineRegisterInfo *RegInfo; // Machine register information 40 MachineDominatorTree *DT; // Machine dominator tree 41 MachineLoopInfo *LI; 42 AliasAnalysis *AA; 43 BitVector AllocatableSet; // Which physregs are allocatable? 44 45 public: 46 static char ID; // Pass identification 47 MachineSinking() : MachineFunctionPass(&ID) {} 48 49 virtual bool runOnMachineFunction(MachineFunction &MF); 50 51 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 52 AU.setPreservesCFG(); 53 MachineFunctionPass::getAnalysisUsage(AU); 54 AU.addRequired<AliasAnalysis>(); 55 AU.addRequired<MachineDominatorTree>(); 56 AU.addRequired<MachineLoopInfo>(); 57 AU.addPreserved<MachineDominatorTree>(); 58 AU.addPreserved<MachineLoopInfo>(); 59 } 60 private: 61 bool ProcessBlock(MachineBasicBlock &MBB); 62 bool SinkInstruction(MachineInstr *MI, bool &SawStore); 63 bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB) const; 64 }; 65} // end anonymous namespace 66 67char MachineSinking::ID = 0; 68INITIALIZE_PASS(MachineSinking, "machine-sink", 69 "Machine code sinking", false, false); 70 71FunctionPass *llvm::createMachineSinkingPass() { return new MachineSinking(); } 72 73/// AllUsesDominatedByBlock - Return true if all uses of the specified register 74/// occur in blocks dominated by the specified block. 75bool MachineSinking::AllUsesDominatedByBlock(unsigned Reg, 76 MachineBasicBlock *MBB) const { 77 assert(TargetRegisterInfo::isVirtualRegister(Reg) && 78 "Only makes sense for vregs"); 79 // Ignoring debug uses is necessary so debug info doesn't affect the code. 80 // This may leave a referencing dbg_value in the original block, before 81 // the definition of the vreg. Dwarf generator handles this although the 82 // user might not get the right info at runtime. 83 for (MachineRegisterInfo::use_nodbg_iterator 84 I = RegInfo->use_nodbg_begin(Reg), E = RegInfo->use_nodbg_end(); 85 I != E; ++I) { 86 // Determine the block of the use. 87 MachineInstr *UseInst = &*I; 88 MachineBasicBlock *UseBlock = UseInst->getParent(); 89 90 if (UseInst->isPHI()) { 91 // PHI nodes use the operand in the predecessor block, not the block with 92 // the PHI. 93 UseBlock = UseInst->getOperand(I.getOperandNo()+1).getMBB(); 94 } 95 96 // Check that it dominates. 97 if (!DT->dominates(MBB, UseBlock)) 98 return false; 99 } 100 101 return true; 102} 103 104bool MachineSinking::runOnMachineFunction(MachineFunction &MF) { 105 DEBUG(dbgs() << "******** Machine Sinking ********\n"); 106 107 const TargetMachine &TM = MF.getTarget(); 108 TII = TM.getInstrInfo(); 109 TRI = TM.getRegisterInfo(); 110 RegInfo = &MF.getRegInfo(); 111 DT = &getAnalysis<MachineDominatorTree>(); 112 LI = &getAnalysis<MachineLoopInfo>(); 113 AA = &getAnalysis<AliasAnalysis>(); 114 AllocatableSet = TRI->getAllocatableSet(MF); 115 116 bool EverMadeChange = false; 117 118 while (1) { 119 bool MadeChange = false; 120 121 // Process all basic blocks. 122 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); 123 I != E; ++I) 124 MadeChange |= ProcessBlock(*I); 125 126 // If this iteration over the code changed anything, keep iterating. 127 if (!MadeChange) break; 128 EverMadeChange = true; 129 } 130 return EverMadeChange; 131} 132 133bool MachineSinking::ProcessBlock(MachineBasicBlock &MBB) { 134 // Can't sink anything out of a block that has less than two successors. 135 if (MBB.succ_size() <= 1 || MBB.empty()) return false; 136 137 // Don't bother sinking code out of unreachable blocks. In addition to being 138 // unprofitable, it can also lead to infinite looping, because in an 139 // unreachable loop there may be nowhere to stop. 140 if (!DT->isReachableFromEntry(&MBB)) return false; 141 142 bool MadeChange = false; 143 144 // Walk the basic block bottom-up. Remember if we saw a store. 145 MachineBasicBlock::iterator I = MBB.end(); 146 --I; 147 bool ProcessedBegin, SawStore = false; 148 do { 149 MachineInstr *MI = I; // The instruction to sink. 150 151 // Predecrement I (if it's not begin) so that it isn't invalidated by 152 // sinking. 153 ProcessedBegin = I == MBB.begin(); 154 if (!ProcessedBegin) 155 --I; 156 157 if (MI->isDebugValue()) 158 continue; 159 160 if (SinkInstruction(MI, SawStore)) 161 ++NumSunk, MadeChange = true; 162 163 // If we just processed the first instruction in the block, we're done. 164 } while (!ProcessedBegin); 165 166 return MadeChange; 167} 168 169/// SinkInstruction - Determine whether it is safe to sink the specified machine 170/// instruction out of its current block into a successor. 171bool MachineSinking::SinkInstruction(MachineInstr *MI, bool &SawStore) { 172 // Check if it's safe to move the instruction. 173 if (!MI->isSafeToMove(TII, AA, SawStore)) 174 return false; 175 176 // FIXME: This should include support for sinking instructions within the 177 // block they are currently in to shorten the live ranges. We often get 178 // instructions sunk into the top of a large block, but it would be better to 179 // also sink them down before their first use in the block. This xform has to 180 // be careful not to *increase* register pressure though, e.g. sinking 181 // "x = y + z" down if it kills y and z would increase the live ranges of y 182 // and z and only shrink the live range of x. 183 184 // Loop over all the operands of the specified instruction. If there is 185 // anything we can't handle, bail out. 186 MachineBasicBlock *ParentBlock = MI->getParent(); 187 188 // SuccToSinkTo - This is the successor to sink this instruction to, once we 189 // decide. 190 MachineBasicBlock *SuccToSinkTo = 0; 191 192 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 193 const MachineOperand &MO = MI->getOperand(i); 194 if (!MO.isReg()) continue; // Ignore non-register operands. 195 196 unsigned Reg = MO.getReg(); 197 if (Reg == 0) continue; 198 199 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 200 if (MO.isUse()) { 201 // If the physreg has no defs anywhere, it's just an ambient register 202 // and we can freely move its uses. Alternatively, if it's allocatable, 203 // it could get allocated to something with a def during allocation. 204 if (!RegInfo->def_empty(Reg)) 205 return false; 206 207 if (AllocatableSet.test(Reg)) 208 return false; 209 210 // Check for a def among the register's aliases too. 211 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { 212 unsigned AliasReg = *Alias; 213 if (!RegInfo->def_empty(AliasReg)) 214 return false; 215 216 if (AllocatableSet.test(AliasReg)) 217 return false; 218 } 219 } else if (!MO.isDead()) { 220 // A def that isn't dead. We can't move it. 221 return false; 222 } 223 } else { 224 // Virtual register uses are always safe to sink. 225 if (MO.isUse()) continue; 226 227 // If it's not safe to move defs of the register class, then abort. 228 if (!TII->isSafeToMoveRegClassDefs(RegInfo->getRegClass(Reg))) 229 return false; 230 231 // FIXME: This picks a successor to sink into based on having one 232 // successor that dominates all the uses. However, there are cases where 233 // sinking can happen but where the sink point isn't a successor. For 234 // example: 235 // 236 // x = computation 237 // if () {} else {} 238 // use x 239 // 240 // the instruction could be sunk over the whole diamond for the 241 // if/then/else (or loop, etc), allowing it to be sunk into other blocks 242 // after that. 243 244 // Virtual register defs can only be sunk if all their uses are in blocks 245 // dominated by one of the successors. 246 if (SuccToSinkTo) { 247 // If a previous operand picked a block to sink to, then this operand 248 // must be sinkable to the same block. 249 if (!AllUsesDominatedByBlock(Reg, SuccToSinkTo)) 250 return false; 251 252 continue; 253 } 254 255 // Otherwise, we should look at all the successors and decide which one 256 // we should sink to. 257 for (MachineBasicBlock::succ_iterator SI = ParentBlock->succ_begin(), 258 E = ParentBlock->succ_end(); SI != E; ++SI) { 259 if (AllUsesDominatedByBlock(Reg, *SI)) { 260 SuccToSinkTo = *SI; 261 break; 262 } 263 } 264 265 // If we couldn't find a block to sink to, ignore this instruction. 266 if (SuccToSinkTo == 0) 267 return false; 268 } 269 } 270 271 // If there are no outputs, it must have side-effects. 272 if (SuccToSinkTo == 0) 273 return false; 274 275 // It's not safe to sink instructions to EH landing pad. Control flow into 276 // landing pad is implicitly defined. 277 if (SuccToSinkTo->isLandingPad()) 278 return false; 279 280 // It is not possible to sink an instruction into its own block. This can 281 // happen with loops. 282 if (MI->getParent() == SuccToSinkTo) 283 return false; 284 285 // If the instruction to move defines a dead physical register which is live 286 // when leaving the basic block, don't move it because it could turn into a 287 // "zombie" define of that preg. E.g., EFLAGS. (<rdar://problem/8030636>) 288 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) { 289 const MachineOperand &MO = MI->getOperand(I); 290 if (!MO.isReg()) continue; 291 unsigned Reg = MO.getReg(); 292 if (Reg == 0 || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue; 293 if (SuccToSinkTo->isLiveIn(Reg)) 294 return false; 295 } 296 297 DEBUG(dbgs() << "Sink instr " << *MI << "\tinto block " << *SuccToSinkTo); 298 299 // If the block has multiple predecessors, this would introduce computation on 300 // a path that it doesn't already exist. We could split the critical edge, 301 // but for now we just punt. 302 // FIXME: Split critical edges if not backedges. 303 if (SuccToSinkTo->pred_size() > 1) { 304 // We cannot sink a load across a critical edge - there may be stores in 305 // other code paths. 306 bool store = true; 307 if (!MI->isSafeToMove(TII, AA, store)) { 308 DEBUG(dbgs() << " *** PUNTING: Wont sink load along critical edge.\n"); 309 return false; 310 } 311 312 // We don't want to sink across a critical edge if we don't dominate the 313 // successor. We could be introducing calculations to new code paths. 314 if (!DT->dominates(ParentBlock, SuccToSinkTo)) { 315 DEBUG(dbgs() << " *** PUNTING: Critical edge found\n"); 316 return false; 317 } 318 319 // Don't sink instructions into a loop. 320 if (LI->isLoopHeader(SuccToSinkTo)) { 321 DEBUG(dbgs() << " *** PUNTING: Loop header found\n"); 322 return false; 323 } 324 325 // Otherwise we are OK with sinking along a critical edge. 326 DEBUG(dbgs() << "Sinking along critical edge.\n"); 327 } 328 329 // Determine where to insert into. Skip phi nodes. 330 MachineBasicBlock::iterator InsertPos = SuccToSinkTo->begin(); 331 while (InsertPos != SuccToSinkTo->end() && InsertPos->isPHI()) 332 ++InsertPos; 333 334 // Move the instruction. 335 SuccToSinkTo->splice(InsertPos, ParentBlock, MI, 336 ++MachineBasicBlock::iterator(MI)); 337 338 // Conservatively, clear any kill flags, since it's possible that they are no 339 // longer correct. 340 MI->clearKillInfo(); 341 342 return true; 343} 344