RegisterScavenging.cpp revision c40f6130344c53d5f0833838eddca1f94670ea1d
196fa612373e258120d351ed14361f964ad22f99dEvan Cheng//===-- RegisterScavenging.cpp - Machine register scavenging --------------===// 296fa612373e258120d351ed14361f964ad22f99dEvan Cheng// 396fa612373e258120d351ed14361f964ad22f99dEvan Cheng// The LLVM Compiler Infrastructure 496fa612373e258120d351ed14361f964ad22f99dEvan Cheng// 54ee451de366474b9c228b4e5fa573795a715216dChris Lattner// This file is distributed under the University of Illinois Open Source 64ee451de366474b9c228b4e5fa573795a715216dChris Lattner// License. See LICENSE.TXT for details. 796fa612373e258120d351ed14361f964ad22f99dEvan Cheng// 896fa612373e258120d351ed14361f964ad22f99dEvan Cheng//===----------------------------------------------------------------------===// 996fa612373e258120d351ed14361f964ad22f99dEvan Cheng// 1096fa612373e258120d351ed14361f964ad22f99dEvan Cheng// This file implements the machine register scavenger. It can provide 11ed1fcd8987a7d39ca69bfa3cbf14b270738f029cBill Wendling// information, such as unused registers, at any point in a machine basic block. 12ed1fcd8987a7d39ca69bfa3cbf14b270738f029cBill Wendling// It also provides a mechanism to make registers available by evicting them to 13ed1fcd8987a7d39ca69bfa3cbf14b270738f029cBill Wendling// spill slots. 1496fa612373e258120d351ed14361f964ad22f99dEvan Cheng// 1596fa612373e258120d351ed14361f964ad22f99dEvan Cheng//===----------------------------------------------------------------------===// 1696fa612373e258120d351ed14361f964ad22f99dEvan Cheng 1796fa612373e258120d351ed14361f964ad22f99dEvan Cheng#define DEBUG_TYPE "reg-scavenging" 1896fa612373e258120d351ed14361f964ad22f99dEvan Cheng#include "llvm/CodeGen/RegisterScavenging.h" 19e0161ea1050fd4107f3307b1e25b3aac02c2ba16John Mosby#include "llvm/CodeGen/MachineFrameInfo.h" 2096fa612373e258120d351ed14361f964ad22f99dEvan Cheng#include "llvm/CodeGen/MachineFunction.h" 2196fa612373e258120d351ed14361f964ad22f99dEvan Cheng#include "llvm/CodeGen/MachineBasicBlock.h" 2296fa612373e258120d351ed14361f964ad22f99dEvan Cheng#include "llvm/CodeGen/MachineInstr.h" 231dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng#include "llvm/CodeGen/MachineRegisterInfo.h" 247d696d80409aad20bb5da0fc4eccab941dd371d4Torok Edwin#include "llvm/Support/ErrorHandling.h" 256f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman#include "llvm/Target/TargetRegisterInfo.h" 2696fa612373e258120d351ed14361f964ad22f99dEvan Cheng#include "llvm/Target/TargetInstrInfo.h" 2796fa612373e258120d351ed14361f964ad22f99dEvan Cheng#include "llvm/Target/TargetMachine.h" 281dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng#include "llvm/ADT/SmallPtrSet.h" 29d68a07650cdb2e18f18f362ba533459aa10e01b6Dan Gohman#include "llvm/ADT/SmallVector.h" 30ed570dedad945e1fe9a4bfeaa47276d875f1feedEvan Cheng#include "llvm/ADT/STLExtras.h" 3196fa612373e258120d351ed14361f964ad22f99dEvan Chengusing namespace llvm; 3296fa612373e258120d351ed14361f964ad22f99dEvan Cheng 33ed1fcd8987a7d39ca69bfa3cbf14b270738f029cBill Wendling/// RedefinesSuperRegPart - Return true if the specified register is redefining 34ed1fcd8987a7d39ca69bfa3cbf14b270738f029cBill Wendling/// part of a super-register. 35ed1fcd8987a7d39ca69bfa3cbf14b270738f029cBill Wendlingstatic bool RedefinesSuperRegPart(const MachineInstr *MI, unsigned SubReg, 36ed1fcd8987a7d39ca69bfa3cbf14b270738f029cBill Wendling const TargetRegisterInfo *TRI) { 37d68f47c6fd744e051f7f2d97b6366d40bf27c438Evan Cheng bool SeenSuperUse = false; 38d68f47c6fd744e051f7f2d97b6366d40bf27c438Evan Cheng bool SeenSuperDef = false; 39ed1fcd8987a7d39ca69bfa3cbf14b270738f029cBill Wendling for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 40ed1fcd8987a7d39ca69bfa3cbf14b270738f029cBill Wendling const MachineOperand &MO = MI->getOperand(i); 414784f1fc73abf6005b7b7262d395af71b57b1255Evan Cheng if (!MO.isReg() || MO.isUndef()) 42ed1fcd8987a7d39ca69bfa3cbf14b270738f029cBill Wendling continue; 4343e2a035309f4e353a8bd5547d10125414597e74Duncan Sands if (TRI->isSuperRegister(SubReg, MO.getReg())) { 44d68f47c6fd744e051f7f2d97b6366d40bf27c438Evan Cheng if (MO.isUse()) 45d68f47c6fd744e051f7f2d97b6366d40bf27c438Evan Cheng SeenSuperUse = true; 46d68f47c6fd744e051f7f2d97b6366d40bf27c438Evan Cheng else if (MO.isImplicit()) 47d68f47c6fd744e051f7f2d97b6366d40bf27c438Evan Cheng SeenSuperDef = true; 4843e2a035309f4e353a8bd5547d10125414597e74Duncan Sands } 49ed1fcd8987a7d39ca69bfa3cbf14b270738f029cBill Wendling } 50ed1fcd8987a7d39ca69bfa3cbf14b270738f029cBill Wendling 51d68f47c6fd744e051f7f2d97b6366d40bf27c438Evan Cheng return SeenSuperDef && SeenSuperUse; 52ed1fcd8987a7d39ca69bfa3cbf14b270738f029cBill Wendling} 53ed1fcd8987a7d39ca69bfa3cbf14b270738f029cBill Wendling 54ed1fcd8987a7d39ca69bfa3cbf14b270738f029cBill Wendlingstatic bool RedefinesSuperRegPart(const MachineInstr *MI, 55ed1fcd8987a7d39ca69bfa3cbf14b270738f029cBill Wendling const MachineOperand &MO, 56ed1fcd8987a7d39ca69bfa3cbf14b270738f029cBill Wendling const TargetRegisterInfo *TRI) { 57d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman assert(MO.isReg() && MO.isDef() && "Not a register def!"); 58ed1fcd8987a7d39ca69bfa3cbf14b270738f029cBill Wendling return RedefinesSuperRegPart(MI, MO.getReg(), TRI); 59ed1fcd8987a7d39ca69bfa3cbf14b270738f029cBill Wendling} 60ed1fcd8987a7d39ca69bfa3cbf14b270738f029cBill Wendling 610e6a4efdd4f97137fb0a58d7bb3de07562185530Jakob Stoklund Olesenbool RegScavenger::isSuperRegUsed(unsigned Reg) const { 620e6a4efdd4f97137fb0a58d7bb3de07562185530Jakob Stoklund Olesen for (const unsigned *SuperRegs = TRI->getSuperRegisters(Reg); 630e6a4efdd4f97137fb0a58d7bb3de07562185530Jakob Stoklund Olesen unsigned SuperReg = *SuperRegs; ++SuperRegs) 640e6a4efdd4f97137fb0a58d7bb3de07562185530Jakob Stoklund Olesen if (isUsed(SuperReg)) 650e6a4efdd4f97137fb0a58d7bb3de07562185530Jakob Stoklund Olesen return true; 660e6a4efdd4f97137fb0a58d7bb3de07562185530Jakob Stoklund Olesen return false; 670e6a4efdd4f97137fb0a58d7bb3de07562185530Jakob Stoklund Olesen} 680e6a4efdd4f97137fb0a58d7bb3de07562185530Jakob Stoklund Olesen 69a0a570cec647b860a724f4f70a191bc83cdcc947Bill Wendling/// setUsed - Set the register and its sub-registers as being used. 70459a7c6b6ad9c4fcb9f119aa6eaaf2769b00d9b1Evan Chengvoid RegScavenger::setUsed(unsigned Reg) { 71a0a570cec647b860a724f4f70a191bc83cdcc947Bill Wendling RegsAvailable.reset(Reg); 72a0a570cec647b860a724f4f70a191bc83cdcc947Bill Wendling 736130f66eaae89f8878590796977678afa8448926Evan Cheng for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); 74459a7c6b6ad9c4fcb9f119aa6eaaf2769b00d9b1Evan Cheng unsigned SubReg = *SubRegs; ++SubRegs) 75a0a570cec647b860a724f4f70a191bc83cdcc947Bill Wendling RegsAvailable.reset(SubReg); 76a0a570cec647b860a724f4f70a191bc83cdcc947Bill Wendling} 77a0a570cec647b860a724f4f70a191bc83cdcc947Bill Wendling 78a0a570cec647b860a724f4f70a191bc83cdcc947Bill Wendling/// setUnused - Set the register and its sub-registers as being unused. 79ed1fcd8987a7d39ca69bfa3cbf14b270738f029cBill Wendlingvoid RegScavenger::setUnused(unsigned Reg, const MachineInstr *MI) { 80a0a570cec647b860a724f4f70a191bc83cdcc947Bill Wendling RegsAvailable.set(Reg); 81a0a570cec647b860a724f4f70a191bc83cdcc947Bill Wendling 826130f66eaae89f8878590796977678afa8448926Evan Cheng for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); 83a0a570cec647b860a724f4f70a191bc83cdcc947Bill Wendling unsigned SubReg = *SubRegs; ++SubRegs) 84459a7c6b6ad9c4fcb9f119aa6eaaf2769b00d9b1Evan Cheng if (!RedefinesSuperRegPart(MI, Reg, TRI)) 85ed1fcd8987a7d39ca69bfa3cbf14b270738f029cBill Wendling RegsAvailable.set(SubReg); 86a0a570cec647b860a724f4f70a191bc83cdcc947Bill Wendling} 87a0a570cec647b860a724f4f70a191bc83cdcc947Bill Wendling 88e0161ea1050fd4107f3307b1e25b3aac02c2ba16John Mosbyvoid RegScavenger::initRegState() { 89e0161ea1050fd4107f3307b1e25b3aac02c2ba16John Mosby ScavengedReg = 0; 90e0161ea1050fd4107f3307b1e25b3aac02c2ba16John Mosby ScavengedRC = NULL; 91e0161ea1050fd4107f3307b1e25b3aac02c2ba16John Mosby ScavengeRestore = NULL; 92e0161ea1050fd4107f3307b1e25b3aac02c2ba16John Mosby CurrDist = 0; 93e0161ea1050fd4107f3307b1e25b3aac02c2ba16John Mosby DistanceMap.clear(); 94e0161ea1050fd4107f3307b1e25b3aac02c2ba16John Mosby 95e0161ea1050fd4107f3307b1e25b3aac02c2ba16John Mosby // All registers started out unused. 96e0161ea1050fd4107f3307b1e25b3aac02c2ba16John Mosby RegsAvailable.set(); 97e0161ea1050fd4107f3307b1e25b3aac02c2ba16John Mosby 98e0161ea1050fd4107f3307b1e25b3aac02c2ba16John Mosby // Reserved registers are always used. 99e0161ea1050fd4107f3307b1e25b3aac02c2ba16John Mosby RegsAvailable ^= ReservedRegs; 100e0161ea1050fd4107f3307b1e25b3aac02c2ba16John Mosby 101e0161ea1050fd4107f3307b1e25b3aac02c2ba16John Mosby // Live-in registers are in use. 102c40f6130344c53d5f0833838eddca1f94670ea1dEvan Cheng if (!MBB || MBB->livein_empty()) 103c40f6130344c53d5f0833838eddca1f94670ea1dEvan Cheng return; 104c40f6130344c53d5f0833838eddca1f94670ea1dEvan Cheng for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(), 105c40f6130344c53d5f0833838eddca1f94670ea1dEvan Cheng E = MBB->livein_end(); I != E; ++I) 106c40f6130344c53d5f0833838eddca1f94670ea1dEvan Cheng setUsed(*I); 107e0161ea1050fd4107f3307b1e25b3aac02c2ba16John Mosby} 108e0161ea1050fd4107f3307b1e25b3aac02c2ba16John Mosby 109a3756ee7fe384210eddcfd66e2934439960b13a1Evan Chengvoid RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) { 1104542611bb9793e8376d7d5f33b4a1e2d11712894Dan Gohman MachineFunction &MF = *mbb->getParent(); 11196fa612373e258120d351ed14361f964ad22f99dEvan Cheng const TargetMachine &TM = MF.getTarget(); 112b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng TII = TM.getInstrInfo(); 1136130f66eaae89f8878590796977678afa8448926Evan Cheng TRI = TM.getRegisterInfo(); 1141dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng MRI = &MF.getRegInfo(); 11596fa612373e258120d351ed14361f964ad22f99dEvan Cheng 1166130f66eaae89f8878590796977678afa8448926Evan Cheng assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) && 117898218cc5edecea1275ee266b2cd13313ea6b67bEvan Cheng "Target changed?"); 118898218cc5edecea1275ee266b2cd13313ea6b67bEvan Cheng 119e0161ea1050fd4107f3307b1e25b3aac02c2ba16John Mosby // Self-initialize. 120898218cc5edecea1275ee266b2cd13313ea6b67bEvan Cheng if (!MBB) { 1216130f66eaae89f8878590796977678afa8448926Evan Cheng NumPhysRegs = TRI->getNumRegs(); 122c6b9ef80a890fcf75f18cabc3fe2d5f9ef2faaf5Dale Johannesen RegsAvailable.resize(NumPhysRegs); 123898218cc5edecea1275ee266b2cd13313ea6b67bEvan Cheng 124a3756ee7fe384210eddcfd66e2934439960b13a1Evan Cheng // Create reserved registers bitvector. 1256130f66eaae89f8878590796977678afa8448926Evan Cheng ReservedRegs = TRI->getReservedRegs(MF); 126a3756ee7fe384210eddcfd66e2934439960b13a1Evan Cheng 127898218cc5edecea1275ee266b2cd13313ea6b67bEvan Cheng // Create callee-saved registers bitvector. 128898218cc5edecea1275ee266b2cd13313ea6b67bEvan Cheng CalleeSavedRegs.resize(NumPhysRegs); 1296130f66eaae89f8878590796977678afa8448926Evan Cheng const unsigned *CSRegs = TRI->getCalleeSavedRegs(); 130c40f6130344c53d5f0833838eddca1f94670ea1dEvan Cheng if (CSRegs != NULL) 131c40f6130344c53d5f0833838eddca1f94670ea1dEvan Cheng for (unsigned i = 0; CSRegs[i]; ++i) 132c40f6130344c53d5f0833838eddca1f94670ea1dEvan Cheng CalleeSavedRegs.set(CSRegs[i]); 133898218cc5edecea1275ee266b2cd13313ea6b67bEvan Cheng } 134898218cc5edecea1275ee266b2cd13313ea6b67bEvan Cheng 135c40f6130344c53d5f0833838eddca1f94670ea1dEvan Cheng // RS used within emit{Pro,Epi}logue() 136e0161ea1050fd4107f3307b1e25b3aac02c2ba16John Mosby if (mbb != MBB) { 137e0161ea1050fd4107f3307b1e25b3aac02c2ba16John Mosby MBB = mbb; 138e0161ea1050fd4107f3307b1e25b3aac02c2ba16John Mosby initRegState(); 139e0161ea1050fd4107f3307b1e25b3aac02c2ba16John Mosby } 140a3756ee7fe384210eddcfd66e2934439960b13a1Evan Cheng 141a3756ee7fe384210eddcfd66e2934439960b13a1Evan Cheng Tracking = false; 14296fa612373e258120d351ed14361f964ad22f99dEvan Cheng} 14396fa612373e258120d351ed14361f964ad22f99dEvan Cheng 144b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Chengvoid RegScavenger::restoreScavengedReg() { 145f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson TII->loadRegFromStackSlot(*MBB, MBBI, ScavengedReg, 1461dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng ScavengingFrameIndex, ScavengedRC); 147b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng MachineBasicBlock::iterator II = prior(MBBI); 1486130f66eaae89f8878590796977678afa8448926Evan Cheng TRI->eliminateFrameIndex(II, 0, this); 149b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng setUsed(ScavengedReg); 150b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng ScavengedReg = 0; 151b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng ScavengedRC = NULL; 152b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng} 153b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng 1542755896fd048d189bedc5e99e776b3eca010dd4eDevang Patel#ifndef NDEBUG 1551dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng/// isLiveInButUnusedBefore - Return true if register is livein the MBB not 1561dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng/// not used before it reaches the MI that defines register. 1571dc7869025d91906e8305e921ddb82dac780d70eEvan Chengstatic bool isLiveInButUnusedBefore(unsigned Reg, MachineInstr *MI, 1581dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng MachineBasicBlock *MBB, 1591dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng const TargetRegisterInfo *TRI, 1601dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng MachineRegisterInfo* MRI) { 1611dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng // First check if register is livein. 1621dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng bool isLiveIn = false; 1631dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(), 1641dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng E = MBB->livein_end(); I != E; ++I) 1651dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng if (Reg == *I || TRI->isSuperRegister(Reg, *I)) { 1661dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng isLiveIn = true; 1671dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng break; 1681dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng } 1691dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng if (!isLiveIn) 1701dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng return false; 1711dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng 1721dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng // Is there any use of it before the specified MI? 1731dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng SmallPtrSet<MachineInstr*, 4> UsesInMBB; 1741dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg), 1751dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng UE = MRI->use_end(); UI != UE; ++UI) { 1761e0c1588b1b030a1402cf1865b63faf060e44a39Evan Cheng MachineOperand &UseMO = UI.getOperand(); 1771e0c1588b1b030a1402cf1865b63faf060e44a39Evan Cheng if (UseMO.isReg() && UseMO.isUndef()) 1781e0c1588b1b030a1402cf1865b63faf060e44a39Evan Cheng continue; 1791dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng MachineInstr *UseMI = &*UI; 1801dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng if (UseMI->getParent() == MBB) 1811dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng UsesInMBB.insert(UseMI); 1821dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng } 1831dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng if (UsesInMBB.empty()) 1841dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng return true; 1851dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng 1861dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng for (MachineBasicBlock::iterator I = MBB->begin(), E = MI; I != E; ++I) 1871dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng if (UsesInMBB.count(&*I)) 1881dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng return false; 1891dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng return true; 1901dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng} 1912755896fd048d189bedc5e99e776b3eca010dd4eDevang Patel#endif 1921dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng 19396fa612373e258120d351ed14361f964ad22f99dEvan Chengvoid RegScavenger::forward() { 194ed570dedad945e1fe9a4bfeaa47276d875f1feedEvan Cheng // Move ptr forward. 195898218cc5edecea1275ee266b2cd13313ea6b67bEvan Cheng if (!Tracking) { 196898218cc5edecea1275ee266b2cd13313ea6b67bEvan Cheng MBBI = MBB->begin(); 197898218cc5edecea1275ee266b2cd13313ea6b67bEvan Cheng Tracking = true; 198898218cc5edecea1275ee266b2cd13313ea6b67bEvan Cheng } else { 199898218cc5edecea1275ee266b2cd13313ea6b67bEvan Cheng assert(MBBI != MBB->end() && "Already at the end of the basic block!"); 200ed570dedad945e1fe9a4bfeaa47276d875f1feedEvan Cheng MBBI = next(MBBI); 201898218cc5edecea1275ee266b2cd13313ea6b67bEvan Cheng } 202ed570dedad945e1fe9a4bfeaa47276d875f1feedEvan Cheng 20396fa612373e258120d351ed14361f964ad22f99dEvan Cheng MachineInstr *MI = MBBI; 204d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng DistanceMap.insert(std::make_pair(MI, CurrDist++)); 205b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng 206d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng if (MI == ScavengeRestore) { 207d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng ScavengedReg = 0; 208d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng ScavengedRC = NULL; 209d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng ScavengeRestore = NULL; 210d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng } 211b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng 2129c64bf3905ea338719800008c03d95a17cb26689Evan Cheng // Separate register operands into 3 classes: uses, defs, earlyclobbers. 21363a431c6704e711713b0258bd987cfb257767cf4Evan Cheng SmallVector<std::pair<const MachineOperand*,unsigned>, 4> UseMOs; 21463a431c6704e711713b0258bd987cfb257767cf4Evan Cheng SmallVector<std::pair<const MachineOperand*,unsigned>, 4> DefMOs; 21563a431c6704e711713b0258bd987cfb257767cf4Evan Cheng SmallVector<std::pair<const MachineOperand*,unsigned>, 4> EarlyClobberMOs; 21696fa612373e258120d351ed14361f964ad22f99dEvan Cheng for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 21796fa612373e258120d351ed14361f964ad22f99dEvan Cheng const MachineOperand &MO = MI->getOperand(i); 2184784f1fc73abf6005b7b7262d395af71b57b1255Evan Cheng if (!MO.isReg() || MO.getReg() == 0 || MO.isUndef()) 21996fa612373e258120d351ed14361f964ad22f99dEvan Cheng continue; 2209c64bf3905ea338719800008c03d95a17cb26689Evan Cheng if (MO.isUse()) 22163a431c6704e711713b0258bd987cfb257767cf4Evan Cheng UseMOs.push_back(std::make_pair(&MO,i)); 2229c64bf3905ea338719800008c03d95a17cb26689Evan Cheng else if (MO.isEarlyClobber()) 22363a431c6704e711713b0258bd987cfb257767cf4Evan Cheng EarlyClobberMOs.push_back(std::make_pair(&MO,i)); 224c40f6130344c53d5f0833838eddca1f94670ea1dEvan Cheng else { 225c40f6130344c53d5f0833838eddca1f94670ea1dEvan Cheng assert(MO.isDef()); 22663a431c6704e711713b0258bd987cfb257767cf4Evan Cheng DefMOs.push_back(std::make_pair(&MO,i)); 227c40f6130344c53d5f0833838eddca1f94670ea1dEvan Cheng } 2289c64bf3905ea338719800008c03d95a17cb26689Evan Cheng } 229a0a570cec647b860a724f4f70a191bc83cdcc947Bill Wendling 2309c64bf3905ea338719800008c03d95a17cb26689Evan Cheng // Process uses first. 2314a274e573dbbd4a6085de0d3c738c801b9d000c5Evan Cheng BitVector KillRegs(NumPhysRegs); 2329c64bf3905ea338719800008c03d95a17cb26689Evan Cheng for (unsigned i = 0, e = UseMOs.size(); i != e; ++i) { 23363a431c6704e711713b0258bd987cfb257767cf4Evan Cheng const MachineOperand MO = *UseMOs[i].first; 234323e7d32ab256ba8847ba4ed176b5cd7d0bec3adJakob Stoklund Olesen unsigned Idx = UseMOs[i].second; 23596fa612373e258120d351ed14361f964ad22f99dEvan Cheng unsigned Reg = MO.getReg(); 236a0a570cec647b860a724f4f70a191bc83cdcc947Bill Wendling 237c40f6130344c53d5f0833838eddca1f94670ea1dEvan Cheng assert(isUsed(Reg) && "Using an undefined register!"); 238a0a570cec647b860a724f4f70a191bc83cdcc947Bill Wendling 239323e7d32ab256ba8847ba4ed176b5cd7d0bec3adJakob Stoklund Olesen // Two-address operands implicitly kill. 240323e7d32ab256ba8847ba4ed176b5cd7d0bec3adJakob Stoklund Olesen if ((MO.isKill() || MI->isRegTiedToDefOperand(Idx)) && !isReserved(Reg)) { 2414a274e573dbbd4a6085de0d3c738c801b9d000c5Evan Cheng KillRegs.set(Reg); 242a0a570cec647b860a724f4f70a191bc83cdcc947Bill Wendling 2439c64bf3905ea338719800008c03d95a17cb26689Evan Cheng // Mark sub-registers as used. 2446130f66eaae89f8878590796977678afa8448926Evan Cheng for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); 245a0a570cec647b860a724f4f70a191bc83cdcc947Bill Wendling unsigned SubReg = *SubRegs; ++SubRegs) 2464a274e573dbbd4a6085de0d3c738c801b9d000c5Evan Cheng KillRegs.set(SubReg); 247a0a570cec647b860a724f4f70a191bc83cdcc947Bill Wendling } 24896fa612373e258120d351ed14361f964ad22f99dEvan Cheng } 249a0a570cec647b860a724f4f70a191bc83cdcc947Bill Wendling 25096fa612373e258120d351ed14361f964ad22f99dEvan Cheng // Change states of all registers after all the uses are processed to guard 25196fa612373e258120d351ed14361f964ad22f99dEvan Cheng // against multiple uses. 2524a274e573dbbd4a6085de0d3c738c801b9d000c5Evan Cheng setUnused(KillRegs); 253a0a570cec647b860a724f4f70a191bc83cdcc947Bill Wendling 2549c64bf3905ea338719800008c03d95a17cb26689Evan Cheng // Process early clobber defs then process defs. We can have a early clobber 2559c64bf3905ea338719800008c03d95a17cb26689Evan Cheng // that is dead, it should not conflict with a def that happens one "slot" 2569c64bf3905ea338719800008c03d95a17cb26689Evan Cheng // (see InstrSlots in LiveIntervalAnalysis.h) later. 2579c64bf3905ea338719800008c03d95a17cb26689Evan Cheng unsigned NumECs = EarlyClobberMOs.size(); 2589c64bf3905ea338719800008c03d95a17cb26689Evan Cheng unsigned NumDefs = DefMOs.size(); 259a0a570cec647b860a724f4f70a191bc83cdcc947Bill Wendling 2609c64bf3905ea338719800008c03d95a17cb26689Evan Cheng for (unsigned i = 0, e = NumECs + NumDefs; i != e; ++i) { 2619c64bf3905ea338719800008c03d95a17cb26689Evan Cheng const MachineOperand &MO = (i < NumECs) 26263a431c6704e711713b0258bd987cfb257767cf4Evan Cheng ? *EarlyClobberMOs[i].first : *DefMOs[i-NumECs].first; 2630badfea274f9612780caccbad6e1870f39ed9f40Evan Cheng unsigned Reg = MO.getReg(); 2642578ba26e72e36dde64be0f52a2788480aad3378Evan Cheng if (MO.isUndef()) 2652578ba26e72e36dde64be0f52a2788480aad3378Evan Cheng continue; 266a0a570cec647b860a724f4f70a191bc83cdcc947Bill Wendling 2675de3b7f35131b3c17e0b3c711d47ab3fb2c1e9beEvan Cheng // If it's dead upon def, then it is now free. 2685de3b7f35131b3c17e0b3c711d47ab3fb2c1e9beEvan Cheng if (MO.isDead()) { 269ed1fcd8987a7d39ca69bfa3cbf14b270738f029cBill Wendling setUnused(Reg, MI); 2705de3b7f35131b3c17e0b3c711d47ab3fb2c1e9beEvan Cheng continue; 2715de3b7f35131b3c17e0b3c711d47ab3fb2c1e9beEvan Cheng } 272a0a570cec647b860a724f4f70a191bc83cdcc947Bill Wendling 273d118342b25eb6a3a67792cda9fce9b4c1e45a867Dan Gohman // Skip if this is merely redefining part of a super-register. 274ed1fcd8987a7d39ca69bfa3cbf14b270738f029cBill Wendling if (RedefinesSuperRegPart(MI, MO, TRI)) 275ed1fcd8987a7d39ca69bfa3cbf14b270738f029cBill Wendling continue; 276ed1fcd8987a7d39ca69bfa3cbf14b270738f029cBill Wendling 277f955cbf56f130cdeb4c6c8aaa4a2715d420c1327Jakob Stoklund Olesen assert((isReserved(Reg) || isUnused(Reg) || isSuperRegUsed(Reg) || 2781dc7869025d91906e8305e921ddb82dac780d70eEvan Cheng isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) && 2795db322acefc3089c133b8f3a33fa0a3ce90e2001Evan Cheng "Re-defining a live register!"); 280459a7c6b6ad9c4fcb9f119aa6eaaf2769b00d9b1Evan Cheng setUsed(Reg); 28196fa612373e258120d351ed14361f964ad22f99dEvan Cheng } 28296fa612373e258120d351ed14361f964ad22f99dEvan Cheng} 28396fa612373e258120d351ed14361f964ad22f99dEvan Cheng 28469cb9b78f11d505f4351a269fc90e7b77fcda437Dale Johannesenvoid RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) { 28569cb9b78f11d505f4351a269fc90e7b77fcda437Dale Johannesen if (includeReserved) 286c6b9ef80a890fcf75f18cabc3fe2d5f9ef2faaf5Dale Johannesen used = ~RegsAvailable; 28769cb9b78f11d505f4351a269fc90e7b77fcda437Dale Johannesen else 288c6b9ef80a890fcf75f18cabc3fe2d5f9ef2faaf5Dale Johannesen used = ~RegsAvailable & ~ReservedRegs; 28969cb9b78f11d505f4351a269fc90e7b77fcda437Dale Johannesen} 29069cb9b78f11d505f4351a269fc90e7b77fcda437Dale Johannesen 29196fa612373e258120d351ed14361f964ad22f99dEvan Cheng/// CreateRegClassMask - Set the bits that represent the registers in the 29296fa612373e258120d351ed14361f964ad22f99dEvan Cheng/// TargetRegisterClass. 29396fa612373e258120d351ed14361f964ad22f99dEvan Chengstatic void CreateRegClassMask(const TargetRegisterClass *RC, BitVector &Mask) { 29496fa612373e258120d351ed14361f964ad22f99dEvan Cheng for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I != E; 29596fa612373e258120d351ed14361f964ad22f99dEvan Cheng ++I) 29696fa612373e258120d351ed14361f964ad22f99dEvan Cheng Mask.set(*I); 29796fa612373e258120d351ed14361f964ad22f99dEvan Cheng} 29896fa612373e258120d351ed14361f964ad22f99dEvan Cheng 29996fa612373e258120d351ed14361f964ad22f99dEvan Chengunsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass, 3005196b3680cf8df32b6c763e3d97e963e45150e5aEvan Cheng const BitVector &Candidates) const { 3015196b3680cf8df32b6c763e3d97e963e45150e5aEvan Cheng // Mask off the registers which are not in the TargetRegisterClass. 302c6b9ef80a890fcf75f18cabc3fe2d5f9ef2faaf5Dale Johannesen BitVector RegsAvailableCopy(NumPhysRegs, false); 303c6b9ef80a890fcf75f18cabc3fe2d5f9ef2faaf5Dale Johannesen CreateRegClassMask(RegClass, RegsAvailableCopy); 304c6b9ef80a890fcf75f18cabc3fe2d5f9ef2faaf5Dale Johannesen RegsAvailableCopy &= RegsAvailable; 3055196b3680cf8df32b6c763e3d97e963e45150e5aEvan Cheng 3065196b3680cf8df32b6c763e3d97e963e45150e5aEvan Cheng // Restrict the search to candidates. 307c6b9ef80a890fcf75f18cabc3fe2d5f9ef2faaf5Dale Johannesen RegsAvailableCopy &= Candidates; 3085196b3680cf8df32b6c763e3d97e963e45150e5aEvan Cheng 3095196b3680cf8df32b6c763e3d97e963e45150e5aEvan Cheng // Returns the first unused (bit is set) register, or 0 is none is found. 310c6b9ef80a890fcf75f18cabc3fe2d5f9ef2faaf5Dale Johannesen int Reg = RegsAvailableCopy.find_first(); 3115196b3680cf8df32b6c763e3d97e963e45150e5aEvan Cheng return (Reg == -1) ? 0 : Reg; 3125196b3680cf8df32b6c763e3d97e963e45150e5aEvan Cheng} 3135196b3680cf8df32b6c763e3d97e963e45150e5aEvan Cheng 3145196b3680cf8df32b6c763e3d97e963e45150e5aEvan Chengunsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass, 31596fa612373e258120d351ed14361f964ad22f99dEvan Cheng bool ExCalleeSaved) const { 31696fa612373e258120d351ed14361f964ad22f99dEvan Cheng // Mask off the registers which are not in the TargetRegisterClass. 317c6b9ef80a890fcf75f18cabc3fe2d5f9ef2faaf5Dale Johannesen BitVector RegsAvailableCopy(NumPhysRegs, false); 318c6b9ef80a890fcf75f18cabc3fe2d5f9ef2faaf5Dale Johannesen CreateRegClassMask(RegClass, RegsAvailableCopy); 319c6b9ef80a890fcf75f18cabc3fe2d5f9ef2faaf5Dale Johannesen RegsAvailableCopy &= RegsAvailable; 32096fa612373e258120d351ed14361f964ad22f99dEvan Cheng 32196fa612373e258120d351ed14361f964ad22f99dEvan Cheng // If looking for a non-callee-saved register, mask off all the callee-saved 32296fa612373e258120d351ed14361f964ad22f99dEvan Cheng // registers. 32396fa612373e258120d351ed14361f964ad22f99dEvan Cheng if (ExCalleeSaved) 324c6b9ef80a890fcf75f18cabc3fe2d5f9ef2faaf5Dale Johannesen RegsAvailableCopy &= ~CalleeSavedRegs; 32596fa612373e258120d351ed14361f964ad22f99dEvan Cheng 32696fa612373e258120d351ed14361f964ad22f99dEvan Cheng // Returns the first unused (bit is set) register, or 0 is none is found. 327c6b9ef80a890fcf75f18cabc3fe2d5f9ef2faaf5Dale Johannesen int Reg = RegsAvailableCopy.find_first(); 32896fa612373e258120d351ed14361f964ad22f99dEvan Cheng return (Reg == -1) ? 0 : Reg; 32996fa612373e258120d351ed14361f964ad22f99dEvan Cheng} 330b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng 331d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng/// findFirstUse - Calculate the distance to the first use of the 332b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng/// specified register. 333d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan ChengMachineInstr* 334d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan ChengRegScavenger::findFirstUse(MachineBasicBlock *MBB, 335d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng MachineBasicBlock::iterator I, unsigned Reg, 336d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng unsigned &Dist) { 337d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng MachineInstr *UseMI = 0; 338d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng Dist = ~0U; 339d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(Reg), 340d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng RE = MRI->reg_end(); RI != RE; ++RI) { 341d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng MachineInstr *UDMI = &*RI; 342d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng if (UDMI->getParent() != MBB) 343d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng continue; 344d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UDMI); 345d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng if (DI == DistanceMap.end()) { 346d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng // If it's not in map, it's below current MI, let's initialize the 347d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng // map. 348d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng I = next(I); 349d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng unsigned Dist = CurrDist + 1; 350d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng while (I != MBB->end()) { 351d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng DistanceMap.insert(std::make_pair(I, Dist++)); 352d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng I = next(I); 353d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng } 354d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng } 355d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng DI = DistanceMap.find(UDMI); 356d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng if (DI->second > CurrDist && DI->second < Dist) { 357d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng Dist = DI->second; 358d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng UseMI = UDMI; 359d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng } 360b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng } 361d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng return UseMI; 362b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng} 363b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng 364b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Chengunsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC, 3658e3347332120956538a6d882b02719e34b57f0cdEvan Cheng MachineBasicBlock::iterator I, 3668e3347332120956538a6d882b02719e34b57f0cdEvan Cheng int SPAdj) { 367b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng assert(ScavengingFrameIndex >= 0 && 368b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng "Cannot scavenge a register without an emergency spill slot!"); 369b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng 370b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng // Mask off the registers which are not in the TargetRegisterClass. 371b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng BitVector Candidates(NumPhysRegs, false); 372b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng CreateRegClassMask(RC, Candidates); 373e0161ea1050fd4107f3307b1e25b3aac02c2ba16John Mosby // Do not include reserved registers. 374e0161ea1050fd4107f3307b1e25b3aac02c2ba16John Mosby Candidates ^= ReservedRegs & Candidates; 375b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng 376b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng // Exclude all the registers being used by the instruction. 377b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) { 378b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng MachineOperand &MO = I->getOperand(i); 379d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman if (MO.isReg()) 380b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng Candidates.reset(MO.getReg()); 381b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng } 382b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng 383527c250a9080a5b6cf0053a6215037c3769ff4a0Bill Wendling // Find the register whose use is furthest away. 384b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng unsigned SReg = 0; 385b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng unsigned MaxDist = 0; 386d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng MachineInstr *MaxUseMI = 0; 387b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng int Reg = Candidates.find_first(); 388b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng while (Reg != -1) { 389d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng unsigned Dist; 390d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng MachineInstr *UseMI = findFirstUse(MBB, I, Reg, Dist); 391d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) { 392d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng unsigned AsDist; 393d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng MachineInstr *AsUseMI = findFirstUse(MBB, I, *AS, AsDist); 394d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng if (AsDist < Dist) { 395d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng Dist = AsDist; 396d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng UseMI = AsUseMI; 397d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng } 398d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng } 399b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng if (Dist >= MaxDist) { 400b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng MaxDist = Dist; 401d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng MaxUseMI = UseMI; 402b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng SReg = Reg; 403b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng } 404b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng Reg = Candidates.find_next(Reg); 405b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng } 406b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng 407b36eb9df205aa83cfdfc8ecebc93e1043d6253d9Jakob Stoklund Olesen assert(ScavengedReg == 0 && 408f36892335b4919b9120e48a792e6b3630b9de978Torok Edwin "Scavenger slot is live, unable to scavenge another register!"); 409b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng 410e0161ea1050fd4107f3307b1e25b3aac02c2ba16John Mosby // Avoid infinite regress 411e0161ea1050fd4107f3307b1e25b3aac02c2ba16John Mosby ScavengedReg = SReg; 412e0161ea1050fd4107f3307b1e25b3aac02c2ba16John Mosby 413e0161ea1050fd4107f3307b1e25b3aac02c2ba16John Mosby // Make sure SReg is marked as used. It could be considered available 414e0161ea1050fd4107f3307b1e25b3aac02c2ba16John Mosby // if it is one of the callee saved registers, but hasn't been spilled. 415b36eb9df205aa83cfdfc8ecebc93e1043d6253d9Jakob Stoklund Olesen if (!isUsed(SReg)) { 416b36eb9df205aa83cfdfc8ecebc93e1043d6253d9Jakob Stoklund Olesen MBB->addLiveIn(SReg); 417b36eb9df205aa83cfdfc8ecebc93e1043d6253d9Jakob Stoklund Olesen setUsed(SReg); 418b36eb9df205aa83cfdfc8ecebc93e1043d6253d9Jakob Stoklund Olesen } 419b36eb9df205aa83cfdfc8ecebc93e1043d6253d9Jakob Stoklund Olesen 420d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng // Spill the scavenged register before I. 421f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC); 422b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng MachineBasicBlock::iterator II = prior(I); 4236130f66eaae89f8878590796977678afa8448926Evan Cheng TRI->eliminateFrameIndex(II, SPAdj, this); 424d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng 425d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng // Restore the scavenged register before its use (or first terminator). 426d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng II = MaxUseMI 427d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng ? MachineBasicBlock::iterator(MaxUseMI) : MBB->getFirstTerminator(); 428d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng TII->loadRegFromStackSlot(*MBB, II, SReg, ScavengingFrameIndex, RC); 429d37c13cfd1bf4b08d0b99d93c799a1caa74cf3c6Evan Cheng ScavengeRestore = prior(II); 430c40f6130344c53d5f0833838eddca1f94670ea1dEvan Cheng // Doing this here leads to infinite regress. 431e0161ea1050fd4107f3307b1e25b3aac02c2ba16John Mosby // ScavengedReg = SReg; 432b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng ScavengedRC = RC; 433b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng 434b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng return SReg; 435b74a3e6fda768eb6160559e025f8b65c46db46d9Evan Cheng} 436