LegalizeDAG.cpp revision d4e50bb2e23b8f9ddde629a28dab3bcdaf0633e4
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineConstantPool.h" 16#include "llvm/CodeGen/MachineFunction.h" 17#include "llvm/CodeGen/MachineFrameInfo.h" 18#include "llvm/Target/TargetLowering.h" 19#include "llvm/Target/TargetData.h" 20#include "llvm/Target/TargetOptions.h" 21#include "llvm/Constants.h" 22#include <iostream> 23using namespace llvm; 24 25//===----------------------------------------------------------------------===// 26/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 27/// hacks on it until the target machine can handle it. This involves 28/// eliminating value sizes the machine cannot handle (promoting small sizes to 29/// large sizes or splitting up large values into small values) as well as 30/// eliminating operations the machine cannot handle. 31/// 32/// This code also does a small amount of optimization and recognition of idioms 33/// as part of its processing. For example, if a target does not support a 34/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 35/// will attempt merge setcc and brc instructions into brcc's. 36/// 37namespace { 38class SelectionDAGLegalize { 39 TargetLowering &TLI; 40 SelectionDAG &DAG; 41 42 /// LegalizeAction - This enum indicates what action we should take for each 43 /// value type the can occur in the program. 44 enum LegalizeAction { 45 Legal, // The target natively supports this value type. 46 Promote, // This should be promoted to the next larger type. 47 Expand, // This integer type should be broken into smaller pieces. 48 }; 49 50 /// ValueTypeActions - This is a bitvector that contains two bits for each 51 /// value type, where the two bits correspond to the LegalizeAction enum. 52 /// This can be queried with "getTypeAction(VT)". 53 unsigned ValueTypeActions; 54 55 /// NeedsAnotherIteration - This is set when we expand a large integer 56 /// operation into smaller integer operations, but the smaller operations are 57 /// not set. This occurs only rarely in practice, for targets that don't have 58 /// 32-bit or larger integer registers. 59 bool NeedsAnotherIteration; 60 61 /// LegalizedNodes - For nodes that are of legal width, and that have more 62 /// than one use, this map indicates what regularized operand to use. This 63 /// allows us to avoid legalizing the same thing more than once. 64 std::map<SDOperand, SDOperand> LegalizedNodes; 65 66 /// PromotedNodes - For nodes that are below legal width, and that have more 67 /// than one use, this map indicates what promoted value to use. This allows 68 /// us to avoid promoting the same thing more than once. 69 std::map<SDOperand, SDOperand> PromotedNodes; 70 71 /// ExpandedNodes - For nodes that need to be expanded, and which have more 72 /// than one use, this map indicates which which operands are the expanded 73 /// version of the input. This allows us to avoid expanding the same node 74 /// more than once. 75 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 76 77 void AddLegalizedOperand(SDOperand From, SDOperand To) { 78 bool isNew = LegalizedNodes.insert(std::make_pair(From, To)).second; 79 assert(isNew && "Got into the map somehow?"); 80 } 81 void AddPromotedOperand(SDOperand From, SDOperand To) { 82 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 83 assert(isNew && "Got into the map somehow?"); 84 } 85 86public: 87 88 SelectionDAGLegalize(SelectionDAG &DAG); 89 90 /// Run - While there is still lowering to do, perform a pass over the DAG. 91 /// Most regularization can be done in a single pass, but targets that require 92 /// large values to be split into registers multiple times (e.g. i64 -> 4x 93 /// i16) require iteration for these values (the first iteration will demote 94 /// to i32, the second will demote to i16). 95 void Run() { 96 do { 97 NeedsAnotherIteration = false; 98 LegalizeDAG(); 99 } while (NeedsAnotherIteration); 100 } 101 102 /// getTypeAction - Return how we should legalize values of this type, either 103 /// it is already legal or we need to expand it into multiple registers of 104 /// smaller integer type, or we need to promote it to a larger type. 105 LegalizeAction getTypeAction(MVT::ValueType VT) const { 106 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3); 107 } 108 109 /// isTypeLegal - Return true if this type is legal on this target. 110 /// 111 bool isTypeLegal(MVT::ValueType VT) const { 112 return getTypeAction(VT) == Legal; 113 } 114 115private: 116 void LegalizeDAG(); 117 118 SDOperand LegalizeOp(SDOperand O); 119 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 120 SDOperand PromoteOp(SDOperand O); 121 122 SDOperand ExpandLibCall(const char *Name, SDNode *Node, 123 SDOperand &Hi); 124 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 125 SDOperand Source); 126 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 127 SDOperand &Lo, SDOperand &Hi); 128 void ExpandAddSub(bool isAdd, SDOperand Op, SDOperand Amt, 129 SDOperand &Lo, SDOperand &Hi); 130 131 SDOperand getIntPtrConstant(uint64_t Val) { 132 return DAG.getConstant(Val, TLI.getPointerTy()); 133 } 134}; 135} 136 137 138SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 139 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 140 ValueTypeActions(TLI.getValueTypeActions()) { 141 assert(MVT::LAST_VALUETYPE <= 16 && 142 "Too many value types for ValueTypeActions to hold!"); 143} 144 145void SelectionDAGLegalize::LegalizeDAG() { 146 SDOperand OldRoot = DAG.getRoot(); 147 SDOperand NewRoot = LegalizeOp(OldRoot); 148 DAG.setRoot(NewRoot); 149 150 ExpandedNodes.clear(); 151 LegalizedNodes.clear(); 152 PromotedNodes.clear(); 153 154 // Remove dead nodes now. 155 DAG.RemoveDeadNodes(OldRoot.Val); 156} 157 158SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 159 assert(getTypeAction(Op.getValueType()) == Legal && 160 "Caller should expand or promote operands that are not legal!"); 161 162 // If this operation defines any values that cannot be represented in a 163 // register on this target, make sure to expand or promote them. 164 if (Op.Val->getNumValues() > 1) { 165 for (unsigned i = 0, e = Op.Val->getNumValues(); i != e; ++i) 166 switch (getTypeAction(Op.Val->getValueType(i))) { 167 case Legal: break; // Nothing to do. 168 case Expand: { 169 SDOperand T1, T2; 170 ExpandOp(Op.getValue(i), T1, T2); 171 assert(LegalizedNodes.count(Op) && 172 "Expansion didn't add legal operands!"); 173 return LegalizedNodes[Op]; 174 } 175 case Promote: 176 PromoteOp(Op.getValue(i)); 177 assert(LegalizedNodes.count(Op) && 178 "Expansion didn't add legal operands!"); 179 return LegalizedNodes[Op]; 180 } 181 } 182 183 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 184 if (I != LegalizedNodes.end()) return I->second; 185 186 SDOperand Tmp1, Tmp2, Tmp3; 187 188 SDOperand Result = Op; 189 SDNode *Node = Op.Val; 190 191 switch (Node->getOpcode()) { 192 default: 193 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 194 assert(0 && "Do not know how to legalize this operator!"); 195 abort(); 196 case ISD::EntryToken: 197 case ISD::FrameIndex: 198 case ISD::GlobalAddress: 199 case ISD::ExternalSymbol: 200 case ISD::ConstantPool: // Nothing to do. 201 assert(getTypeAction(Node->getValueType(0)) == Legal && 202 "This must be legal!"); 203 break; 204 case ISD::CopyFromReg: 205 Tmp1 = LegalizeOp(Node->getOperand(0)); 206 if (Tmp1 != Node->getOperand(0)) 207 Result = DAG.getCopyFromReg(cast<RegSDNode>(Node)->getReg(), 208 Node->getValueType(0), Tmp1); 209 else 210 Result = Op.getValue(0); 211 212 // Since CopyFromReg produces two values, make sure to remember that we 213 // legalized both of them. 214 AddLegalizedOperand(Op.getValue(0), Result); 215 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 216 return Result.getValue(Op.ResNo); 217 case ISD::ImplicitDef: 218 Tmp1 = LegalizeOp(Node->getOperand(0)); 219 if (Tmp1 != Node->getOperand(0)) 220 Result = DAG.getImplicitDef(Tmp1, cast<RegSDNode>(Node)->getReg()); 221 break; 222 case ISD::Constant: 223 // We know we don't need to expand constants here, constants only have one 224 // value and we check that it is fine above. 225 226 // FIXME: Maybe we should handle things like targets that don't support full 227 // 32-bit immediates? 228 break; 229 case ISD::ConstantFP: { 230 // Spill FP immediates to the constant pool if the target cannot directly 231 // codegen them. Targets often have some immediate values that can be 232 // efficiently generated into an FP register without a load. We explicitly 233 // leave these constants as ConstantFP nodes for the target to deal with. 234 235 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 236 237 // Check to see if this FP immediate is already legal. 238 bool isLegal = false; 239 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 240 E = TLI.legal_fpimm_end(); I != E; ++I) 241 if (CFP->isExactlyValue(*I)) { 242 isLegal = true; 243 break; 244 } 245 246 if (!isLegal) { 247 // Otherwise we need to spill the constant to memory. 248 MachineConstantPool *CP = DAG.getMachineFunction().getConstantPool(); 249 250 bool Extend = false; 251 252 // If a FP immediate is precise when represented as a float, we put it 253 // into the constant pool as a float, even if it's is statically typed 254 // as a double. 255 MVT::ValueType VT = CFP->getValueType(0); 256 bool isDouble = VT == MVT::f64; 257 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 258 Type::FloatTy, CFP->getValue()); 259 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) && 260 // Only do this if the target has a native EXTLOAD instruction from 261 // f32. 262 TLI.getOperationAction(ISD::EXTLOAD, 263 MVT::f32) == TargetLowering::Legal) { 264 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy)); 265 VT = MVT::f32; 266 Extend = true; 267 } 268 269 SDOperand CPIdx = DAG.getConstantPool(CP->getConstantPoolIndex(LLVMC), 270 TLI.getPointerTy()); 271 if (Extend) { 272 Result = DAG.getNode(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), CPIdx, 273 MVT::f32); 274 } else { 275 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx); 276 } 277 } 278 break; 279 } 280 case ISD::TokenFactor: { 281 std::vector<SDOperand> Ops; 282 bool Changed = false; 283 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 284 SDOperand Op = Node->getOperand(i); 285 // Fold single-use TokenFactor nodes into this token factor as we go. 286 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) { 287 Changed = true; 288 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j) 289 Ops.push_back(LegalizeOp(Op.getOperand(j))); 290 } else { 291 Ops.push_back(LegalizeOp(Op)); // Legalize the operands 292 Changed |= Ops[i] != Op; 293 } 294 } 295 if (Changed) 296 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 297 break; 298 } 299 300 case ISD::ADJCALLSTACKDOWN: 301 case ISD::ADJCALLSTACKUP: 302 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 303 // There is no need to legalize the size argument (Operand #1) 304 if (Tmp1 != Node->getOperand(0)) 305 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, 306 Node->getOperand(1)); 307 break; 308 case ISD::DYNAMIC_STACKALLOC: 309 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 310 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 311 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 312 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 313 Tmp3 != Node->getOperand(2)) 314 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, Node->getValueType(0), 315 Tmp1, Tmp2, Tmp3); 316 else 317 Result = Op.getValue(0); 318 319 // Since this op produces two values, make sure to remember that we 320 // legalized both of them. 321 AddLegalizedOperand(SDOperand(Node, 0), Result); 322 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 323 return Result.getValue(Op.ResNo); 324 325 case ISD::CALL: { 326 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 327 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 328 329 bool Changed = false; 330 std::vector<SDOperand> Ops; 331 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 332 Ops.push_back(LegalizeOp(Node->getOperand(i))); 333 Changed |= Ops.back() != Node->getOperand(i); 334 } 335 336 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || Changed) { 337 std::vector<MVT::ValueType> RetTyVTs; 338 RetTyVTs.reserve(Node->getNumValues()); 339 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 340 RetTyVTs.push_back(Node->getValueType(i)); 341 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops), 0); 342 } else { 343 Result = Result.getValue(0); 344 } 345 // Since calls produce multiple values, make sure to remember that we 346 // legalized all of them. 347 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 348 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 349 return Result.getValue(Op.ResNo); 350 } 351 case ISD::BR: 352 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 353 if (Tmp1 != Node->getOperand(0)) 354 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1)); 355 break; 356 357 case ISD::BRCOND: 358 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 359 360 switch (getTypeAction(Node->getOperand(1).getValueType())) { 361 case Expand: assert(0 && "It's impossible to expand bools"); 362 case Legal: 363 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 364 break; 365 case Promote: 366 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 367 break; 368 } 369 // Basic block destination (Op#2) is always legal. 370 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 371 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 372 Node->getOperand(2)); 373 break; 374 375 case ISD::LOAD: 376 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 377 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 378 if (Tmp1 != Node->getOperand(0) || 379 Tmp2 != Node->getOperand(1)) 380 Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2); 381 else 382 Result = SDOperand(Node, 0); 383 384 // Since loads produce two values, make sure to remember that we legalized 385 // both of them. 386 AddLegalizedOperand(SDOperand(Node, 0), Result); 387 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 388 return Result.getValue(Op.ResNo); 389 390 case ISD::EXTLOAD: 391 case ISD::SEXTLOAD: 392 case ISD::ZEXTLOAD: 393 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 394 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 395 if (Tmp1 != Node->getOperand(0) || 396 Tmp2 != Node->getOperand(1)) 397 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, Tmp2, 398 cast<MVTSDNode>(Node)->getExtraValueType()); 399 else 400 Result = SDOperand(Node, 0); 401 402 // Since loads produce two values, make sure to remember that we legalized 403 // both of them. 404 AddLegalizedOperand(SDOperand(Node, 0), Result); 405 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 406 return Result.getValue(Op.ResNo); 407 408 case ISD::EXTRACT_ELEMENT: 409 // Get both the low and high parts. 410 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 411 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 412 Result = Tmp2; // 1 -> Hi 413 else 414 Result = Tmp1; // 0 -> Lo 415 break; 416 417 case ISD::CopyToReg: 418 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 419 420 switch (getTypeAction(Node->getOperand(1).getValueType())) { 421 case Legal: 422 // Legalize the incoming value (must be legal). 423 Tmp2 = LegalizeOp(Node->getOperand(1)); 424 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 425 Result = DAG.getCopyToReg(Tmp1, Tmp2, cast<RegSDNode>(Node)->getReg()); 426 break; 427 case Promote: 428 Tmp2 = PromoteOp(Node->getOperand(1)); 429 Result = DAG.getCopyToReg(Tmp1, Tmp2, cast<RegSDNode>(Node)->getReg()); 430 break; 431 case Expand: 432 SDOperand Lo, Hi; 433 ExpandOp(Node->getOperand(1), Lo, Hi); 434 unsigned Reg = cast<RegSDNode>(Node)->getReg(); 435 Lo = DAG.getCopyToReg(Tmp1, Lo, Reg); 436 Hi = DAG.getCopyToReg(Tmp1, Hi, Reg+1); 437 // Note that the copytoreg nodes are independent of each other. 438 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 439 assert(isTypeLegal(Result.getValueType()) && 440 "Cannot expand multiple times yet (i64 -> i16)"); 441 break; 442 } 443 break; 444 445 case ISD::RET: 446 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 447 switch (Node->getNumOperands()) { 448 case 2: // ret val 449 switch (getTypeAction(Node->getOperand(1).getValueType())) { 450 case Legal: 451 Tmp2 = LegalizeOp(Node->getOperand(1)); 452 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 453 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 454 break; 455 case Expand: { 456 SDOperand Lo, Hi; 457 ExpandOp(Node->getOperand(1), Lo, Hi); 458 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi); 459 break; 460 } 461 case Promote: 462 Tmp2 = PromoteOp(Node->getOperand(1)); 463 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 464 break; 465 } 466 break; 467 case 1: // ret void 468 if (Tmp1 != Node->getOperand(0)) 469 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1); 470 break; 471 default: { // ret <values> 472 std::vector<SDOperand> NewValues; 473 NewValues.push_back(Tmp1); 474 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) 475 switch (getTypeAction(Node->getOperand(i).getValueType())) { 476 case Legal: 477 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 478 break; 479 case Expand: { 480 SDOperand Lo, Hi; 481 ExpandOp(Node->getOperand(i), Lo, Hi); 482 NewValues.push_back(Lo); 483 NewValues.push_back(Hi); 484 break; 485 } 486 case Promote: 487 assert(0 && "Can't promote multiple return value yet!"); 488 } 489 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues); 490 break; 491 } 492 } 493 break; 494 case ISD::STORE: 495 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 496 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 497 498 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 499 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){ 500 if (CFP->getValueType(0) == MVT::f32) { 501 union { 502 unsigned I; 503 float F; 504 } V; 505 V.F = CFP->getValue(); 506 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 507 DAG.getConstant(V.I, MVT::i32), Tmp2); 508 } else { 509 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 510 union { 511 uint64_t I; 512 double F; 513 } V; 514 V.F = CFP->getValue(); 515 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 516 DAG.getConstant(V.I, MVT::i64), Tmp2); 517 } 518 Node = Result.Val; 519 } 520 521 switch (getTypeAction(Node->getOperand(1).getValueType())) { 522 case Legal: { 523 SDOperand Val = LegalizeOp(Node->getOperand(1)); 524 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) || 525 Tmp2 != Node->getOperand(2)) 526 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2); 527 break; 528 } 529 case Promote: 530 // Truncate the value and store the result. 531 Tmp3 = PromoteOp(Node->getOperand(1)); 532 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2, 533 Node->getOperand(1).getValueType()); 534 break; 535 536 case Expand: 537 SDOperand Lo, Hi; 538 ExpandOp(Node->getOperand(1), Lo, Hi); 539 540 if (!TLI.isLittleEndian()) 541 std::swap(Lo, Hi); 542 543 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2); 544 545 unsigned IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8; 546 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 547 getIntPtrConstant(IncrementSize)); 548 assert(isTypeLegal(Tmp2.getValueType()) && 549 "Pointers must be legal!"); 550 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2); 551 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 552 break; 553 } 554 break; 555 case ISD::TRUNCSTORE: 556 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 557 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 558 559 switch (getTypeAction(Node->getOperand(1).getValueType())) { 560 case Legal: 561 Tmp2 = LegalizeOp(Node->getOperand(1)); 562 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 563 Tmp3 != Node->getOperand(2)) 564 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 565 cast<MVTSDNode>(Node)->getExtraValueType()); 566 break; 567 case Promote: 568 case Expand: 569 assert(0 && "Cannot handle illegal TRUNCSTORE yet!"); 570 } 571 break; 572 case ISD::SELECT: 573 switch (getTypeAction(Node->getOperand(0).getValueType())) { 574 case Expand: assert(0 && "It's impossible to expand bools"); 575 case Legal: 576 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 577 break; 578 case Promote: 579 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 580 break; 581 } 582 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 583 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 584 585 switch (TLI.getOperationAction(Node->getOpcode(), Tmp2.getValueType())) { 586 default: assert(0 && "This action is not supported yet!"); 587 case TargetLowering::Legal: 588 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 589 Tmp3 != Node->getOperand(2)) 590 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0), 591 Tmp1, Tmp2, Tmp3); 592 break; 593 case TargetLowering::Promote: { 594 MVT::ValueType NVT = 595 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 596 unsigned ExtOp, TruncOp; 597 if (MVT::isInteger(Tmp2.getValueType())) { 598 ExtOp = ISD::ZERO_EXTEND; 599 TruncOp = ISD::TRUNCATE; 600 } else { 601 ExtOp = ISD::FP_EXTEND; 602 TruncOp = ISD::FP_ROUND; 603 } 604 // Promote each of the values to the new type. 605 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 606 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 607 // Perform the larger operation, then round down. 608 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 609 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 610 break; 611 } 612 } 613 break; 614 case ISD::SETCC: 615 switch (getTypeAction(Node->getOperand(0).getValueType())) { 616 case Legal: 617 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 618 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 619 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 620 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), 621 Node->getValueType(0), Tmp1, Tmp2); 622 break; 623 case Promote: 624 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS 625 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS 626 627 // If this is an FP compare, the operands have already been extended. 628 if (MVT::isInteger(Node->getOperand(0).getValueType())) { 629 MVT::ValueType VT = Node->getOperand(0).getValueType(); 630 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 631 632 // Otherwise, we have to insert explicit sign or zero extends. Note 633 // that we could insert sign extends for ALL conditions, but zero extend 634 // is cheaper on many machines (an AND instead of two shifts), so prefer 635 // it. 636 switch (cast<SetCCSDNode>(Node)->getCondition()) { 637 default: assert(0 && "Unknown integer comparison!"); 638 case ISD::SETEQ: 639 case ISD::SETNE: 640 case ISD::SETUGE: 641 case ISD::SETUGT: 642 case ISD::SETULE: 643 case ISD::SETULT: 644 // ALL of these operations will work if we either sign or zero extend 645 // the operands (including the unsigned comparisons!). Zero extend is 646 // usually a simpler/cheaper operation, so prefer it. 647 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND_INREG, NVT, Tmp1, VT); 648 Tmp2 = DAG.getNode(ISD::ZERO_EXTEND_INREG, NVT, Tmp2, VT); 649 break; 650 case ISD::SETGE: 651 case ISD::SETGT: 652 case ISD::SETLT: 653 case ISD::SETLE: 654 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, VT); 655 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, VT); 656 break; 657 } 658 659 } 660 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), 661 Node->getValueType(0), Tmp1, Tmp2); 662 break; 663 case Expand: 664 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 665 ExpandOp(Node->getOperand(0), LHSLo, LHSHi); 666 ExpandOp(Node->getOperand(1), RHSLo, RHSHi); 667 switch (cast<SetCCSDNode>(Node)->getCondition()) { 668 case ISD::SETEQ: 669 case ISD::SETNE: 670 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 671 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 672 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 673 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), 674 Node->getValueType(0), Tmp1, 675 DAG.getConstant(0, Tmp1.getValueType())); 676 break; 677 default: 678 // FIXME: This generated code sucks. 679 ISD::CondCode LowCC; 680 switch (cast<SetCCSDNode>(Node)->getCondition()) { 681 default: assert(0 && "Unknown integer setcc!"); 682 case ISD::SETLT: 683 case ISD::SETULT: LowCC = ISD::SETULT; break; 684 case ISD::SETGT: 685 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 686 case ISD::SETLE: 687 case ISD::SETULE: LowCC = ISD::SETULE; break; 688 case ISD::SETGE: 689 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 690 } 691 692 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 693 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 694 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 695 696 // NOTE: on targets without efficient SELECT of bools, we can always use 697 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 698 Tmp1 = DAG.getSetCC(LowCC, Node->getValueType(0), LHSLo, RHSLo); 699 Tmp2 = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), 700 Node->getValueType(0), LHSHi, RHSHi); 701 Result = DAG.getSetCC(ISD::SETEQ, Node->getValueType(0), LHSHi, RHSHi); 702 Result = DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 703 Result, Tmp1, Tmp2); 704 break; 705 } 706 } 707 break; 708 709 case ISD::MEMSET: 710 case ISD::MEMCPY: 711 case ISD::MEMMOVE: { 712 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 713 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 714 715 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 716 switch (getTypeAction(Node->getOperand(2).getValueType())) { 717 case Expand: assert(0 && "Cannot expand a byte!"); 718 case Legal: 719 Tmp3 = LegalizeOp(Node->getOperand(2)); 720 break; 721 case Promote: 722 Tmp3 = PromoteOp(Node->getOperand(2)); 723 break; 724 } 725 } else { 726 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 727 } 728 729 SDOperand Tmp4; 730 switch (getTypeAction(Node->getOperand(3).getValueType())) { 731 case Expand: assert(0 && "Cannot expand this yet!"); 732 case Legal: 733 Tmp4 = LegalizeOp(Node->getOperand(3)); 734 break; 735 case Promote: 736 Tmp4 = PromoteOp(Node->getOperand(3)); 737 break; 738 } 739 740 SDOperand Tmp5; 741 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 742 case Expand: assert(0 && "Cannot expand this yet!"); 743 case Legal: 744 Tmp5 = LegalizeOp(Node->getOperand(4)); 745 break; 746 case Promote: 747 Tmp5 = PromoteOp(Node->getOperand(4)); 748 break; 749 } 750 751 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 752 default: assert(0 && "This action not implemented for this operation!"); 753 case TargetLowering::Legal: 754 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 755 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) || 756 Tmp5 != Node->getOperand(4)) { 757 std::vector<SDOperand> Ops; 758 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 759 Ops.push_back(Tmp4); Ops.push_back(Tmp5); 760 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops); 761 } 762 break; 763 case TargetLowering::Expand: { 764 // Otherwise, the target does not support this operation. Lower the 765 // operation to an explicit libcall as appropriate. 766 MVT::ValueType IntPtr = TLI.getPointerTy(); 767 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType(); 768 std::vector<std::pair<SDOperand, const Type*> > Args; 769 770 const char *FnName = 0; 771 if (Node->getOpcode() == ISD::MEMSET) { 772 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 773 // Extend the ubyte argument to be an int value for the call. 774 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 775 Args.push_back(std::make_pair(Tmp3, Type::IntTy)); 776 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 777 778 FnName = "memset"; 779 } else if (Node->getOpcode() == ISD::MEMCPY || 780 Node->getOpcode() == ISD::MEMMOVE) { 781 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 782 Args.push_back(std::make_pair(Tmp3, IntPtrTy)); 783 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 784 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 785 } else { 786 assert(0 && "Unknown op!"); 787 } 788 std::pair<SDOperand,SDOperand> CallResult = 789 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, 790 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 791 Result = LegalizeOp(CallResult.second); 792 break; 793 } 794 case TargetLowering::Custom: 795 std::vector<SDOperand> Ops; 796 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 797 Ops.push_back(Tmp4); Ops.push_back(Tmp5); 798 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops); 799 Result = TLI.LowerOperation(Result); 800 Result = LegalizeOp(Result); 801 break; 802 } 803 break; 804 } 805 case ISD::ADD_PARTS: 806 case ISD::SUB_PARTS: { 807 std::vector<SDOperand> Ops; 808 bool Changed = false; 809 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 810 Ops.push_back(LegalizeOp(Node->getOperand(i))); 811 Changed |= Ops.back() != Node->getOperand(i); 812 } 813 if (Changed) 814 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops); 815 break; 816 } 817 case ISD::ADD: 818 case ISD::SUB: 819 case ISD::MUL: 820 case ISD::UDIV: 821 case ISD::SDIV: 822 case ISD::UREM: 823 case ISD::SREM: 824 case ISD::AND: 825 case ISD::OR: 826 case ISD::XOR: 827 case ISD::SHL: 828 case ISD::SRL: 829 case ISD::SRA: 830 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 831 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 832 if (Tmp1 != Node->getOperand(0) || 833 Tmp2 != Node->getOperand(1)) 834 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2); 835 break; 836 case ISD::ZERO_EXTEND: 837 case ISD::SIGN_EXTEND: 838 case ISD::TRUNCATE: 839 case ISD::FP_EXTEND: 840 case ISD::FP_ROUND: 841 case ISD::FP_TO_SINT: 842 case ISD::FP_TO_UINT: 843 case ISD::SINT_TO_FP: 844 case ISD::UINT_TO_FP: 845 switch (getTypeAction(Node->getOperand(0).getValueType())) { 846 case Legal: 847 Tmp1 = LegalizeOp(Node->getOperand(0)); 848 if (Tmp1 != Node->getOperand(0)) 849 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 850 break; 851 case Expand: 852 if (Node->getOpcode() == ISD::SINT_TO_FP || 853 Node->getOpcode() == ISD::UINT_TO_FP) { 854 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 855 Node->getValueType(0), Node->getOperand(0)); 856 Result = LegalizeOp(Result); 857 break; 858 } 859 // In the expand case, we must be dealing with a truncate, because 860 // otherwise the result would be larger than the source. 861 assert(Node->getOpcode() == ISD::TRUNCATE && 862 "Shouldn't need to expand other operators here!"); 863 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 864 865 // Since the result is legal, we should just be able to truncate the low 866 // part of the source. 867 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 868 break; 869 870 case Promote: 871 switch (Node->getOpcode()) { 872 case ISD::ZERO_EXTEND: 873 Result = PromoteOp(Node->getOperand(0)); 874 // NOTE: Any extend would work here... 875 Result = DAG.getNode(ISD::ZERO_EXTEND, Op.getValueType(), Result); 876 Result = DAG.getNode(ISD::ZERO_EXTEND_INREG, Op.getValueType(), 877 Result, Node->getOperand(0).getValueType()); 878 break; 879 case ISD::SIGN_EXTEND: 880 Result = PromoteOp(Node->getOperand(0)); 881 // NOTE: Any extend would work here... 882 Result = DAG.getNode(ISD::ZERO_EXTEND, Op.getValueType(), Result); 883 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 884 Result, Node->getOperand(0).getValueType()); 885 break; 886 case ISD::TRUNCATE: 887 Result = PromoteOp(Node->getOperand(0)); 888 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 889 break; 890 case ISD::FP_EXTEND: 891 Result = PromoteOp(Node->getOperand(0)); 892 if (Result.getValueType() != Op.getValueType()) 893 // Dynamically dead while we have only 2 FP types. 894 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 895 break; 896 case ISD::FP_ROUND: 897 case ISD::FP_TO_SINT: 898 case ISD::FP_TO_UINT: 899 Result = PromoteOp(Node->getOperand(0)); 900 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 901 break; 902 case ISD::SINT_TO_FP: 903 Result = PromoteOp(Node->getOperand(0)); 904 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 905 Result, Node->getOperand(0).getValueType()); 906 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result); 907 break; 908 case ISD::UINT_TO_FP: 909 Result = PromoteOp(Node->getOperand(0)); 910 Result = DAG.getNode(ISD::ZERO_EXTEND_INREG, Result.getValueType(), 911 Result, Node->getOperand(0).getValueType()); 912 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result); 913 break; 914 } 915 } 916 break; 917 case ISD::FP_ROUND_INREG: 918 case ISD::SIGN_EXTEND_INREG: 919 case ISD::ZERO_EXTEND_INREG: { 920 Tmp1 = LegalizeOp(Node->getOperand(0)); 921 MVT::ValueType ExtraVT = cast<MVTSDNode>(Node)->getExtraValueType(); 922 923 // If this operation is not supported, convert it to a shl/shr or load/store 924 // pair. 925 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 926 default: assert(0 && "This action not supported for this op yet!"); 927 case TargetLowering::Legal: 928 if (Tmp1 != Node->getOperand(0)) 929 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 930 ExtraVT); 931 break; 932 case TargetLowering::Expand: 933 // If this is an integer extend and shifts are supported, do that. 934 if (Node->getOpcode() == ISD::ZERO_EXTEND_INREG) { 935 // NOTE: we could fall back on load/store here too for targets without 936 // AND. However, it is doubtful that any exist. 937 // AND out the appropriate bits. 938 SDOperand Mask = 939 DAG.getConstant((1ULL << MVT::getSizeInBits(ExtraVT))-1, 940 Node->getValueType(0)); 941 Result = DAG.getNode(ISD::AND, Node->getValueType(0), 942 Node->getOperand(0), Mask); 943 } else if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 944 // NOTE: we could fall back on load/store here too for targets without 945 // SAR. However, it is doubtful that any exist. 946 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 947 MVT::getSizeInBits(ExtraVT); 948 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 949 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 950 Node->getOperand(0), ShiftCst); 951 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 952 Result, ShiftCst); 953 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 954 // The only way we can lower this is to turn it into a STORETRUNC, 955 // EXTLOAD pair, targetting a temporary location (a stack slot). 956 957 // NOTE: there is a choice here between constantly creating new stack 958 // slots and always reusing the same one. We currently always create 959 // new ones, as reuse may inhibit scheduling. 960 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 961 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty); 962 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty); 963 MachineFunction &MF = DAG.getMachineFunction(); 964 int SSFI = 965 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 966 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 967 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(), 968 Node->getOperand(0), StackSlot, ExtraVT); 969 Result = DAG.getNode(ISD::EXTLOAD, Node->getValueType(0), 970 Result, StackSlot, ExtraVT); 971 } else { 972 assert(0 && "Unknown op"); 973 } 974 Result = LegalizeOp(Result); 975 break; 976 } 977 break; 978 } 979 } 980 981 if (!Op.Val->hasOneUse()) 982 AddLegalizedOperand(Op, Result); 983 984 return Result; 985} 986 987/// PromoteOp - Given an operation that produces a value in an invalid type, 988/// promote it to compute the value into a larger type. The produced value will 989/// have the correct bits for the low portion of the register, but no guarantee 990/// is made about the top bits: it may be zero, sign-extended, or garbage. 991SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 992 MVT::ValueType VT = Op.getValueType(); 993 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 994 assert(getTypeAction(VT) == Promote && 995 "Caller should expand or legalize operands that are not promotable!"); 996 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 997 "Cannot promote to smaller type!"); 998 999 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 1000 if (I != PromotedNodes.end()) return I->second; 1001 1002 SDOperand Tmp1, Tmp2, Tmp3; 1003 1004 SDOperand Result; 1005 SDNode *Node = Op.Val; 1006 1007 // Promotion needs an optimization step to clean up after it, and is not 1008 // careful to avoid operations the target does not support. Make sure that 1009 // all generated operations are legalized in the next iteration. 1010 NeedsAnotherIteration = true; 1011 1012 switch (Node->getOpcode()) { 1013 default: 1014 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 1015 assert(0 && "Do not know how to promote this operator!"); 1016 abort(); 1017 case ISD::Constant: 1018 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 1019 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 1020 break; 1021 case ISD::ConstantFP: 1022 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 1023 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 1024 break; 1025 case ISD::CopyFromReg: 1026 Result = DAG.getCopyFromReg(cast<RegSDNode>(Node)->getReg(), NVT, 1027 Node->getOperand(0)); 1028 // Remember that we legalized the chain. 1029 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1030 break; 1031 1032 case ISD::SETCC: 1033 assert(getTypeAction(TLI.getSetCCResultTy()) == Legal && 1034 "SetCC type is not legal??"); 1035 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), 1036 TLI.getSetCCResultTy(), Node->getOperand(0), 1037 Node->getOperand(1)); 1038 Result = LegalizeOp(Result); 1039 break; 1040 1041 case ISD::TRUNCATE: 1042 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1043 case Legal: 1044 Result = LegalizeOp(Node->getOperand(0)); 1045 assert(Result.getValueType() >= NVT && 1046 "This truncation doesn't make sense!"); 1047 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 1048 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 1049 break; 1050 case Promote: 1051 // The truncation is not required, because we don't guarantee anything 1052 // about high bits anyway. 1053 Result = PromoteOp(Node->getOperand(0)); 1054 break; 1055 case Expand: 1056 assert(0 && "Cannot handle expand yet"); 1057 } 1058 break; 1059 case ISD::SIGN_EXTEND: 1060 case ISD::ZERO_EXTEND: 1061 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1062 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 1063 case Legal: 1064 // Input is legal? Just do extend all the way to the larger type. 1065 Result = LegalizeOp(Node->getOperand(0)); 1066 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 1067 break; 1068 case Promote: 1069 // Promote the reg if it's smaller. 1070 Result = PromoteOp(Node->getOperand(0)); 1071 // The high bits are not guaranteed to be anything. Insert an extend. 1072 if (Node->getOpcode() == ISD::SIGN_EXTEND) 1073 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 1074 Node->getOperand(0).getValueType()); 1075 else 1076 Result = DAG.getNode(ISD::ZERO_EXTEND_INREG, NVT, Result, 1077 Node->getOperand(0).getValueType()); 1078 break; 1079 } 1080 break; 1081 1082 case ISD::FP_EXTEND: 1083 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 1084 case ISD::FP_ROUND: 1085 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1086 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 1087 case Promote: assert(0 && "Unreachable with 2 FP types!"); 1088 case Legal: 1089 // Input is legal? Do an FP_ROUND_INREG. 1090 Result = LegalizeOp(Node->getOperand(0)); 1091 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT); 1092 break; 1093 } 1094 break; 1095 1096 case ISD::SINT_TO_FP: 1097 case ISD::UINT_TO_FP: 1098 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1099 case Legal: 1100 Result = LegalizeOp(Node->getOperand(0)); 1101 // No extra round required here. 1102 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 1103 break; 1104 1105 case Promote: 1106 Result = PromoteOp(Node->getOperand(0)); 1107 if (Node->getOpcode() == ISD::SINT_TO_FP) 1108 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1109 Result, Node->getOperand(0).getValueType()); 1110 else 1111 Result = DAG.getNode(ISD::ZERO_EXTEND_INREG, Result.getValueType(), 1112 Result, Node->getOperand(0).getValueType()); 1113 // No extra round required here. 1114 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 1115 break; 1116 case Expand: 1117 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 1118 Node->getOperand(0)); 1119 Result = LegalizeOp(Result); 1120 1121 // Round if we cannot tolerate excess precision. 1122 if (NoExcessFPPrecision) 1123 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT); 1124 break; 1125 } 1126 break; 1127 1128 case ISD::FP_TO_SINT: 1129 case ISD::FP_TO_UINT: 1130 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1131 case Legal: 1132 Tmp1 = LegalizeOp(Node->getOperand(0)); 1133 break; 1134 case Promote: 1135 // The input result is prerounded, so we don't have to do anything 1136 // special. 1137 Tmp1 = PromoteOp(Node->getOperand(0)); 1138 break; 1139 case Expand: 1140 assert(0 && "not implemented"); 1141 } 1142 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 1143 break; 1144 1145 case ISD::AND: 1146 case ISD::OR: 1147 case ISD::XOR: 1148 case ISD::ADD: 1149 case ISD::SUB: 1150 case ISD::MUL: 1151 // The input may have strange things in the top bits of the registers, but 1152 // these operations don't care. They may have wierd bits going out, but 1153 // that too is okay if they are integer operations. 1154 Tmp1 = PromoteOp(Node->getOperand(0)); 1155 Tmp2 = PromoteOp(Node->getOperand(1)); 1156 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 1157 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 1158 1159 // However, if this is a floating point operation, they will give excess 1160 // precision that we may not be able to tolerate. If we DO allow excess 1161 // precision, just leave it, otherwise excise it. 1162 // FIXME: Why would we need to round FP ops more than integer ones? 1163 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 1164 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 1165 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT); 1166 break; 1167 1168 case ISD::SDIV: 1169 case ISD::SREM: 1170 // These operators require that their input be sign extended. 1171 Tmp1 = PromoteOp(Node->getOperand(0)); 1172 Tmp2 = PromoteOp(Node->getOperand(1)); 1173 if (MVT::isInteger(NVT)) { 1174 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, VT); 1175 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, VT); 1176 } 1177 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 1178 1179 // Perform FP_ROUND: this is probably overly pessimistic. 1180 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 1181 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT); 1182 break; 1183 1184 case ISD::UDIV: 1185 case ISD::UREM: 1186 // These operators require that their input be zero extended. 1187 Tmp1 = PromoteOp(Node->getOperand(0)); 1188 Tmp2 = PromoteOp(Node->getOperand(1)); 1189 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 1190 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND_INREG, NVT, Tmp1, VT); 1191 Tmp2 = DAG.getNode(ISD::ZERO_EXTEND_INREG, NVT, Tmp2, VT); 1192 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 1193 break; 1194 1195 case ISD::SHL: 1196 Tmp1 = PromoteOp(Node->getOperand(0)); 1197 Tmp2 = LegalizeOp(Node->getOperand(1)); 1198 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2); 1199 break; 1200 case ISD::SRA: 1201 // The input value must be properly sign extended. 1202 Tmp1 = PromoteOp(Node->getOperand(0)); 1203 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, VT); 1204 Tmp2 = LegalizeOp(Node->getOperand(1)); 1205 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2); 1206 break; 1207 case ISD::SRL: 1208 // The input value must be properly zero extended. 1209 Tmp1 = PromoteOp(Node->getOperand(0)); 1210 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND_INREG, NVT, Tmp1, VT); 1211 Tmp2 = LegalizeOp(Node->getOperand(1)); 1212 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2); 1213 break; 1214 case ISD::LOAD: 1215 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1216 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1217 Result = DAG.getNode(ISD::EXTLOAD, NVT, Tmp1, Tmp2, VT); 1218 1219 // Remember that we legalized the chain. 1220 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1221 break; 1222 case ISD::SELECT: 1223 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1224 case Expand: assert(0 && "It's impossible to expand bools"); 1225 case Legal: 1226 Tmp1 = LegalizeOp(Node->getOperand(0));// Legalize the condition. 1227 break; 1228 case Promote: 1229 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 1230 break; 1231 } 1232 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 1233 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 1234 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3); 1235 break; 1236 case ISD::CALL: { 1237 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1238 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 1239 1240 std::vector<SDOperand> Ops; 1241 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) 1242 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1243 1244 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 1245 "Can only promote single result calls"); 1246 std::vector<MVT::ValueType> RetTyVTs; 1247 RetTyVTs.reserve(2); 1248 RetTyVTs.push_back(NVT); 1249 RetTyVTs.push_back(MVT::Other); 1250 SDNode *NC = DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops); 1251 Result = SDOperand(NC, 0); 1252 1253 // Insert the new chain mapping. 1254 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1255 break; 1256 } 1257 } 1258 1259 assert(Result.Val && "Didn't set a result!"); 1260 AddPromotedOperand(Op, Result); 1261 return Result; 1262} 1263 1264/// ExpandAddSub - Find a clever way to expand this add operation into 1265/// subcomponents. 1266void SelectionDAGLegalize::ExpandAddSub(bool isAdd, SDOperand LHS,SDOperand RHS, 1267 SDOperand &Lo, SDOperand &Hi) { 1268 // Expand the subcomponents. 1269 SDOperand LHSL, LHSH, RHSL, RHSH; 1270 ExpandOp(LHS, LHSL, LHSH); 1271 ExpandOp(RHS, RHSL, RHSH); 1272 1273 // Convert this add to the appropriate ADDC pair. The low part has no carry 1274 // in. 1275 unsigned Opc = isAdd ? ISD::ADD_PARTS : ISD::SUB_PARTS; 1276 std::vector<SDOperand> Ops; 1277 Ops.push_back(LHSL); 1278 Ops.push_back(LHSH); 1279 Ops.push_back(RHSL); 1280 Ops.push_back(RHSH); 1281 Lo = DAG.getNode(Opc, LHSL.getValueType(), Ops); 1282 Hi = Lo.getValue(1); 1283} 1284 1285/// ExpandShift - Try to find a clever way to expand this shift operation out to 1286/// smaller elements. If we can't find a way that is more efficient than a 1287/// libcall on this target, return false. Otherwise, return true with the 1288/// low-parts expanded into Lo and Hi. 1289bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 1290 SDOperand &Lo, SDOperand &Hi) { 1291 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 1292 "This is not a shift!"); 1293 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 1294 1295 // If we have an efficient select operation (or if the selects will all fold 1296 // away), lower to some complex code, otherwise just emit the libcall. 1297 if (TLI.getOperationAction(ISD::SELECT, NVT) != TargetLowering::Legal && 1298 !isa<ConstantSDNode>(Amt)) 1299 return false; 1300 1301 SDOperand InL, InH; 1302 ExpandOp(Op, InL, InH); 1303 SDOperand ShAmt = LegalizeOp(Amt); 1304 MVT::ValueType ShTy = ShAmt.getValueType(); 1305 1306 unsigned NVTBits = MVT::getSizeInBits(NVT); 1307 SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy, // NAmt = 32-ShAmt 1308 DAG.getConstant(NVTBits, ShTy), ShAmt); 1309 1310 // Compare the unmasked shift amount against 32. 1311 SDOperand Cond = DAG.getSetCC(ISD::SETGE, TLI.getSetCCResultTy(), ShAmt, 1312 DAG.getConstant(NVTBits, ShTy)); 1313 1314 if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) { 1315 ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt, // ShAmt &= 31 1316 DAG.getConstant(NVTBits-1, ShTy)); 1317 NAmt = DAG.getNode(ISD::AND, ShTy, NAmt, // NAmt &= 31 1318 DAG.getConstant(NVTBits-1, ShTy)); 1319 } 1320 1321 if (Opc == ISD::SHL) { 1322 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt) 1323 DAG.getNode(ISD::SHL, NVT, InH, ShAmt), 1324 DAG.getNode(ISD::SRL, NVT, InL, NAmt)); 1325 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31 1326 1327 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 1328 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2); 1329 } else { 1330 SDOperand HiLoPart = DAG.getNode(ISD::SELECT, NVT, 1331 DAG.getSetCC(ISD::SETEQ, 1332 TLI.getSetCCResultTy(), NAmt, 1333 DAG.getConstant(32, ShTy)), 1334 DAG.getConstant(0, NVT), 1335 DAG.getNode(ISD::SHL, NVT, InH, NAmt)); 1336 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << NAmt) | (Lo >> Amt) 1337 HiLoPart, 1338 DAG.getNode(ISD::SRL, NVT, InL, ShAmt)); 1339 SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt); // T2 = InH >> ShAmt&31 1340 1341 SDOperand HiPart; 1342 if (Opc == ISD::SRA) 1343 HiPart = DAG.getNode(ISD::SRA, NVT, InH, 1344 DAG.getConstant(NVTBits-1, ShTy)); 1345 else 1346 HiPart = DAG.getConstant(0, NVT); 1347 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 1348 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart, T2); 1349 } 1350 return true; 1351} 1352 1353/// FindLatestAdjCallStackDown - Scan up the dag to find the latest (highest 1354/// NodeDepth) node that is an AdjCallStackDown operation and occurs later than 1355/// Found. 1356static void FindLatestAdjCallStackDown(SDNode *Node, SDNode *&Found) { 1357 if (Node->getNodeDepth() <= Found->getNodeDepth()) return; 1358 1359 // If we found an ADJCALLSTACKDOWN, we already know this node occurs later 1360 // than the Found node. Just remember this node and return. 1361 if (Node->getOpcode() == ISD::ADJCALLSTACKDOWN) { 1362 Found = Node; 1363 return; 1364 } 1365 1366 // Otherwise, scan the operands of Node to see if any of them is a call. 1367 assert(Node->getNumOperands() != 0 && 1368 "All leaves should have depth equal to the entry node!"); 1369 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i) 1370 FindLatestAdjCallStackDown(Node->getOperand(i).Val, Found); 1371 1372 // Tail recurse for the last iteration. 1373 FindLatestAdjCallStackDown(Node->getOperand(Node->getNumOperands()-1).Val, 1374 Found); 1375} 1376 1377 1378/// FindEarliestAdjCallStackUp - Scan down the dag to find the earliest (lowest 1379/// NodeDepth) node that is an AdjCallStackUp operation and occurs more recent 1380/// than Found. 1381static void FindEarliestAdjCallStackUp(SDNode *Node, SDNode *&Found) { 1382 if (Found && Node->getNodeDepth() >= Found->getNodeDepth()) return; 1383 1384 // If we found an ADJCALLSTACKUP, we already know this node occurs earlier 1385 // than the Found node. Just remember this node and return. 1386 if (Node->getOpcode() == ISD::ADJCALLSTACKUP) { 1387 Found = Node; 1388 return; 1389 } 1390 1391 // Otherwise, scan the operands of Node to see if any of them is a call. 1392 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 1393 if (UI == E) return; 1394 for (--E; UI != E; ++UI) 1395 FindEarliestAdjCallStackUp(*UI, Found); 1396 1397 // Tail recurse for the last iteration. 1398 FindEarliestAdjCallStackUp(*UI, Found); 1399} 1400 1401/// FindAdjCallStackUp - Given a chained node that is part of a call sequence, 1402/// find the ADJCALLSTACKUP node that terminates the call sequence. 1403static SDNode *FindAdjCallStackUp(SDNode *Node) { 1404 if (Node->getOpcode() == ISD::ADJCALLSTACKUP) 1405 return Node; 1406 assert(!Node->use_empty() && "Could not find ADJCALLSTACKUP!"); 1407 1408 if (Node->hasOneUse()) // Simple case, only has one user to check. 1409 return FindAdjCallStackUp(*Node->use_begin()); 1410 1411 SDOperand TheChain(Node, Node->getNumValues()-1); 1412 assert(TheChain.getValueType() == MVT::Other && "Is not a token chain!"); 1413 1414 for (SDNode::use_iterator UI = Node->use_begin(), 1415 E = Node->use_end(); ; ++UI) { 1416 assert(UI != E && "Didn't find a user of the tokchain, no ADJCALLSTACKUP!"); 1417 1418 // Make sure to only follow users of our token chain. 1419 SDNode *User = *UI; 1420 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 1421 if (User->getOperand(i) == TheChain) 1422 return FindAdjCallStackUp(User); 1423 } 1424 assert(0 && "Unreachable"); 1425 abort(); 1426} 1427 1428/// FindInputOutputChains - If we are replacing an operation with a call we need 1429/// to find the call that occurs before and the call that occurs after it to 1430/// properly serialize the calls in the block. 1431static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain, 1432 SDOperand Entry) { 1433 SDNode *LatestAdjCallStackDown = Entry.Val; 1434 FindLatestAdjCallStackDown(OpNode, LatestAdjCallStackDown); 1435 //std::cerr << "Found node: "; LatestAdjCallStackDown->dump(); std::cerr <<"\n"; 1436 1437 SDNode *LatestAdjCallStackUp = FindAdjCallStackUp(LatestAdjCallStackDown); 1438 1439 1440 SDNode *EarliestAdjCallStackUp = 0; 1441 FindEarliestAdjCallStackUp(OpNode, EarliestAdjCallStackUp); 1442 1443 if (EarliestAdjCallStackUp) { 1444 //std::cerr << "Found node: "; 1445 //EarliestAdjCallStackUp->dump(); std::cerr <<"\n"; 1446 } 1447 1448 return SDOperand(LatestAdjCallStackUp, 0); 1449} 1450 1451 1452 1453// ExpandLibCall - Expand a node into a call to a libcall. If the result value 1454// does not fit into a register, return the lo part and set the hi part to the 1455// by-reg argument. If it does fit into a single register, return the result 1456// and leave the Hi part unset. 1457SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 1458 SDOperand &Hi) { 1459 SDNode *OutChain; 1460 SDOperand InChain = FindInputOutputChains(Node, OutChain, 1461 DAG.getEntryNode()); 1462 // TODO. Link in chains. 1463 1464 TargetLowering::ArgListTy Args; 1465 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1466 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 1467 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 1468 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy)); 1469 } 1470 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 1471 1472 // We don't care about token chains for libcalls. We just use the entry 1473 // node as our input and ignore the output chain. This allows us to place 1474 // calls wherever we need them to satisfy data dependences. 1475 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 1476 SDOperand Result = TLI.LowerCallTo(InChain, RetTy, false, Callee, 1477 Args, DAG).first; 1478 switch (getTypeAction(Result.getValueType())) { 1479 default: assert(0 && "Unknown thing"); 1480 case Legal: 1481 return Result; 1482 case Promote: 1483 assert(0 && "Cannot promote this yet!"); 1484 case Expand: 1485 SDOperand Lo; 1486 ExpandOp(Result, Lo, Hi); 1487 return Lo; 1488 } 1489} 1490 1491 1492/// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the 1493/// destination type is legal. 1494SDOperand SelectionDAGLegalize:: 1495ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 1496 assert(getTypeAction(DestTy) == Legal && "Destination type is not legal!"); 1497 assert(getTypeAction(Source.getValueType()) == Expand && 1498 "This is not an expansion!"); 1499 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 1500 1501 SDNode *OutChain; 1502 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain, 1503 DAG.getEntryNode()); 1504 1505 const char *FnName = 0; 1506 if (isSigned) { 1507 if (DestTy == MVT::f32) 1508 FnName = "__floatdisf"; 1509 else { 1510 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 1511 FnName = "__floatdidf"; 1512 } 1513 } else { 1514 // If this is unsigned, and not supported, first perform the conversion to 1515 // signed, then adjust the result if the sign bit is set. 1516 SDOperand SignedConv = ExpandIntToFP(false, DestTy, Source); 1517 1518 assert(0 && "Unsigned casts not supported yet!"); 1519 } 1520 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy()); 1521 1522 TargetLowering::ArgListTy Args; 1523 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType()); 1524 Args.push_back(std::make_pair(Source, ArgTy)); 1525 1526 // We don't care about token chains for libcalls. We just use the entry 1527 // node as our input and ignore the output chain. This allows us to place 1528 // calls wherever we need them to satisfy data dependences. 1529 const Type *RetTy = MVT::getTypeForValueType(DestTy); 1530 return TLI.LowerCallTo(InChain, RetTy, false, Callee, Args, DAG).first; 1531 1532} 1533 1534 1535 1536/// ExpandOp - Expand the specified SDOperand into its two component pieces 1537/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 1538/// LegalizeNodes map is filled in for any results that are not expanded, the 1539/// ExpandedNodes map is filled in for any results that are expanded, and the 1540/// Lo/Hi values are returned. 1541void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 1542 MVT::ValueType VT = Op.getValueType(); 1543 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 1544 SDNode *Node = Op.Val; 1545 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 1546 assert(MVT::isInteger(VT) && "Cannot expand FP values!"); 1547 assert(MVT::isInteger(NVT) && NVT < VT && 1548 "Cannot expand to FP value or to larger int value!"); 1549 1550 // If there is more than one use of this, see if we already expanded it. 1551 // There is no use remembering values that only have a single use, as the map 1552 // entries will never be reused. 1553 if (!Node->hasOneUse()) { 1554 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 1555 = ExpandedNodes.find(Op); 1556 if (I != ExpandedNodes.end()) { 1557 Lo = I->second.first; 1558 Hi = I->second.second; 1559 return; 1560 } 1561 } 1562 1563 // Expanding to multiple registers needs to perform an optimization step, and 1564 // is not careful to avoid operations the target does not support. Make sure 1565 // that all generated operations are legalized in the next iteration. 1566 NeedsAnotherIteration = true; 1567 1568 switch (Node->getOpcode()) { 1569 default: 1570 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 1571 assert(0 && "Do not know how to expand this operator!"); 1572 abort(); 1573 case ISD::Constant: { 1574 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 1575 Lo = DAG.getConstant(Cst, NVT); 1576 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 1577 break; 1578 } 1579 1580 case ISD::CopyFromReg: { 1581 unsigned Reg = cast<RegSDNode>(Node)->getReg(); 1582 // Aggregate register values are always in consequtive pairs. 1583 Lo = DAG.getCopyFromReg(Reg, NVT, Node->getOperand(0)); 1584 Hi = DAG.getCopyFromReg(Reg+1, NVT, Lo.getValue(1)); 1585 1586 // Remember that we legalized the chain. 1587 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 1588 1589 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!"); 1590 break; 1591 } 1592 1593 case ISD::BUILD_PAIR: 1594 // Legalize both operands. FIXME: in the future we should handle the case 1595 // where the two elements are not legal. 1596 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!"); 1597 Lo = LegalizeOp(Node->getOperand(0)); 1598 Hi = LegalizeOp(Node->getOperand(1)); 1599 break; 1600 1601 case ISD::LOAD: { 1602 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1603 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1604 Lo = DAG.getLoad(NVT, Ch, Ptr); 1605 1606 // Increment the pointer to the other half. 1607 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 1608 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 1609 getIntPtrConstant(IncrementSize)); 1610 Hi = DAG.getLoad(NVT, Ch, Ptr); 1611 1612 // Build a factor node to remember that this load is independent of the 1613 // other one. 1614 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 1615 Hi.getValue(1)); 1616 1617 // Remember that we legalized the chain. 1618 AddLegalizedOperand(Op.getValue(1), TF); 1619 if (!TLI.isLittleEndian()) 1620 std::swap(Lo, Hi); 1621 break; 1622 } 1623 case ISD::CALL: { 1624 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1625 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 1626 1627 bool Changed = false; 1628 std::vector<SDOperand> Ops; 1629 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 1630 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1631 Changed |= Ops.back() != Node->getOperand(i); 1632 } 1633 1634 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 1635 "Can only expand a call once so far, not i64 -> i16!"); 1636 1637 std::vector<MVT::ValueType> RetTyVTs; 1638 RetTyVTs.reserve(3); 1639 RetTyVTs.push_back(NVT); 1640 RetTyVTs.push_back(NVT); 1641 RetTyVTs.push_back(MVT::Other); 1642 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee, Ops); 1643 Lo = SDOperand(NC, 0); 1644 Hi = SDOperand(NC, 1); 1645 1646 // Insert the new chain mapping. 1647 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2)); 1648 break; 1649 } 1650 case ISD::AND: 1651 case ISD::OR: 1652 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 1653 SDOperand LL, LH, RL, RH; 1654 ExpandOp(Node->getOperand(0), LL, LH); 1655 ExpandOp(Node->getOperand(1), RL, RH); 1656 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 1657 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 1658 break; 1659 } 1660 case ISD::SELECT: { 1661 SDOperand C, LL, LH, RL, RH; 1662 1663 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1664 case Expand: assert(0 && "It's impossible to expand bools"); 1665 case Legal: 1666 C = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 1667 break; 1668 case Promote: 1669 C = PromoteOp(Node->getOperand(0)); // Promote the condition. 1670 break; 1671 } 1672 ExpandOp(Node->getOperand(1), LL, LH); 1673 ExpandOp(Node->getOperand(2), RL, RH); 1674 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL); 1675 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH); 1676 break; 1677 } 1678 case ISD::SIGN_EXTEND: { 1679 // The low part is just a sign extension of the input (which degenerates to 1680 // a copy). 1681 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, LegalizeOp(Node->getOperand(0))); 1682 1683 // The high part is obtained by SRA'ing all but one of the bits of the lo 1684 // part. 1685 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 1686 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 1687 TLI.getShiftAmountTy())); 1688 break; 1689 } 1690 case ISD::ZERO_EXTEND: 1691 // The low part is just a zero extension of the input (which degenerates to 1692 // a copy). 1693 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, LegalizeOp(Node->getOperand(0))); 1694 1695 // The high part is just a zero. 1696 Hi = DAG.getConstant(0, NVT); 1697 break; 1698 1699 // These operators cannot be expanded directly, emit them as calls to 1700 // library functions. 1701 case ISD::FP_TO_SINT: 1702 if (Node->getOperand(0).getValueType() == MVT::f32) 1703 Lo = ExpandLibCall("__fixsfdi", Node, Hi); 1704 else 1705 Lo = ExpandLibCall("__fixdfdi", Node, Hi); 1706 break; 1707 case ISD::FP_TO_UINT: 1708 if (Node->getOperand(0).getValueType() == MVT::f32) 1709 Lo = ExpandLibCall("__fixunssfdi", Node, Hi); 1710 else 1711 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi); 1712 break; 1713 1714 case ISD::SHL: 1715 // If we can emit an efficient shift operation, do so now. 1716 if (ExpandShift(ISD::SHL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 1717 break; 1718 // Otherwise, emit a libcall. 1719 Lo = ExpandLibCall("__ashldi3", Node, Hi); 1720 break; 1721 1722 case ISD::SRA: 1723 // If we can emit an efficient shift operation, do so now. 1724 if (ExpandShift(ISD::SRA, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 1725 break; 1726 // Otherwise, emit a libcall. 1727 Lo = ExpandLibCall("__ashrdi3", Node, Hi); 1728 break; 1729 case ISD::SRL: 1730 // If we can emit an efficient shift operation, do so now. 1731 if (ExpandShift(ISD::SRL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 1732 break; 1733 // Otherwise, emit a libcall. 1734 Lo = ExpandLibCall("__lshrdi3", Node, Hi); 1735 break; 1736 1737 case ISD::ADD: 1738 ExpandAddSub(true, Node->getOperand(0), Node->getOperand(1), Lo, Hi); 1739 break; 1740 case ISD::SUB: 1741 ExpandAddSub(false, Node->getOperand(0), Node->getOperand(1), Lo, Hi); 1742 break; 1743 case ISD::MUL: Lo = ExpandLibCall("__muldi3" , Node, Hi); break; 1744 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break; 1745 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break; 1746 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break; 1747 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break; 1748 } 1749 1750 // Remember in a map if the values will be reused later. 1751 if (!Node->hasOneUse()) { 1752 bool isNew = ExpandedNodes.insert(std::make_pair(Op, 1753 std::make_pair(Lo, Hi))).second; 1754 assert(isNew && "Value already expanded?!?"); 1755 } 1756} 1757 1758 1759// SelectionDAG::Legalize - This is the entry point for the file. 1760// 1761void SelectionDAG::Legalize() { 1762 /// run - This is the main entry point to this class. 1763 /// 1764 SelectionDAGLegalize(*this).Run(); 1765} 1766 1767