LegalizeDAG.cpp revision de387ce81024f9be0ca523e9487b1aafeb95fa22
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/Support/MathExtras.h" 18#include "llvm/Target/TargetLowering.h" 19#include "llvm/Target/TargetData.h" 20#include "llvm/Target/TargetOptions.h" 21#include "llvm/CallingConv.h" 22#include "llvm/Constants.h" 23#include <iostream> 24#include <set> 25using namespace llvm; 26 27//===----------------------------------------------------------------------===// 28/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 29/// hacks on it until the target machine can handle it. This involves 30/// eliminating value sizes the machine cannot handle (promoting small sizes to 31/// large sizes or splitting up large values into small values) as well as 32/// eliminating operations the machine cannot handle. 33/// 34/// This code also does a small amount of optimization and recognition of idioms 35/// as part of its processing. For example, if a target does not support a 36/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 37/// will attempt merge setcc and brc instructions into brcc's. 38/// 39namespace { 40class SelectionDAGLegalize { 41 TargetLowering &TLI; 42 SelectionDAG &DAG; 43 44 /// LegalizeAction - This enum indicates what action we should take for each 45 /// value type the can occur in the program. 46 enum LegalizeAction { 47 Legal, // The target natively supports this value type. 48 Promote, // This should be promoted to the next larger type. 49 Expand, // This integer type should be broken into smaller pieces. 50 }; 51 52 /// ValueTypeActions - This is a bitvector that contains two bits for each 53 /// value type, where the two bits correspond to the LegalizeAction enum. 54 /// This can be queried with "getTypeAction(VT)". 55 unsigned long long ValueTypeActions; 56 57 /// NeedsAnotherIteration - This is set when we expand a large integer 58 /// operation into smaller integer operations, but the smaller operations are 59 /// not set. This occurs only rarely in practice, for targets that don't have 60 /// 32-bit or larger integer registers. 61 bool NeedsAnotherIteration; 62 63 /// LegalizedNodes - For nodes that are of legal width, and that have more 64 /// than one use, this map indicates what regularized operand to use. This 65 /// allows us to avoid legalizing the same thing more than once. 66 std::map<SDOperand, SDOperand> LegalizedNodes; 67 68 /// PromotedNodes - For nodes that are below legal width, and that have more 69 /// than one use, this map indicates what promoted value to use. This allows 70 /// us to avoid promoting the same thing more than once. 71 std::map<SDOperand, SDOperand> PromotedNodes; 72 73 /// ExpandedNodes - For nodes that need to be expanded, and which have more 74 /// than one use, this map indicates which which operands are the expanded 75 /// version of the input. This allows us to avoid expanding the same node 76 /// more than once. 77 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 78 79 void AddLegalizedOperand(SDOperand From, SDOperand To) { 80 LegalizedNodes.insert(std::make_pair(From, To)); 81 // If someone requests legalization of the new node, return itself. 82 if (From != To) 83 LegalizedNodes.insert(std::make_pair(To, To)); 84 } 85 void AddPromotedOperand(SDOperand From, SDOperand To) { 86 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 87 assert(isNew && "Got into the map somehow?"); 88 // If someone requests legalization of the new node, return itself. 89 LegalizedNodes.insert(std::make_pair(To, To)); 90 } 91 92public: 93 94 SelectionDAGLegalize(SelectionDAG &DAG); 95 96 /// Run - While there is still lowering to do, perform a pass over the DAG. 97 /// Most regularization can be done in a single pass, but targets that require 98 /// large values to be split into registers multiple times (e.g. i64 -> 4x 99 /// i16) require iteration for these values (the first iteration will demote 100 /// to i32, the second will demote to i16). 101 void Run() { 102 do { 103 NeedsAnotherIteration = false; 104 LegalizeDAG(); 105 } while (NeedsAnotherIteration); 106 } 107 108 /// getTypeAction - Return how we should legalize values of this type, either 109 /// it is already legal or we need to expand it into multiple registers of 110 /// smaller integer type, or we need to promote it to a larger type. 111 LegalizeAction getTypeAction(MVT::ValueType VT) const { 112 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3); 113 } 114 115 /// isTypeLegal - Return true if this type is legal on this target. 116 /// 117 bool isTypeLegal(MVT::ValueType VT) const { 118 return getTypeAction(VT) == Legal; 119 } 120 121private: 122 void LegalizeDAG(); 123 124 SDOperand LegalizeOp(SDOperand O); 125 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 126 SDOperand PromoteOp(SDOperand O); 127 128 SDOperand ExpandLibCall(const char *Name, SDNode *Node, 129 SDOperand &Hi); 130 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 131 SDOperand Source); 132 133 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp); 134 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 135 SDOperand LegalOp, 136 MVT::ValueType DestVT); 137 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 138 bool isSigned); 139 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 140 bool isSigned); 141 142 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 143 SDOperand &Lo, SDOperand &Hi); 144 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 145 SDOperand &Lo, SDOperand &Hi); 146 void ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 147 SDOperand &Lo, SDOperand &Hi); 148 149 void SpliceCallInto(const SDOperand &CallResult, SDNode *OutChain); 150 151 SDOperand getIntPtrConstant(uint64_t Val) { 152 return DAG.getConstant(Val, TLI.getPointerTy()); 153 } 154}; 155} 156 157static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) { 158 switch (VecOp) { 159 default: assert(0 && "Don't know how to scalarize this opcode!"); 160 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD; 161 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB; 162 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL; 163 } 164} 165 166SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 167 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 168 ValueTypeActions(TLI.getValueTypeActions()) { 169 assert(MVT::LAST_VALUETYPE <= 32 && 170 "Too many value types for ValueTypeActions to hold!"); 171} 172 173/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 174/// INT_TO_FP operation of the specified operand when the target requests that 175/// we expand it. At this point, we know that the result and operand types are 176/// legal for the target. 177SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 178 SDOperand Op0, 179 MVT::ValueType DestVT) { 180 if (Op0.getValueType() == MVT::i32) { 181 // simple 32-bit [signed|unsigned] integer to float/double expansion 182 183 // get the stack frame index of a 8 byte buffer 184 MachineFunction &MF = DAG.getMachineFunction(); 185 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 186 // get address of 8 byte buffer 187 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 188 // word offset constant for Hi/Lo address computation 189 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 190 // set up Hi and Lo (into buffer) address based on endian 191 SDOperand Hi, Lo; 192 if (TLI.isLittleEndian()) { 193 Hi = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff); 194 Lo = StackSlot; 195 } else { 196 Hi = StackSlot; 197 Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff); 198 } 199 // if signed map to unsigned space 200 SDOperand Op0Mapped; 201 if (isSigned) { 202 // constant used to invert sign bit (signed to unsigned mapping) 203 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 204 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 205 } else { 206 Op0Mapped = Op0; 207 } 208 // store the lo of the constructed double - based on integer input 209 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 210 Op0Mapped, Lo, DAG.getSrcValue(NULL)); 211 // initial hi portion of constructed double 212 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 213 // store the hi of the constructed double - biased exponent 214 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1, 215 InitialHi, Hi, DAG.getSrcValue(NULL)); 216 // load the constructed double 217 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, 218 DAG.getSrcValue(NULL)); 219 // FP constant to bias correct the final result 220 SDOperand Bias = DAG.getConstantFP(isSigned ? 221 BitsToDouble(0x4330000080000000ULL) 222 : BitsToDouble(0x4330000000000000ULL), 223 MVT::f64); 224 // subtract the bias 225 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 226 // final result 227 SDOperand Result; 228 // handle final rounding 229 if (DestVT == MVT::f64) { 230 // do nothing 231 Result = Sub; 232 } else { 233 // if f32 then cast to f32 234 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub); 235 } 236 return LegalizeOp(Result); 237 } 238 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 239 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 240 241 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 242 DAG.getConstant(0, Op0.getValueType()), 243 ISD::SETLT); 244 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 245 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 246 SignSet, Four, Zero); 247 248 // If the sign bit of the integer is set, the large number will be treated 249 // as a negative number. To counteract this, the dynamic code adds an 250 // offset depending on the data type. 251 uint64_t FF; 252 switch (Op0.getValueType()) { 253 default: assert(0 && "Unsupported integer type!"); 254 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 255 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 256 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 257 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 258 } 259 if (TLI.isLittleEndian()) FF <<= 32; 260 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 261 262 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 263 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 264 SDOperand FudgeInReg; 265 if (DestVT == MVT::f32) 266 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 267 DAG.getSrcValue(NULL)); 268 else { 269 assert(DestVT == MVT::f64 && "Unexpected conversion"); 270 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, 271 DAG.getEntryNode(), CPIdx, 272 DAG.getSrcValue(NULL), MVT::f32)); 273 } 274 275 return LegalizeOp(DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg)); 276} 277 278/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 279/// *INT_TO_FP operation of the specified operand when the target requests that 280/// we promote it. At this point, we know that the result and operand types are 281/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 282/// operation that takes a larger input. 283SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 284 MVT::ValueType DestVT, 285 bool isSigned) { 286 // First step, figure out the appropriate *INT_TO_FP operation to use. 287 MVT::ValueType NewInTy = LegalOp.getValueType(); 288 289 unsigned OpToUse = 0; 290 291 // Scan for the appropriate larger type to use. 292 while (1) { 293 NewInTy = (MVT::ValueType)(NewInTy+1); 294 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 295 296 // If the target supports SINT_TO_FP of this type, use it. 297 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 298 default: break; 299 case TargetLowering::Legal: 300 if (!TLI.isTypeLegal(NewInTy)) 301 break; // Can't use this datatype. 302 // FALL THROUGH. 303 case TargetLowering::Custom: 304 OpToUse = ISD::SINT_TO_FP; 305 break; 306 } 307 if (OpToUse) break; 308 if (isSigned) continue; 309 310 // If the target supports UINT_TO_FP of this type, use it. 311 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 312 default: break; 313 case TargetLowering::Legal: 314 if (!TLI.isTypeLegal(NewInTy)) 315 break; // Can't use this datatype. 316 // FALL THROUGH. 317 case TargetLowering::Custom: 318 OpToUse = ISD::UINT_TO_FP; 319 break; 320 } 321 if (OpToUse) break; 322 323 // Otherwise, try a larger type. 324 } 325 326 // Okay, we found the operation and type to use. Zero extend our input to the 327 // desired type then run the operation on it. 328 SDOperand N = DAG.getNode(OpToUse, DestVT, 329 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 330 NewInTy, LegalOp)); 331 // Make sure to legalize any nodes we create here. 332 return LegalizeOp(N); 333} 334 335/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 336/// FP_TO_*INT operation of the specified operand when the target requests that 337/// we promote it. At this point, we know that the result and operand types are 338/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 339/// operation that returns a larger result. 340SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 341 MVT::ValueType DestVT, 342 bool isSigned) { 343 // First step, figure out the appropriate FP_TO*INT operation to use. 344 MVT::ValueType NewOutTy = DestVT; 345 346 unsigned OpToUse = 0; 347 348 // Scan for the appropriate larger type to use. 349 while (1) { 350 NewOutTy = (MVT::ValueType)(NewOutTy+1); 351 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 352 353 // If the target supports FP_TO_SINT returning this type, use it. 354 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 355 default: break; 356 case TargetLowering::Legal: 357 if (!TLI.isTypeLegal(NewOutTy)) 358 break; // Can't use this datatype. 359 // FALL THROUGH. 360 case TargetLowering::Custom: 361 OpToUse = ISD::FP_TO_SINT; 362 break; 363 } 364 if (OpToUse) break; 365 366 // If the target supports FP_TO_UINT of this type, use it. 367 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 368 default: break; 369 case TargetLowering::Legal: 370 if (!TLI.isTypeLegal(NewOutTy)) 371 break; // Can't use this datatype. 372 // FALL THROUGH. 373 case TargetLowering::Custom: 374 OpToUse = ISD::FP_TO_UINT; 375 break; 376 } 377 if (OpToUse) break; 378 379 // Otherwise, try a larger type. 380 } 381 382 // Okay, we found the operation and type to use. Truncate the result of the 383 // extended FP_TO_*INT operation to the desired size. 384 SDOperand N = DAG.getNode(ISD::TRUNCATE, DestVT, 385 DAG.getNode(OpToUse, NewOutTy, LegalOp)); 386 // Make sure to legalize any nodes we create here in the next pass. 387 return LegalizeOp(N); 388} 389 390/// ComputeTopDownOrdering - Add the specified node to the Order list if it has 391/// not been visited yet and if all of its operands have already been visited. 392static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order, 393 std::map<SDNode*, unsigned> &Visited) { 394 if (++Visited[N] != N->getNumOperands()) 395 return; // Haven't visited all operands yet 396 397 Order.push_back(N); 398 399 if (N->hasOneUse()) { // Tail recurse in common case. 400 ComputeTopDownOrdering(*N->use_begin(), Order, Visited); 401 return; 402 } 403 404 // Now that we have N in, add anything that uses it if all of their operands 405 // are now done. 406 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI) 407 ComputeTopDownOrdering(*UI, Order, Visited); 408} 409 410 411void SelectionDAGLegalize::LegalizeDAG() { 412 // The legalize process is inherently a bottom-up recursive process (users 413 // legalize their uses before themselves). Given infinite stack space, we 414 // could just start legalizing on the root and traverse the whole graph. In 415 // practice however, this causes us to run out of stack space on large basic 416 // blocks. To avoid this problem, compute an ordering of the nodes where each 417 // node is only legalized after all of its operands are legalized. 418 std::map<SDNode*, unsigned> Visited; 419 std::vector<SDNode*> Order; 420 421 // Compute ordering from all of the leaves in the graphs, those (like the 422 // entry node) that have no operands. 423 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 424 E = DAG.allnodes_end(); I != E; ++I) { 425 if (I->getNumOperands() == 0) { 426 Visited[I] = 0 - 1U; 427 ComputeTopDownOrdering(I, Order, Visited); 428 } 429 } 430 431 assert(Order.size() == Visited.size() && 432 Order.size() == 433 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 434 "Error: DAG is cyclic!"); 435 Visited.clear(); 436 437 for (unsigned i = 0, e = Order.size(); i != e; ++i) { 438 SDNode *N = Order[i]; 439 switch (getTypeAction(N->getValueType(0))) { 440 default: assert(0 && "Bad type action!"); 441 case Legal: 442 LegalizeOp(SDOperand(N, 0)); 443 break; 444 case Promote: 445 PromoteOp(SDOperand(N, 0)); 446 break; 447 case Expand: { 448 SDOperand X, Y; 449 ExpandOp(SDOperand(N, 0), X, Y); 450 break; 451 } 452 } 453 } 454 455 // Finally, it's possible the root changed. Get the new root. 456 SDOperand OldRoot = DAG.getRoot(); 457 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 458 DAG.setRoot(LegalizedNodes[OldRoot]); 459 460 ExpandedNodes.clear(); 461 LegalizedNodes.clear(); 462 PromotedNodes.clear(); 463 464 // Remove dead nodes now. 465 DAG.RemoveDeadNodes(OldRoot.Val); 466} 467 468SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 469 assert(isTypeLegal(Op.getValueType()) && 470 "Caller should expand or promote operands that are not legal!"); 471 SDNode *Node = Op.Val; 472 473 // If this operation defines any values that cannot be represented in a 474 // register on this target, make sure to expand or promote them. 475 if (Node->getNumValues() > 1) { 476 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 477 switch (getTypeAction(Node->getValueType(i))) { 478 case Legal: break; // Nothing to do. 479 case Expand: { 480 SDOperand T1, T2; 481 ExpandOp(Op.getValue(i), T1, T2); 482 assert(LegalizedNodes.count(Op) && 483 "Expansion didn't add legal operands!"); 484 return LegalizedNodes[Op]; 485 } 486 case Promote: 487 PromoteOp(Op.getValue(i)); 488 assert(LegalizedNodes.count(Op) && 489 "Expansion didn't add legal operands!"); 490 return LegalizedNodes[Op]; 491 } 492 } 493 494 // Note that LegalizeOp may be reentered even from single-use nodes, which 495 // means that we always must cache transformed nodes. 496 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 497 if (I != LegalizedNodes.end()) return I->second; 498 499 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 500 501 SDOperand Result = Op; 502 503 switch (Node->getOpcode()) { 504 default: 505 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 506 // If this is a target node, legalize it by legalizing the operands then 507 // passing it through. 508 std::vector<SDOperand> Ops; 509 bool Changed = false; 510 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 511 Ops.push_back(LegalizeOp(Node->getOperand(i))); 512 Changed = Changed || Node->getOperand(i) != Ops.back(); 513 } 514 if (Changed) 515 if (Node->getNumValues() == 1) 516 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops); 517 else { 518 std::vector<MVT::ValueType> VTs(Node->value_begin(), 519 Node->value_end()); 520 Result = DAG.getNode(Node->getOpcode(), VTs, Ops); 521 } 522 523 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 524 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 525 return Result.getValue(Op.ResNo); 526 } 527 // Otherwise this is an unhandled builtin node. splat. 528 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 529 assert(0 && "Do not know how to legalize this operator!"); 530 abort(); 531 case ISD::EntryToken: 532 case ISD::FrameIndex: 533 case ISD::TargetFrameIndex: 534 case ISD::Register: 535 case ISD::TargetConstant: 536 case ISD::TargetConstantPool: 537 case ISD::GlobalAddress: 538 case ISD::TargetGlobalAddress: 539 case ISD::ExternalSymbol: 540 case ISD::TargetExternalSymbol: 541 case ISD::ConstantPool: // Nothing to do. 542 case ISD::BasicBlock: 543 case ISD::CONDCODE: 544 case ISD::VALUETYPE: 545 case ISD::SRCVALUE: 546 case ISD::STRING: 547 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 548 default: assert(0 && "This action is not supported yet!"); 549 case TargetLowering::Custom: { 550 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 551 if (Tmp.Val) { 552 Result = LegalizeOp(Tmp); 553 break; 554 } 555 } // FALLTHROUGH if the target doesn't want to lower this op after all. 556 case TargetLowering::Legal: 557 assert(isTypeLegal(Node->getValueType(0)) && "This must be legal!"); 558 break; 559 } 560 break; 561 case ISD::AssertSext: 562 case ISD::AssertZext: 563 Tmp1 = LegalizeOp(Node->getOperand(0)); 564 if (Tmp1 != Node->getOperand(0)) 565 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 566 Node->getOperand(1)); 567 break; 568 case ISD::MERGE_VALUES: 569 return LegalizeOp(Node->getOperand(Op.ResNo)); 570 case ISD::CopyFromReg: 571 Tmp1 = LegalizeOp(Node->getOperand(0)); 572 Result = Op.getValue(0); 573 if (Node->getNumValues() == 2) { 574 if (Tmp1 != Node->getOperand(0)) 575 Result = DAG.getCopyFromReg(Tmp1, 576 cast<RegisterSDNode>(Node->getOperand(1))->getReg(), 577 Node->getValueType(0)); 578 } else { 579 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 580 if (Node->getNumOperands() == 3) 581 Tmp2 = LegalizeOp(Node->getOperand(2)); 582 if (Tmp1 != Node->getOperand(0) || 583 (Node->getNumOperands() == 3 && Tmp2 != Node->getOperand(2))) 584 Result = DAG.getCopyFromReg(Tmp1, 585 cast<RegisterSDNode>(Node->getOperand(1))->getReg(), 586 Node->getValueType(0), Tmp2); 587 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 588 } 589 // Since CopyFromReg produces two values, make sure to remember that we 590 // legalized both of them. 591 AddLegalizedOperand(Op.getValue(0), Result); 592 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 593 return Result.getValue(Op.ResNo); 594 case ISD::UNDEF: { 595 MVT::ValueType VT = Op.getValueType(); 596 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 597 default: assert(0 && "This action is not supported yet!"); 598 case TargetLowering::Expand: 599 case TargetLowering::Promote: 600 if (MVT::isInteger(VT)) 601 Result = DAG.getConstant(0, VT); 602 else if (MVT::isFloatingPoint(VT)) 603 Result = DAG.getConstantFP(0, VT); 604 else 605 assert(0 && "Unknown value type!"); 606 break; 607 case TargetLowering::Legal: 608 break; 609 } 610 break; 611 } 612 613 case ISD::LOCATION: 614 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 615 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 616 617 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 618 case TargetLowering::Promote: 619 default: assert(0 && "This action is not supported yet!"); 620 case TargetLowering::Expand: { 621 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo(); 622 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 623 bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other); 624 625 if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) { 626 const std::string &FName = 627 cast<StringSDNode>(Node->getOperand(3))->getValue(); 628 const std::string &DirName = 629 cast<StringSDNode>(Node->getOperand(4))->getValue(); 630 unsigned SrcFile = DebugInfo->getUniqueSourceID(FName, DirName); 631 632 std::vector<SDOperand> Ops; 633 Ops.push_back(Tmp1); // chain 634 SDOperand LineOp = Node->getOperand(1); 635 SDOperand ColOp = Node->getOperand(2); 636 637 if (useDEBUG_LOC) { 638 Ops.push_back(LineOp); // line # 639 Ops.push_back(ColOp); // col # 640 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id 641 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops); 642 } else { 643 unsigned Line = dyn_cast<ConstantSDNode>(LineOp)->getValue(); 644 unsigned Col = dyn_cast<ConstantSDNode>(ColOp)->getValue(); 645 unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile); 646 Ops.push_back(DAG.getConstant(ID, MVT::i32)); 647 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops); 648 } 649 } else { 650 Result = Tmp1; // chain 651 } 652 Result = LegalizeOp(Result); // Relegalize new nodes. 653 break; 654 } 655 case TargetLowering::Legal: 656 if (Tmp1 != Node->getOperand(0) || 657 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 658 std::vector<SDOperand> Ops; 659 Ops.push_back(Tmp1); 660 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 661 Ops.push_back(Node->getOperand(1)); // line # must be legal. 662 Ops.push_back(Node->getOperand(2)); // col # must be legal. 663 } else { 664 // Otherwise promote them. 665 Ops.push_back(PromoteOp(Node->getOperand(1))); 666 Ops.push_back(PromoteOp(Node->getOperand(2))); 667 } 668 Ops.push_back(Node->getOperand(3)); // filename must be legal. 669 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 670 Result = DAG.getNode(ISD::LOCATION, MVT::Other, Ops); 671 } 672 break; 673 } 674 break; 675 676 case ISD::DEBUG_LOC: 677 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 678 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 679 case TargetLowering::Promote: 680 case TargetLowering::Expand: 681 default: assert(0 && "This action is not supported yet!"); 682 case TargetLowering::Legal: 683 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 684 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 685 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 686 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 687 688 if (Tmp1 != Node->getOperand(0) || 689 Tmp2 != Node->getOperand(1) || 690 Tmp3 != Node->getOperand(2) || 691 Tmp4 != Node->getOperand(3)) { 692 Result = DAG.getNode(ISD::DEBUG_LOC,MVT::Other, Tmp1, Tmp2, Tmp3, Tmp4); 693 } 694 break; 695 } 696 break; 697 698 case ISD::DEBUG_LABEL: 699 assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!"); 700 switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) { 701 case TargetLowering::Promote: 702 case TargetLowering::Expand: 703 default: assert(0 && "This action is not supported yet!"); 704 case TargetLowering::Legal: 705 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 706 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id. 707 708 if (Tmp1 != Node->getOperand(0) || 709 Tmp2 != Node->getOperand(1)) { 710 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Tmp1, Tmp2); 711 } 712 break; 713 } 714 break; 715 716 case ISD::Constant: 717 // We know we don't need to expand constants here, constants only have one 718 // value and we check that it is fine above. 719 720 // FIXME: Maybe we should handle things like targets that don't support full 721 // 32-bit immediates? 722 break; 723 case ISD::ConstantFP: { 724 // Spill FP immediates to the constant pool if the target cannot directly 725 // codegen them. Targets often have some immediate values that can be 726 // efficiently generated into an FP register without a load. We explicitly 727 // leave these constants as ConstantFP nodes for the target to deal with. 728 729 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 730 731 // Check to see if this FP immediate is already legal. 732 bool isLegal = false; 733 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 734 E = TLI.legal_fpimm_end(); I != E; ++I) 735 if (CFP->isExactlyValue(*I)) { 736 isLegal = true; 737 break; 738 } 739 740 if (!isLegal) { 741 // Otherwise we need to spill the constant to memory. 742 bool Extend = false; 743 744 // If a FP immediate is precise when represented as a float, we put it 745 // into the constant pool as a float, even if it's is statically typed 746 // as a double. 747 MVT::ValueType VT = CFP->getValueType(0); 748 bool isDouble = VT == MVT::f64; 749 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 750 Type::FloatTy, CFP->getValue()); 751 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) && 752 // Only do this if the target has a native EXTLOAD instruction from 753 // f32. 754 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) { 755 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy)); 756 VT = MVT::f32; 757 Extend = true; 758 } 759 760 SDOperand CPIdx = 761 LegalizeOp(DAG.getConstantPool(LLVMC, TLI.getPointerTy())); 762 if (Extend) { 763 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 764 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 765 } else { 766 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 767 DAG.getSrcValue(NULL)); 768 } 769 } 770 break; 771 } 772 case ISD::ConstantVec: { 773 // We assume that vector constants are not legal, and will be immediately 774 // spilled to the constant pool. 775 // 776 // FIXME: revisit this when we have some kind of mechanism by which targets 777 // can decided legality of vector constants, of which there may be very 778 // many. 779 // 780 // Create a ConstantPacked, and put it in the constant pool. 781 std::vector<Constant*> CV; 782 MVT::ValueType VT = Node->getValueType(0); 783 for (unsigned I = 0, E = Node->getNumOperands(); I < E; ++I) { 784 SDOperand OpN = Node->getOperand(I); 785 const Type* OpNTy = MVT::getTypeForValueType(OpN.getValueType()); 786 if (MVT::isFloatingPoint(VT)) 787 CV.push_back(ConstantFP::get(OpNTy, 788 cast<ConstantFPSDNode>(OpN)->getValue())); 789 else 790 CV.push_back(ConstantUInt::get(OpNTy, 791 cast<ConstantSDNode>(OpN)->getValue())); 792 } 793 Constant *CP = ConstantPacked::get(CV); 794 SDOperand CPIdx = LegalizeOp(DAG.getConstantPool(CP, TLI.getPointerTy())); 795 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL)); 796 break; 797 } 798 case ISD::TokenFactor: 799 if (Node->getNumOperands() == 2) { 800 bool Changed = false; 801 SDOperand Op0 = LegalizeOp(Node->getOperand(0)); 802 SDOperand Op1 = LegalizeOp(Node->getOperand(1)); 803 if (Op0 != Node->getOperand(0) || Op1 != Node->getOperand(1)) 804 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Op0, Op1); 805 } else { 806 std::vector<SDOperand> Ops; 807 bool Changed = false; 808 // Legalize the operands. 809 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 810 SDOperand Op = Node->getOperand(i); 811 Ops.push_back(LegalizeOp(Op)); 812 Changed |= Ops[i] != Op; 813 } 814 if (Changed) 815 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 816 } 817 break; 818 819 case ISD::CALLSEQ_START: 820 case ISD::CALLSEQ_END: 821 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 822 // Do not try to legalize the target-specific arguments (#1+) 823 Tmp2 = Node->getOperand(0); 824 if (Tmp1 != Tmp2) 825 Node->setAdjCallChain(Tmp1); 826 827 // Note that we do not create new CALLSEQ_DOWN/UP nodes here. These 828 // nodes are treated specially and are mutated in place. This makes the dag 829 // legalization process more efficient and also makes libcall insertion 830 // easier. 831 break; 832 case ISD::DYNAMIC_STACKALLOC: 833 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 834 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 835 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 836 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 837 Tmp3 != Node->getOperand(2)) { 838 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 839 std::vector<SDOperand> Ops; 840 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 841 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops); 842 } else 843 Result = Op.getValue(0); 844 845 // Since this op produces two values, make sure to remember that we 846 // legalized both of them. 847 AddLegalizedOperand(SDOperand(Node, 0), Result); 848 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 849 return Result.getValue(Op.ResNo); 850 851 case ISD::TAILCALL: 852 case ISD::CALL: { 853 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 854 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 855 856 bool Changed = false; 857 std::vector<SDOperand> Ops; 858 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 859 Ops.push_back(LegalizeOp(Node->getOperand(i))); 860 Changed |= Ops.back() != Node->getOperand(i); 861 } 862 863 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || Changed) { 864 std::vector<MVT::ValueType> RetTyVTs; 865 RetTyVTs.reserve(Node->getNumValues()); 866 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 867 RetTyVTs.push_back(Node->getValueType(i)); 868 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops, 869 Node->getOpcode() == ISD::TAILCALL), 0); 870 } else { 871 Result = Result.getValue(0); 872 } 873 // Since calls produce multiple values, make sure to remember that we 874 // legalized all of them. 875 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 876 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 877 return Result.getValue(Op.ResNo); 878 } 879 case ISD::BR: 880 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 881 if (Tmp1 != Node->getOperand(0)) 882 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1)); 883 break; 884 885 case ISD::BRCOND: 886 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 887 888 switch (getTypeAction(Node->getOperand(1).getValueType())) { 889 case Expand: assert(0 && "It's impossible to expand bools"); 890 case Legal: 891 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 892 break; 893 case Promote: 894 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 895 break; 896 } 897 898 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 899 default: assert(0 && "This action is not supported yet!"); 900 case TargetLowering::Expand: 901 // Expand brcond's setcc into its constituent parts and create a BR_CC 902 // Node. 903 if (Tmp2.getOpcode() == ISD::SETCC) { 904 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 905 Tmp2.getOperand(0), Tmp2.getOperand(1), 906 Node->getOperand(2)); 907 } else { 908 // Make sure the condition is either zero or one. It may have been 909 // promoted from something else. 910 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 911 912 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 913 DAG.getCondCode(ISD::SETNE), Tmp2, 914 DAG.getConstant(0, Tmp2.getValueType()), 915 Node->getOperand(2)); 916 } 917 Result = LegalizeOp(Result); // Relegalize new nodes. 918 break; 919 case TargetLowering::Custom: { 920 SDOperand Tmp = 921 TLI.LowerOperation(DAG.getNode(ISD::BRCOND, Node->getValueType(0), 922 Tmp1, Tmp2, Node->getOperand(2)), DAG); 923 if (Tmp.Val) { 924 Result = LegalizeOp(Tmp); 925 break; 926 } 927 // FALLTHROUGH if the target thinks it is legal. 928 } 929 case TargetLowering::Legal: 930 // Basic block destination (Op#2) is always legal. 931 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 932 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 933 Node->getOperand(2)); 934 break; 935 } 936 break; 937 case ISD::BR_CC: 938 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 939 if (!isTypeLegal(Node->getOperand(2).getValueType())) { 940 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 941 Node->getOperand(2), // LHS 942 Node->getOperand(3), // RHS 943 Node->getOperand(1))); 944 // If we get a SETCC back from legalizing the SETCC node we just 945 // created, then use its LHS, RHS, and CC directly in creating a new 946 // node. Otherwise, select between the true and false value based on 947 // comparing the result of the legalized with zero. 948 if (Tmp2.getOpcode() == ISD::SETCC) { 949 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 950 Tmp2.getOperand(0), Tmp2.getOperand(1), 951 Node->getOperand(4)); 952 } else { 953 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 954 DAG.getCondCode(ISD::SETNE), 955 Tmp2, DAG.getConstant(0, Tmp2.getValueType()), 956 Node->getOperand(4)); 957 } 958 break; 959 } 960 961 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS 962 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS 963 964 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 965 default: assert(0 && "Unexpected action for BR_CC!"); 966 case TargetLowering::Custom: { 967 Tmp4 = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1), 968 Tmp2, Tmp3, Node->getOperand(4)); 969 Tmp4 = TLI.LowerOperation(Tmp4, DAG); 970 if (Tmp4.Val) { 971 Result = LegalizeOp(Tmp4); 972 break; 973 } 974 } // FALLTHROUGH if the target doesn't want to lower this op after all. 975 case TargetLowering::Legal: 976 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 977 Tmp3 != Node->getOperand(3)) { 978 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1), 979 Tmp2, Tmp3, Node->getOperand(4)); 980 } 981 break; 982 } 983 break; 984 case ISD::BRCONDTWOWAY: 985 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 986 switch (getTypeAction(Node->getOperand(1).getValueType())) { 987 case Expand: assert(0 && "It's impossible to expand bools"); 988 case Legal: 989 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 990 break; 991 case Promote: 992 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 993 break; 994 } 995 // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR 996 // pair. 997 switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) { 998 case TargetLowering::Promote: 999 default: assert(0 && "This action is not supported yet!"); 1000 case TargetLowering::Legal: 1001 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 1002 std::vector<SDOperand> Ops; 1003 Ops.push_back(Tmp1); 1004 Ops.push_back(Tmp2); 1005 Ops.push_back(Node->getOperand(2)); 1006 Ops.push_back(Node->getOperand(3)); 1007 Result = DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops); 1008 } 1009 break; 1010 case TargetLowering::Expand: 1011 // If BRTWOWAY_CC is legal for this target, then simply expand this node 1012 // to that. Otherwise, skip BRTWOWAY_CC and expand directly to a 1013 // BRCOND/BR pair. 1014 if (TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) { 1015 if (Tmp2.getOpcode() == ISD::SETCC) { 1016 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2), 1017 Tmp2.getOperand(0), Tmp2.getOperand(1), 1018 Node->getOperand(2), Node->getOperand(3)); 1019 } else { 1020 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2, 1021 DAG.getConstant(0, Tmp2.getValueType()), 1022 Node->getOperand(2), Node->getOperand(3)); 1023 } 1024 } else { 1025 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 1026 Node->getOperand(2)); 1027 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3)); 1028 } 1029 Result = LegalizeOp(Result); // Relegalize new nodes. 1030 break; 1031 } 1032 break; 1033 case ISD::BRTWOWAY_CC: 1034 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1035 if (isTypeLegal(Node->getOperand(2).getValueType())) { 1036 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS 1037 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS 1038 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 1039 Tmp3 != Node->getOperand(3)) { 1040 Result = DAG.getBR2Way_CC(Tmp1, Node->getOperand(1), Tmp2, Tmp3, 1041 Node->getOperand(4), Node->getOperand(5)); 1042 } 1043 break; 1044 } else { 1045 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 1046 Node->getOperand(2), // LHS 1047 Node->getOperand(3), // RHS 1048 Node->getOperand(1))); 1049 // If this target does not support BRTWOWAY_CC, lower it to a BRCOND/BR 1050 // pair. 1051 switch (TLI.getOperationAction(ISD::BRTWOWAY_CC, MVT::Other)) { 1052 default: assert(0 && "This action is not supported yet!"); 1053 case TargetLowering::Legal: 1054 // If we get a SETCC back from legalizing the SETCC node we just 1055 // created, then use its LHS, RHS, and CC directly in creating a new 1056 // node. Otherwise, select between the true and false value based on 1057 // comparing the result of the legalized with zero. 1058 if (Tmp2.getOpcode() == ISD::SETCC) { 1059 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2), 1060 Tmp2.getOperand(0), Tmp2.getOperand(1), 1061 Node->getOperand(4), Node->getOperand(5)); 1062 } else { 1063 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2, 1064 DAG.getConstant(0, Tmp2.getValueType()), 1065 Node->getOperand(4), Node->getOperand(5)); 1066 } 1067 break; 1068 case TargetLowering::Expand: 1069 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 1070 Node->getOperand(4)); 1071 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(5)); 1072 break; 1073 } 1074 Result = LegalizeOp(Result); // Relegalize new nodes. 1075 } 1076 break; 1077 case ISD::LOAD: { 1078 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1079 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1080 1081 MVT::ValueType VT = Node->getValueType(0); 1082 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1083 default: assert(0 && "This action is not supported yet!"); 1084 case TargetLowering::Custom: { 1085 SDOperand Op = DAG.getLoad(Node->getValueType(0), 1086 Tmp1, Tmp2, Node->getOperand(2)); 1087 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 1088 if (Tmp.Val) { 1089 Result = LegalizeOp(Tmp); 1090 // Since loads produce two values, make sure to remember that we legalized 1091 // both of them. 1092 AddLegalizedOperand(SDOperand(Node, 0), Result); 1093 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1094 return Result.getValue(Op.ResNo); 1095 } 1096 // FALLTHROUGH if the target thinks it is legal. 1097 } 1098 case TargetLowering::Legal: 1099 if (Tmp1 != Node->getOperand(0) || 1100 Tmp2 != Node->getOperand(1)) 1101 Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2, 1102 Node->getOperand(2)); 1103 else 1104 Result = SDOperand(Node, 0); 1105 1106 // Since loads produce two values, make sure to remember that we legalized 1107 // both of them. 1108 AddLegalizedOperand(SDOperand(Node, 0), Result); 1109 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1110 return Result.getValue(Op.ResNo); 1111 } 1112 assert(0 && "Unreachable"); 1113 } 1114 case ISD::EXTLOAD: 1115 case ISD::SEXTLOAD: 1116 case ISD::ZEXTLOAD: { 1117 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1118 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1119 1120 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 1121 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) { 1122 default: assert(0 && "This action is not supported yet!"); 1123 case TargetLowering::Promote: 1124 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!"); 1125 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0), 1126 Tmp1, Tmp2, Node->getOperand(2), MVT::i8); 1127 // Since loads produce two values, make sure to remember that we legalized 1128 // both of them. 1129 AddLegalizedOperand(SDOperand(Node, 0), Result); 1130 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1131 return Result.getValue(Op.ResNo); 1132 1133 case TargetLowering::Custom: { 1134 SDOperand Op = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0), 1135 Tmp1, Tmp2, Node->getOperand(2), 1136 SrcVT); 1137 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 1138 if (Tmp.Val) { 1139 Result = LegalizeOp(Tmp); 1140 // Since loads produce two values, make sure to remember that we legalized 1141 // both of them. 1142 AddLegalizedOperand(SDOperand(Node, 0), Result); 1143 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1144 return Result.getValue(Op.ResNo); 1145 } 1146 // FALLTHROUGH if the target thinks it is legal. 1147 } 1148 case TargetLowering::Legal: 1149 if (Tmp1 != Node->getOperand(0) || 1150 Tmp2 != Node->getOperand(1)) 1151 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0), 1152 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 1153 else 1154 Result = SDOperand(Node, 0); 1155 1156 // Since loads produce two values, make sure to remember that we legalized 1157 // both of them. 1158 AddLegalizedOperand(SDOperand(Node, 0), Result); 1159 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1160 return Result.getValue(Op.ResNo); 1161 case TargetLowering::Expand: 1162 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1163 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 1164 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2)); 1165 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 1166 Result = LegalizeOp(Result); // Relegalize new nodes. 1167 Load = LegalizeOp(Load); 1168 AddLegalizedOperand(SDOperand(Node, 0), Result); 1169 AddLegalizedOperand(SDOperand(Node, 1), Load.getValue(1)); 1170 if (Op.ResNo) 1171 return Load.getValue(1); 1172 return Result; 1173 } 1174 assert(Node->getOpcode() != ISD::EXTLOAD && 1175 "EXTLOAD should always be supported!"); 1176 // Turn the unsupported load into an EXTLOAD followed by an explicit 1177 // zero/sign extend inreg. 1178 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 1179 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 1180 SDOperand ValRes; 1181 if (Node->getOpcode() == ISD::SEXTLOAD) 1182 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1183 Result, DAG.getValueType(SrcVT)); 1184 else 1185 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 1186 Result = LegalizeOp(Result); // Relegalize new nodes. 1187 ValRes = LegalizeOp(ValRes); // Relegalize new nodes. 1188 AddLegalizedOperand(SDOperand(Node, 0), ValRes); 1189 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1190 if (Op.ResNo) 1191 return Result.getValue(1); 1192 return ValRes; 1193 } 1194 assert(0 && "Unreachable"); 1195 } 1196 case ISD::EXTRACT_ELEMENT: { 1197 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 1198 switch (getTypeAction(OpTy)) { 1199 default: 1200 assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 1201 break; 1202 case Legal: 1203 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 1204 // 1 -> Hi 1205 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 1206 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 1207 TLI.getShiftAmountTy())); 1208 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 1209 } else { 1210 // 0 -> Lo 1211 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 1212 Node->getOperand(0)); 1213 } 1214 Result = LegalizeOp(Result); 1215 break; 1216 case Expand: 1217 // Get both the low and high parts. 1218 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1219 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 1220 Result = Tmp2; // 1 -> Hi 1221 else 1222 Result = Tmp1; // 0 -> Lo 1223 break; 1224 } 1225 break; 1226 } 1227 1228 case ISD::CopyToReg: 1229 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1230 1231 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 1232 "Register type must be legal!"); 1233 // Legalize the incoming value (must be a legal type). 1234 Tmp2 = LegalizeOp(Node->getOperand(2)); 1235 if (Node->getNumValues() == 1) { 1236 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2)) 1237 Result = DAG.getNode(ISD::CopyToReg, MVT::Other, Tmp1, 1238 Node->getOperand(1), Tmp2); 1239 } else { 1240 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 1241 if (Node->getNumOperands() == 4) 1242 Tmp3 = LegalizeOp(Node->getOperand(3)); 1243 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 1244 (Node->getNumOperands() == 4 && Tmp3 != Node->getOperand(3))) { 1245 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 1246 Result = DAG.getCopyToReg(Tmp1, Reg, Tmp2, Tmp3); 1247 } 1248 1249 // Since this produces two values, make sure to remember that we legalized 1250 // both of them. 1251 AddLegalizedOperand(SDOperand(Node, 0), Result); 1252 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1253 return Result.getValue(Op.ResNo); 1254 } 1255 break; 1256 1257 case ISD::RET: 1258 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1259 switch (Node->getNumOperands()) { 1260 case 2: // ret val 1261 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1262 case Legal: 1263 Tmp2 = LegalizeOp(Node->getOperand(1)); 1264 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1265 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 1266 break; 1267 case Expand: { 1268 SDOperand Lo, Hi; 1269 ExpandOp(Node->getOperand(1), Lo, Hi); 1270 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi); 1271 break; 1272 } 1273 case Promote: 1274 Tmp2 = PromoteOp(Node->getOperand(1)); 1275 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 1276 break; 1277 } 1278 break; 1279 case 1: // ret void 1280 if (Tmp1 != Node->getOperand(0)) 1281 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1); 1282 break; 1283 default: { // ret <values> 1284 std::vector<SDOperand> NewValues; 1285 NewValues.push_back(Tmp1); 1286 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) 1287 switch (getTypeAction(Node->getOperand(i).getValueType())) { 1288 case Legal: 1289 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 1290 break; 1291 case Expand: { 1292 SDOperand Lo, Hi; 1293 ExpandOp(Node->getOperand(i), Lo, Hi); 1294 NewValues.push_back(Lo); 1295 NewValues.push_back(Hi); 1296 break; 1297 } 1298 case Promote: 1299 assert(0 && "Can't promote multiple return value yet!"); 1300 } 1301 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues); 1302 break; 1303 } 1304 } 1305 1306 switch (TLI.getOperationAction(Node->getOpcode(), 1307 Node->getValueType(0))) { 1308 default: assert(0 && "This action is not supported yet!"); 1309 case TargetLowering::Custom: { 1310 SDOperand Tmp = TLI.LowerOperation(Result, DAG); 1311 if (Tmp.Val) { 1312 Result = LegalizeOp(Tmp); 1313 break; 1314 } 1315 // FALLTHROUGH if the target thinks it is legal. 1316 } 1317 case TargetLowering::Legal: 1318 // Nothing to do. 1319 break; 1320 } 1321 break; 1322 case ISD::STORE: { 1323 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1324 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1325 1326 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 1327 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){ 1328 if (CFP->getValueType(0) == MVT::f32) { 1329 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 1330 DAG.getConstant(FloatToBits(CFP->getValue()), 1331 MVT::i32), 1332 Tmp2, 1333 Node->getOperand(3)); 1334 } else { 1335 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 1336 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 1337 DAG.getConstant(DoubleToBits(CFP->getValue()), 1338 MVT::i64), 1339 Tmp2, 1340 Node->getOperand(3)); 1341 } 1342 Node = Result.Val; 1343 } 1344 1345 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1346 case Legal: { 1347 SDOperand Val = LegalizeOp(Node->getOperand(1)); 1348 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) || 1349 Tmp2 != Node->getOperand(2)) 1350 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2, 1351 Node->getOperand(3)); 1352 1353 MVT::ValueType VT = Result.Val->getOperand(1).getValueType(); 1354 switch (TLI.getOperationAction(Result.Val->getOpcode(), VT)) { 1355 default: assert(0 && "This action is not supported yet!"); 1356 case TargetLowering::Custom: { 1357 SDOperand Tmp = TLI.LowerOperation(Result, DAG); 1358 if (Tmp.Val) { 1359 Result = LegalizeOp(Tmp); 1360 break; 1361 } 1362 // FALLTHROUGH if the target thinks it is legal. 1363 } 1364 case TargetLowering::Legal: 1365 // Nothing to do. 1366 break; 1367 } 1368 break; 1369 } 1370 case Promote: 1371 // Truncate the value and store the result. 1372 Tmp3 = PromoteOp(Node->getOperand(1)); 1373 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2, 1374 Node->getOperand(3), 1375 DAG.getValueType(Node->getOperand(1).getValueType())); 1376 break; 1377 1378 case Expand: 1379 SDOperand Lo, Hi; 1380 unsigned IncrementSize; 1381 ExpandOp(Node->getOperand(1), Lo, Hi); 1382 1383 if (!TLI.isLittleEndian()) 1384 std::swap(Lo, Hi); 1385 1386 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2, 1387 Node->getOperand(3)); 1388 // If this is a vector type, then we have to calculate the increment as 1389 // the product of the element size in bytes, and the number of elements 1390 // in the high half of the vector. 1391 if (MVT::Vector == Hi.getValueType()) { 1392 unsigned NumElems = cast<ConstantSDNode>(Hi.getOperand(2))->getValue(); 1393 MVT::ValueType EVT = cast<VTSDNode>(Hi.getOperand(3))->getVT(); 1394 IncrementSize = NumElems * MVT::getSizeInBits(EVT)/8; 1395 } else { 1396 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8; 1397 } 1398 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 1399 getIntPtrConstant(IncrementSize)); 1400 assert(isTypeLegal(Tmp2.getValueType()) && 1401 "Pointers must be legal!"); 1402 //Again, claiming both parts of the store came form the same Instr 1403 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2, 1404 Node->getOperand(3)); 1405 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 1406 break; 1407 } 1408 break; 1409 } 1410 case ISD::PCMARKER: 1411 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1412 if (Tmp1 != Node->getOperand(0)) 1413 Result = DAG.getNode(ISD::PCMARKER, MVT::Other, Tmp1,Node->getOperand(1)); 1414 break; 1415 case ISD::READCYCLECOUNTER: 1416 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 1417 if (Tmp1 != Node->getOperand(0)) { 1418 std::vector<MVT::ValueType> rtypes; 1419 std::vector<SDOperand> rvals; 1420 rtypes.push_back(MVT::i64); 1421 rtypes.push_back(MVT::Other); 1422 rvals.push_back(Tmp1); 1423 Result = DAG.getNode(ISD::READCYCLECOUNTER, rtypes, rvals); 1424 } 1425 1426 // Since rdcc produce two values, make sure to remember that we legalized 1427 // both of them. 1428 AddLegalizedOperand(SDOperand(Node, 0), Result); 1429 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1430 return Result.getValue(Op.ResNo); 1431 1432 case ISD::TRUNCSTORE: { 1433 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1434 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1435 1436 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1437 case Promote: 1438 case Expand: 1439 assert(0 && "Cannot handle illegal TRUNCSTORE yet!"); 1440 case Legal: 1441 Tmp2 = LegalizeOp(Node->getOperand(1)); 1442 1443 // The only promote case we handle is TRUNCSTORE:i1 X into 1444 // -> TRUNCSTORE:i8 (and X, 1) 1445 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 && 1446 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) == 1447 TargetLowering::Promote) { 1448 // Promote the bool to a mask then store. 1449 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2, 1450 DAG.getConstant(1, Tmp2.getValueType())); 1451 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 1452 Node->getOperand(3), DAG.getValueType(MVT::i8)); 1453 1454 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1455 Tmp3 != Node->getOperand(2)) { 1456 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 1457 Node->getOperand(3), Node->getOperand(4)); 1458 } 1459 1460 MVT::ValueType StVT = cast<VTSDNode>(Result.Val->getOperand(4))->getVT(); 1461 switch (TLI.getOperationAction(Result.Val->getOpcode(), StVT)) { 1462 default: assert(0 && "This action is not supported yet!"); 1463 case TargetLowering::Custom: { 1464 SDOperand Tmp = TLI.LowerOperation(Result, DAG); 1465 if (Tmp.Val) { 1466 Result = LegalizeOp(Tmp); 1467 break; 1468 } 1469 // FALLTHROUGH if the target thinks it is legal. 1470 } 1471 case TargetLowering::Legal: 1472 // Nothing to do. 1473 break; 1474 } 1475 break; 1476 } 1477 break; 1478 } 1479 case ISD::SELECT: 1480 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1481 case Expand: assert(0 && "It's impossible to expand bools"); 1482 case Legal: 1483 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 1484 break; 1485 case Promote: 1486 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 1487 break; 1488 } 1489 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 1490 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 1491 1492 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 1493 default: assert(0 && "This action is not supported yet!"); 1494 case TargetLowering::Expand: 1495 if (Tmp1.getOpcode() == ISD::SETCC) { 1496 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 1497 Tmp2, Tmp3, 1498 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 1499 } else { 1500 // Make sure the condition is either zero or one. It may have been 1501 // promoted from something else. 1502 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 1503 Result = DAG.getSelectCC(Tmp1, 1504 DAG.getConstant(0, Tmp1.getValueType()), 1505 Tmp2, Tmp3, ISD::SETNE); 1506 } 1507 Result = LegalizeOp(Result); // Relegalize new nodes. 1508 break; 1509 case TargetLowering::Custom: { 1510 SDOperand Tmp = 1511 TLI.LowerOperation(DAG.getNode(ISD::SELECT, Node->getValueType(0), 1512 Tmp1, Tmp2, Tmp3), DAG); 1513 if (Tmp.Val) { 1514 Result = LegalizeOp(Tmp); 1515 break; 1516 } 1517 // FALLTHROUGH if the target thinks it is legal. 1518 } 1519 case TargetLowering::Legal: 1520 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1521 Tmp3 != Node->getOperand(2)) 1522 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0), 1523 Tmp1, Tmp2, Tmp3); 1524 break; 1525 case TargetLowering::Promote: { 1526 MVT::ValueType NVT = 1527 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 1528 unsigned ExtOp, TruncOp; 1529 if (MVT::isInteger(Tmp2.getValueType())) { 1530 ExtOp = ISD::ANY_EXTEND; 1531 TruncOp = ISD::TRUNCATE; 1532 } else { 1533 ExtOp = ISD::FP_EXTEND; 1534 TruncOp = ISD::FP_ROUND; 1535 } 1536 // Promote each of the values to the new type. 1537 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 1538 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 1539 // Perform the larger operation, then round down. 1540 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 1541 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 1542 break; 1543 } 1544 } 1545 break; 1546 case ISD::SELECT_CC: 1547 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 1548 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 1549 1550 if (isTypeLegal(Node->getOperand(0).getValueType())) { 1551 // Everything is legal, see if we should expand this op or something. 1552 switch (TLI.getOperationAction(ISD::SELECT_CC, 1553 Node->getOperand(0).getValueType())) { 1554 default: assert(0 && "This action is not supported yet!"); 1555 case TargetLowering::Custom: { 1556 SDOperand Tmp = 1557 TLI.LowerOperation(DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), 1558 Node->getOperand(0), 1559 Node->getOperand(1), Tmp3, Tmp4, 1560 Node->getOperand(4)), DAG); 1561 if (Tmp.Val) { 1562 Result = LegalizeOp(Tmp); 1563 break; 1564 } 1565 } // FALLTHROUGH if the target can't lower this operation after all. 1566 case TargetLowering::Legal: 1567 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1568 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1569 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1570 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3)) { 1571 Result = DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), Tmp1,Tmp2, 1572 Tmp3, Tmp4, Node->getOperand(4)); 1573 } 1574 break; 1575 } 1576 break; 1577 } else { 1578 Tmp1 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 1579 Node->getOperand(0), // LHS 1580 Node->getOperand(1), // RHS 1581 Node->getOperand(4))); 1582 // If we get a SETCC back from legalizing the SETCC node we just 1583 // created, then use its LHS, RHS, and CC directly in creating a new 1584 // node. Otherwise, select between the true and false value based on 1585 // comparing the result of the legalized with zero. 1586 if (Tmp1.getOpcode() == ISD::SETCC) { 1587 Result = DAG.getNode(ISD::SELECT_CC, Tmp3.getValueType(), 1588 Tmp1.getOperand(0), Tmp1.getOperand(1), 1589 Tmp3, Tmp4, Tmp1.getOperand(2)); 1590 } else { 1591 Result = DAG.getSelectCC(Tmp1, 1592 DAG.getConstant(0, Tmp1.getValueType()), 1593 Tmp3, Tmp4, ISD::SETNE); 1594 } 1595 } 1596 break; 1597 case ISD::SETCC: 1598 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1599 case Legal: 1600 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1601 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1602 break; 1603 case Promote: 1604 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS 1605 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS 1606 1607 // If this is an FP compare, the operands have already been extended. 1608 if (MVT::isInteger(Node->getOperand(0).getValueType())) { 1609 MVT::ValueType VT = Node->getOperand(0).getValueType(); 1610 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 1611 1612 // Otherwise, we have to insert explicit sign or zero extends. Note 1613 // that we could insert sign extends for ALL conditions, but zero extend 1614 // is cheaper on many machines (an AND instead of two shifts), so prefer 1615 // it. 1616 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1617 default: assert(0 && "Unknown integer comparison!"); 1618 case ISD::SETEQ: 1619 case ISD::SETNE: 1620 case ISD::SETUGE: 1621 case ISD::SETUGT: 1622 case ISD::SETULE: 1623 case ISD::SETULT: 1624 // ALL of these operations will work if we either sign or zero extend 1625 // the operands (including the unsigned comparisons!). Zero extend is 1626 // usually a simpler/cheaper operation, so prefer it. 1627 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 1628 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 1629 break; 1630 case ISD::SETGE: 1631 case ISD::SETGT: 1632 case ISD::SETLT: 1633 case ISD::SETLE: 1634 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 1635 DAG.getValueType(VT)); 1636 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 1637 DAG.getValueType(VT)); 1638 break; 1639 } 1640 } 1641 break; 1642 case Expand: 1643 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 1644 ExpandOp(Node->getOperand(0), LHSLo, LHSHi); 1645 ExpandOp(Node->getOperand(1), RHSLo, RHSHi); 1646 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1647 case ISD::SETEQ: 1648 case ISD::SETNE: 1649 if (RHSLo == RHSHi) 1650 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 1651 if (RHSCST->isAllOnesValue()) { 1652 // Comparison to -1. 1653 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 1654 Tmp2 = RHSLo; 1655 break; 1656 } 1657 1658 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 1659 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 1660 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 1661 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 1662 break; 1663 default: 1664 // If this is a comparison of the sign bit, just look at the top part. 1665 // X > -1, x < 0 1666 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1))) 1667 if ((cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETLT && 1668 CST->getValue() == 0) || // X < 0 1669 (cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETGT && 1670 (CST->isAllOnesValue()))) { // X > -1 1671 Tmp1 = LHSHi; 1672 Tmp2 = RHSHi; 1673 break; 1674 } 1675 1676 // FIXME: This generated code sucks. 1677 ISD::CondCode LowCC; 1678 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1679 default: assert(0 && "Unknown integer setcc!"); 1680 case ISD::SETLT: 1681 case ISD::SETULT: LowCC = ISD::SETULT; break; 1682 case ISD::SETGT: 1683 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 1684 case ISD::SETLE: 1685 case ISD::SETULE: LowCC = ISD::SETULE; break; 1686 case ISD::SETGE: 1687 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 1688 } 1689 1690 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 1691 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 1692 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 1693 1694 // NOTE: on targets without efficient SELECT of bools, we can always use 1695 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 1696 Tmp1 = DAG.getSetCC(Node->getValueType(0), LHSLo, RHSLo, LowCC); 1697 Tmp2 = DAG.getNode(ISD::SETCC, Node->getValueType(0), LHSHi, RHSHi, 1698 Node->getOperand(2)); 1699 Result = DAG.getSetCC(Node->getValueType(0), LHSHi, RHSHi, ISD::SETEQ); 1700 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 1701 Result, Tmp1, Tmp2)); 1702 AddLegalizedOperand(SDOperand(Node, 0), Result); 1703 return Result; 1704 } 1705 } 1706 1707 switch(TLI.getOperationAction(ISD::SETCC, 1708 Node->getOperand(0).getValueType())) { 1709 default: 1710 assert(0 && "Cannot handle this action for SETCC yet!"); 1711 break; 1712 case TargetLowering::Promote: { 1713 // First step, figure out the appropriate operation to use. 1714 // Allow SETCC to not be supported for all legal data types 1715 // Mostly this targets FP 1716 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 1717 MVT::ValueType OldVT = NewInTy; 1718 1719 // Scan for the appropriate larger type to use. 1720 while (1) { 1721 NewInTy = (MVT::ValueType)(NewInTy+1); 1722 1723 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 1724 "Fell off of the edge of the integer world"); 1725 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 1726 "Fell off of the edge of the floating point world"); 1727 1728 // If the target supports SETCC of this type, use it. 1729 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 1730 break; 1731 } 1732 if (MVT::isInteger(NewInTy)) 1733 assert(0 && "Cannot promote Legal Integer SETCC yet"); 1734 else { 1735 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 1736 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 1737 } 1738 1739 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2, 1740 Node->getOperand(2)); 1741 break; 1742 } 1743 case TargetLowering::Custom: { 1744 SDOperand Tmp = 1745 TLI.LowerOperation(DAG.getNode(ISD::SETCC, Node->getValueType(0), 1746 Tmp1, Tmp2, Node->getOperand(2)), DAG); 1747 if (Tmp.Val) { 1748 Result = LegalizeOp(Tmp); 1749 break; 1750 } 1751 // FALLTHROUGH if the target thinks it is legal. 1752 } 1753 case TargetLowering::Legal: 1754 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1755 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2, 1756 Node->getOperand(2)); 1757 break; 1758 case TargetLowering::Expand: 1759 // Expand a setcc node into a select_cc of the same condition, lhs, and 1760 // rhs that selects between const 1 (true) and const 0 (false). 1761 MVT::ValueType VT = Node->getValueType(0); 1762 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 1763 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 1764 Node->getOperand(2)); 1765 Result = LegalizeOp(Result); 1766 break; 1767 } 1768 break; 1769 1770 case ISD::MEMSET: 1771 case ISD::MEMCPY: 1772 case ISD::MEMMOVE: { 1773 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 1774 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 1775 1776 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 1777 switch (getTypeAction(Node->getOperand(2).getValueType())) { 1778 case Expand: assert(0 && "Cannot expand a byte!"); 1779 case Legal: 1780 Tmp3 = LegalizeOp(Node->getOperand(2)); 1781 break; 1782 case Promote: 1783 Tmp3 = PromoteOp(Node->getOperand(2)); 1784 break; 1785 } 1786 } else { 1787 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 1788 } 1789 1790 SDOperand Tmp4; 1791 switch (getTypeAction(Node->getOperand(3).getValueType())) { 1792 case Expand: { 1793 // Length is too big, just take the lo-part of the length. 1794 SDOperand HiPart; 1795 ExpandOp(Node->getOperand(3), HiPart, Tmp4); 1796 break; 1797 } 1798 case Legal: 1799 Tmp4 = LegalizeOp(Node->getOperand(3)); 1800 break; 1801 case Promote: 1802 Tmp4 = PromoteOp(Node->getOperand(3)); 1803 break; 1804 } 1805 1806 SDOperand Tmp5; 1807 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 1808 case Expand: assert(0 && "Cannot expand this yet!"); 1809 case Legal: 1810 Tmp5 = LegalizeOp(Node->getOperand(4)); 1811 break; 1812 case Promote: 1813 Tmp5 = PromoteOp(Node->getOperand(4)); 1814 break; 1815 } 1816 1817 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 1818 default: assert(0 && "This action not implemented for this operation!"); 1819 case TargetLowering::Custom: { 1820 SDOperand Tmp = 1821 TLI.LowerOperation(DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, 1822 Tmp2, Tmp3, Tmp4, Tmp5), DAG); 1823 if (Tmp.Val) { 1824 Result = LegalizeOp(Tmp); 1825 break; 1826 } 1827 // FALLTHROUGH if the target thinks it is legal. 1828 } 1829 case TargetLowering::Legal: 1830 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1831 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) || 1832 Tmp5 != Node->getOperand(4)) { 1833 std::vector<SDOperand> Ops; 1834 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 1835 Ops.push_back(Tmp4); Ops.push_back(Tmp5); 1836 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops); 1837 } 1838 break; 1839 case TargetLowering::Expand: { 1840 // Otherwise, the target does not support this operation. Lower the 1841 // operation to an explicit libcall as appropriate. 1842 MVT::ValueType IntPtr = TLI.getPointerTy(); 1843 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType(); 1844 std::vector<std::pair<SDOperand, const Type*> > Args; 1845 1846 const char *FnName = 0; 1847 if (Node->getOpcode() == ISD::MEMSET) { 1848 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1849 // Extend the ubyte argument to be an int value for the call. 1850 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 1851 Args.push_back(std::make_pair(Tmp3, Type::IntTy)); 1852 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1853 1854 FnName = "memset"; 1855 } else if (Node->getOpcode() == ISD::MEMCPY || 1856 Node->getOpcode() == ISD::MEMMOVE) { 1857 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1858 Args.push_back(std::make_pair(Tmp3, IntPtrTy)); 1859 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1860 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 1861 } else { 1862 assert(0 && "Unknown op!"); 1863 } 1864 1865 std::pair<SDOperand,SDOperand> CallResult = 1866 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false, 1867 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 1868 Result = LegalizeOp(CallResult.second); 1869 break; 1870 } 1871 } 1872 break; 1873 } 1874 1875 case ISD::READPORT: 1876 Tmp1 = LegalizeOp(Node->getOperand(0)); 1877 Tmp2 = LegalizeOp(Node->getOperand(1)); 1878 1879 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 1880 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1881 std::vector<SDOperand> Ops; 1882 Ops.push_back(Tmp1); 1883 Ops.push_back(Tmp2); 1884 Result = DAG.getNode(ISD::READPORT, VTs, Ops); 1885 } else 1886 Result = SDOperand(Node, 0); 1887 // Since these produce two values, make sure to remember that we legalized 1888 // both of them. 1889 AddLegalizedOperand(SDOperand(Node, 0), Result); 1890 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1891 return Result.getValue(Op.ResNo); 1892 case ISD::WRITEPORT: 1893 Tmp1 = LegalizeOp(Node->getOperand(0)); 1894 Tmp2 = LegalizeOp(Node->getOperand(1)); 1895 Tmp3 = LegalizeOp(Node->getOperand(2)); 1896 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1897 Tmp3 != Node->getOperand(2)) 1898 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3); 1899 break; 1900 1901 case ISD::READIO: 1902 Tmp1 = LegalizeOp(Node->getOperand(0)); 1903 Tmp2 = LegalizeOp(Node->getOperand(1)); 1904 1905 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1906 case TargetLowering::Custom: 1907 default: assert(0 && "This action not implemented for this operation!"); 1908 case TargetLowering::Legal: 1909 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 1910 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1911 std::vector<SDOperand> Ops; 1912 Ops.push_back(Tmp1); 1913 Ops.push_back(Tmp2); 1914 Result = DAG.getNode(ISD::READPORT, VTs, Ops); 1915 } else 1916 Result = SDOperand(Node, 0); 1917 break; 1918 case TargetLowering::Expand: 1919 // Replace this with a load from memory. 1920 Result = DAG.getLoad(Node->getValueType(0), Node->getOperand(0), 1921 Node->getOperand(1), DAG.getSrcValue(NULL)); 1922 Result = LegalizeOp(Result); 1923 break; 1924 } 1925 1926 // Since these produce two values, make sure to remember that we legalized 1927 // both of them. 1928 AddLegalizedOperand(SDOperand(Node, 0), Result); 1929 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1930 return Result.getValue(Op.ResNo); 1931 1932 case ISD::WRITEIO: 1933 Tmp1 = LegalizeOp(Node->getOperand(0)); 1934 Tmp2 = LegalizeOp(Node->getOperand(1)); 1935 Tmp3 = LegalizeOp(Node->getOperand(2)); 1936 1937 switch (TLI.getOperationAction(Node->getOpcode(), 1938 Node->getOperand(1).getValueType())) { 1939 case TargetLowering::Custom: 1940 default: assert(0 && "This action not implemented for this operation!"); 1941 case TargetLowering::Legal: 1942 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1943 Tmp3 != Node->getOperand(2)) 1944 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3); 1945 break; 1946 case TargetLowering::Expand: 1947 // Replace this with a store to memory. 1948 Result = DAG.getNode(ISD::STORE, MVT::Other, Node->getOperand(0), 1949 Node->getOperand(1), Node->getOperand(2), 1950 DAG.getSrcValue(NULL)); 1951 Result = LegalizeOp(Result); 1952 break; 1953 } 1954 break; 1955 1956 case ISD::ADD_PARTS: 1957 case ISD::SUB_PARTS: 1958 case ISD::SHL_PARTS: 1959 case ISD::SRA_PARTS: 1960 case ISD::SRL_PARTS: { 1961 std::vector<SDOperand> Ops; 1962 bool Changed = false; 1963 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1964 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1965 Changed |= Ops.back() != Node->getOperand(i); 1966 } 1967 if (Changed) { 1968 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1969 Result = DAG.getNode(Node->getOpcode(), VTs, Ops); 1970 } 1971 1972 switch (TLI.getOperationAction(Node->getOpcode(), 1973 Node->getValueType(0))) { 1974 default: assert(0 && "This action is not supported yet!"); 1975 case TargetLowering::Custom: { 1976 SDOperand Tmp = TLI.LowerOperation(Result, DAG); 1977 if (Tmp.Val) { 1978 SDOperand Tmp2, RetVal; 1979 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 1980 Tmp2 = LegalizeOp(Tmp.getValue(i)); 1981 AddLegalizedOperand(SDOperand(Node, i), Tmp2); 1982 if (i == Op.ResNo) 1983 RetVal = Tmp; 1984 } 1985 return RetVal; 1986 } 1987 // FALLTHROUGH if the target thinks it is legal. 1988 } 1989 case TargetLowering::Legal: 1990 // Nothing to do. 1991 break; 1992 } 1993 1994 // Since these produce multiple values, make sure to remember that we 1995 // legalized all of them. 1996 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 1997 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 1998 return Result.getValue(Op.ResNo); 1999 } 2000 2001 // Binary operators 2002 case ISD::ADD: 2003 case ISD::SUB: 2004 case ISD::MUL: 2005 case ISD::MULHS: 2006 case ISD::MULHU: 2007 case ISD::UDIV: 2008 case ISD::SDIV: 2009 case ISD::AND: 2010 case ISD::OR: 2011 case ISD::XOR: 2012 case ISD::SHL: 2013 case ISD::SRL: 2014 case ISD::SRA: 2015 case ISD::FADD: 2016 case ISD::FSUB: 2017 case ISD::FMUL: 2018 case ISD::FDIV: 2019 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2020 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2021 case Expand: assert(0 && "Not possible"); 2022 case Legal: 2023 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2024 break; 2025 case Promote: 2026 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2027 break; 2028 } 2029 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2030 case TargetLowering::Custom: { 2031 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, Tmp2); 2032 SDOperand Tmp = TLI.LowerOperation(Result, DAG); 2033 if (Tmp.Val) { 2034 Tmp = LegalizeOp(Tmp); // Relegalize input. 2035 AddLegalizedOperand(Op, Tmp); 2036 return Tmp; 2037 } //else it was considered legal and we fall through 2038 } 2039 case TargetLowering::Legal: 2040 if (Tmp1 != Node->getOperand(0) || 2041 Tmp2 != Node->getOperand(1)) 2042 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2); 2043 break; 2044 default: 2045 assert(0 && "Operation not supported"); 2046 } 2047 break; 2048 2049 case ISD::BUILD_PAIR: { 2050 MVT::ValueType PairTy = Node->getValueType(0); 2051 // TODO: handle the case where the Lo and Hi operands are not of legal type 2052 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 2053 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 2054 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 2055 case TargetLowering::Legal: 2056 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 2057 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 2058 break; 2059 case TargetLowering::Promote: 2060 case TargetLowering::Custom: 2061 assert(0 && "Cannot promote/custom this yet!"); 2062 case TargetLowering::Expand: 2063 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 2064 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 2065 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 2066 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 2067 TLI.getShiftAmountTy())); 2068 Result = LegalizeOp(DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2)); 2069 break; 2070 } 2071 break; 2072 } 2073 2074 case ISD::UREM: 2075 case ISD::SREM: 2076 case ISD::FREM: 2077 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2078 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2079 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2080 case TargetLowering::Custom: { 2081 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, Tmp2); 2082 SDOperand Tmp = TLI.LowerOperation(Result, DAG); 2083 if (Tmp.Val) { 2084 Tmp = LegalizeOp(Tmp); // Relegalize input. 2085 AddLegalizedOperand(Op, Tmp); 2086 return Tmp; 2087 } //else it was considered legal and we fall through 2088 } 2089 case TargetLowering::Legal: 2090 if (Tmp1 != Node->getOperand(0) || 2091 Tmp2 != Node->getOperand(1)) 2092 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 2093 Tmp2); 2094 break; 2095 case TargetLowering::Promote: 2096 assert(0 && "Cannot promote handle this yet!"); 2097 case TargetLowering::Expand: 2098 if (MVT::isInteger(Node->getValueType(0))) { 2099 MVT::ValueType VT = Node->getValueType(0); 2100 unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 2101 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2); 2102 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 2103 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 2104 } else { 2105 // Floating point mod -> fmod libcall. 2106 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod"; 2107 SDOperand Dummy; 2108 Result = ExpandLibCall(FnName, Node, Dummy); 2109 } 2110 break; 2111 } 2112 break; 2113 2114 case ISD::CTPOP: 2115 case ISD::CTTZ: 2116 case ISD::CTLZ: 2117 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 2118 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2119 case TargetLowering::Legal: 2120 if (Tmp1 != Node->getOperand(0)) 2121 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2122 break; 2123 case TargetLowering::Promote: { 2124 MVT::ValueType OVT = Tmp1.getValueType(); 2125 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2126 2127 // Zero extend the argument. 2128 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2129 // Perform the larger operation, then subtract if needed. 2130 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2131 switch(Node->getOpcode()) 2132 { 2133 case ISD::CTPOP: 2134 Result = Tmp1; 2135 break; 2136 case ISD::CTTZ: 2137 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 2138 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 2139 DAG.getConstant(getSizeInBits(NVT), NVT), 2140 ISD::SETEQ); 2141 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 2142 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1); 2143 break; 2144 case ISD::CTLZ: 2145 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2146 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 2147 DAG.getConstant(getSizeInBits(NVT) - 2148 getSizeInBits(OVT), NVT)); 2149 break; 2150 } 2151 break; 2152 } 2153 case TargetLowering::Custom: 2154 assert(0 && "Cannot custom handle this yet!"); 2155 case TargetLowering::Expand: 2156 switch(Node->getOpcode()) 2157 { 2158 case ISD::CTPOP: { 2159 static const uint64_t mask[6] = { 2160 0x5555555555555555ULL, 0x3333333333333333ULL, 2161 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 2162 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 2163 }; 2164 MVT::ValueType VT = Tmp1.getValueType(); 2165 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 2166 unsigned len = getSizeInBits(VT); 2167 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2168 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 2169 Tmp2 = DAG.getConstant(mask[i], VT); 2170 Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2171 Tmp1 = DAG.getNode(ISD::ADD, VT, 2172 DAG.getNode(ISD::AND, VT, Tmp1, Tmp2), 2173 DAG.getNode(ISD::AND, VT, 2174 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3), 2175 Tmp2)); 2176 } 2177 Result = Tmp1; 2178 break; 2179 } 2180 case ISD::CTLZ: { 2181 /* for now, we do this: 2182 x = x | (x >> 1); 2183 x = x | (x >> 2); 2184 ... 2185 x = x | (x >>16); 2186 x = x | (x >>32); // for 64-bit input 2187 return popcount(~x); 2188 2189 but see also: http://www.hackersdelight.org/HDcode/nlz.cc */ 2190 MVT::ValueType VT = Tmp1.getValueType(); 2191 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 2192 unsigned len = getSizeInBits(VT); 2193 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2194 Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2195 Tmp1 = DAG.getNode(ISD::OR, VT, Tmp1, 2196 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3)); 2197 } 2198 Tmp3 = DAG.getNode(ISD::XOR, VT, Tmp1, DAG.getConstant(~0ULL, VT)); 2199 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3)); 2200 break; 2201 } 2202 case ISD::CTTZ: { 2203 // for now, we use: { return popcount(~x & (x - 1)); } 2204 // unless the target has ctlz but not ctpop, in which case we use: 2205 // { return 32 - nlz(~x & (x-1)); } 2206 // see also http://www.hackersdelight.org/HDcode/ntz.cc 2207 MVT::ValueType VT = Tmp1.getValueType(); 2208 Tmp2 = DAG.getConstant(~0ULL, VT); 2209 Tmp3 = DAG.getNode(ISD::AND, VT, 2210 DAG.getNode(ISD::XOR, VT, Tmp1, Tmp2), 2211 DAG.getNode(ISD::SUB, VT, Tmp1, 2212 DAG.getConstant(1, VT))); 2213 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead 2214 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 2215 TLI.isOperationLegal(ISD::CTLZ, VT)) { 2216 Result = LegalizeOp(DAG.getNode(ISD::SUB, VT, 2217 DAG.getConstant(getSizeInBits(VT), VT), 2218 DAG.getNode(ISD::CTLZ, VT, Tmp3))); 2219 } else { 2220 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3)); 2221 } 2222 break; 2223 } 2224 default: 2225 assert(0 && "Cannot expand this yet!"); 2226 break; 2227 } 2228 break; 2229 } 2230 break; 2231 2232 // Unary operators 2233 case ISD::FABS: 2234 case ISD::FNEG: 2235 case ISD::FSQRT: 2236 case ISD::FSIN: 2237 case ISD::FCOS: 2238 Tmp1 = LegalizeOp(Node->getOperand(0)); 2239 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2240 case TargetLowering::Legal: 2241 if (Tmp1 != Node->getOperand(0)) 2242 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2243 break; 2244 case TargetLowering::Promote: 2245 case TargetLowering::Custom: 2246 assert(0 && "Cannot promote/custom handle this yet!"); 2247 case TargetLowering::Expand: 2248 switch(Node->getOpcode()) { 2249 case ISD::FNEG: { 2250 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2251 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2252 Result = LegalizeOp(DAG.getNode(ISD::FSUB, Node->getValueType(0), 2253 Tmp2, Tmp1)); 2254 break; 2255 } 2256 case ISD::FABS: { 2257 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2258 MVT::ValueType VT = Node->getValueType(0); 2259 Tmp2 = DAG.getConstantFP(0.0, VT); 2260 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 2261 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 2262 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 2263 Result = LegalizeOp(Result); 2264 break; 2265 } 2266 case ISD::FSQRT: 2267 case ISD::FSIN: 2268 case ISD::FCOS: { 2269 MVT::ValueType VT = Node->getValueType(0); 2270 const char *FnName = 0; 2271 switch(Node->getOpcode()) { 2272 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break; 2273 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break; 2274 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break; 2275 default: assert(0 && "Unreachable!"); 2276 } 2277 SDOperand Dummy; 2278 Result = ExpandLibCall(FnName, Node, Dummy); 2279 break; 2280 } 2281 default: 2282 assert(0 && "Unreachable!"); 2283 } 2284 break; 2285 } 2286 break; 2287 2288 case ISD::BIT_CONVERT: 2289 if (!isTypeLegal(Node->getOperand(0).getValueType())) 2290 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2291 else { 2292 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 2293 Node->getOperand(0).getValueType())) { 2294 default: assert(0 && "Unknown operation action!"); 2295 case TargetLowering::Expand: 2296 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2297 break; 2298 case TargetLowering::Legal: 2299 Tmp1 = LegalizeOp(Node->getOperand(0)); 2300 if (Tmp1 != Node->getOperand(0)) 2301 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Tmp1); 2302 break; 2303 } 2304 } 2305 break; 2306 // Conversion operators. The source and destination have different types. 2307 case ISD::SINT_TO_FP: 2308 case ISD::UINT_TO_FP: { 2309 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 2310 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2311 case Legal: 2312 switch (TLI.getOperationAction(Node->getOpcode(), 2313 Node->getOperand(0).getValueType())) { 2314 default: assert(0 && "Unknown operation action!"); 2315 case TargetLowering::Expand: 2316 Result = ExpandLegalINT_TO_FP(isSigned, 2317 LegalizeOp(Node->getOperand(0)), 2318 Node->getValueType(0)); 2319 AddLegalizedOperand(Op, Result); 2320 return Result; 2321 case TargetLowering::Promote: 2322 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 2323 Node->getValueType(0), 2324 isSigned); 2325 AddLegalizedOperand(Op, Result); 2326 return Result; 2327 case TargetLowering::Legal: 2328 break; 2329 case TargetLowering::Custom: { 2330 Tmp1 = LegalizeOp(Node->getOperand(0)); 2331 SDOperand Tmp = 2332 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2333 Tmp = TLI.LowerOperation(Tmp, DAG); 2334 if (Tmp.Val) { 2335 Tmp = LegalizeOp(Tmp); // Relegalize input. 2336 AddLegalizedOperand(Op, Tmp); 2337 return Tmp; 2338 } else { 2339 assert(0 && "Target Must Lower this"); 2340 } 2341 } 2342 } 2343 2344 Tmp1 = LegalizeOp(Node->getOperand(0)); 2345 if (Tmp1 != Node->getOperand(0)) 2346 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2347 break; 2348 case Expand: 2349 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 2350 Node->getValueType(0), Node->getOperand(0)); 2351 break; 2352 case Promote: 2353 if (isSigned) { 2354 Result = PromoteOp(Node->getOperand(0)); 2355 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2356 Result, DAG.getValueType(Node->getOperand(0).getValueType())); 2357 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result); 2358 } else { 2359 Result = PromoteOp(Node->getOperand(0)); 2360 Result = DAG.getZeroExtendInReg(Result, 2361 Node->getOperand(0).getValueType()); 2362 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result); 2363 } 2364 break; 2365 } 2366 break; 2367 } 2368 case ISD::TRUNCATE: 2369 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2370 case Legal: 2371 Tmp1 = LegalizeOp(Node->getOperand(0)); 2372 if (Tmp1 != Node->getOperand(0)) 2373 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2374 break; 2375 case Expand: 2376 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2377 2378 // Since the result is legal, we should just be able to truncate the low 2379 // part of the source. 2380 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 2381 break; 2382 case Promote: 2383 Result = PromoteOp(Node->getOperand(0)); 2384 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 2385 break; 2386 } 2387 break; 2388 2389 case ISD::FP_TO_SINT: 2390 case ISD::FP_TO_UINT: 2391 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2392 case Legal: 2393 Tmp1 = LegalizeOp(Node->getOperand(0)); 2394 2395 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 2396 default: assert(0 && "Unknown operation action!"); 2397 case TargetLowering::Expand: 2398 if (Node->getOpcode() == ISD::FP_TO_UINT) { 2399 SDOperand True, False; 2400 MVT::ValueType VT = Node->getOperand(0).getValueType(); 2401 MVT::ValueType NVT = Node->getValueType(0); 2402 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1; 2403 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT); 2404 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 2405 Node->getOperand(0), Tmp2, ISD::SETLT); 2406 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 2407 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 2408 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 2409 Tmp2)); 2410 False = DAG.getNode(ISD::XOR, NVT, False, 2411 DAG.getConstant(1ULL << ShiftAmt, NVT)); 2412 Result = LegalizeOp(DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False)); 2413 AddLegalizedOperand(SDOperand(Node, 0), Result); 2414 return Result; 2415 } else { 2416 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 2417 } 2418 break; 2419 case TargetLowering::Promote: 2420 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 2421 Node->getOpcode() == ISD::FP_TO_SINT); 2422 AddLegalizedOperand(Op, Result); 2423 return Result; 2424 case TargetLowering::Custom: { 2425 SDOperand Tmp = 2426 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2427 Tmp = TLI.LowerOperation(Tmp, DAG); 2428 if (Tmp.Val) { 2429 Tmp = LegalizeOp(Tmp); 2430 AddLegalizedOperand(Op, Tmp); 2431 return Tmp; 2432 } else { 2433 // The target thinks this is legal afterall. 2434 break; 2435 } 2436 } 2437 case TargetLowering::Legal: 2438 break; 2439 } 2440 2441 if (Tmp1 != Node->getOperand(0)) 2442 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2443 break; 2444 case Expand: 2445 assert(0 && "Shouldn't need to expand other operators here!"); 2446 case Promote: 2447 Result = PromoteOp(Node->getOperand(0)); 2448 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 2449 break; 2450 } 2451 break; 2452 2453 case ISD::ANY_EXTEND: 2454 case ISD::ZERO_EXTEND: 2455 case ISD::SIGN_EXTEND: 2456 case ISD::FP_EXTEND: 2457 case ISD::FP_ROUND: 2458 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2459 case Legal: 2460 Tmp1 = LegalizeOp(Node->getOperand(0)); 2461 if (Tmp1 != Node->getOperand(0)) 2462 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2463 break; 2464 case Expand: 2465 assert(0 && "Shouldn't need to expand other operators here!"); 2466 2467 case Promote: 2468 switch (Node->getOpcode()) { 2469 case ISD::ANY_EXTEND: 2470 Result = PromoteOp(Node->getOperand(0)); 2471 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2472 break; 2473 case ISD::ZERO_EXTEND: 2474 Result = PromoteOp(Node->getOperand(0)); 2475 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2476 Result = DAG.getZeroExtendInReg(Result, 2477 Node->getOperand(0).getValueType()); 2478 break; 2479 case ISD::SIGN_EXTEND: 2480 Result = PromoteOp(Node->getOperand(0)); 2481 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2482 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2483 Result, 2484 DAG.getValueType(Node->getOperand(0).getValueType())); 2485 break; 2486 case ISD::FP_EXTEND: 2487 Result = PromoteOp(Node->getOperand(0)); 2488 if (Result.getValueType() != Op.getValueType()) 2489 // Dynamically dead while we have only 2 FP types. 2490 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 2491 break; 2492 case ISD::FP_ROUND: 2493 Result = PromoteOp(Node->getOperand(0)); 2494 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 2495 break; 2496 } 2497 } 2498 break; 2499 case ISD::FP_ROUND_INREG: 2500 case ISD::SIGN_EXTEND_INREG: { 2501 Tmp1 = LegalizeOp(Node->getOperand(0)); 2502 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2503 2504 // If this operation is not supported, convert it to a shl/shr or load/store 2505 // pair. 2506 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 2507 default: assert(0 && "This action not supported for this op yet!"); 2508 case TargetLowering::Legal: 2509 if (Tmp1 != Node->getOperand(0)) 2510 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 2511 DAG.getValueType(ExtraVT)); 2512 break; 2513 case TargetLowering::Expand: 2514 // If this is an integer extend and shifts are supported, do that. 2515 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 2516 // NOTE: we could fall back on load/store here too for targets without 2517 // SAR. However, it is doubtful that any exist. 2518 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 2519 MVT::getSizeInBits(ExtraVT); 2520 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 2521 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 2522 Node->getOperand(0), ShiftCst); 2523 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 2524 Result, ShiftCst); 2525 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 2526 // The only way we can lower this is to turn it into a STORETRUNC, 2527 // EXTLOAD pair, targetting a temporary location (a stack slot). 2528 2529 // NOTE: there is a choice here between constantly creating new stack 2530 // slots and always reusing the same one. We currently always create 2531 // new ones, as reuse may inhibit scheduling. 2532 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 2533 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty); 2534 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty); 2535 MachineFunction &MF = DAG.getMachineFunction(); 2536 int SSFI = 2537 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 2538 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 2539 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(), 2540 Node->getOperand(0), StackSlot, 2541 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT)); 2542 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2543 Result, StackSlot, DAG.getSrcValue(NULL), 2544 ExtraVT); 2545 } else { 2546 assert(0 && "Unknown op"); 2547 } 2548 Result = LegalizeOp(Result); 2549 break; 2550 } 2551 break; 2552 } 2553 } 2554 2555 // Note that LegalizeOp may be reentered even from single-use nodes, which 2556 // means that we always must cache transformed nodes. 2557 AddLegalizedOperand(Op, Result); 2558 return Result; 2559} 2560 2561/// PromoteOp - Given an operation that produces a value in an invalid type, 2562/// promote it to compute the value into a larger type. The produced value will 2563/// have the correct bits for the low portion of the register, but no guarantee 2564/// is made about the top bits: it may be zero, sign-extended, or garbage. 2565SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 2566 MVT::ValueType VT = Op.getValueType(); 2567 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 2568 assert(getTypeAction(VT) == Promote && 2569 "Caller should expand or legalize operands that are not promotable!"); 2570 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 2571 "Cannot promote to smaller type!"); 2572 2573 SDOperand Tmp1, Tmp2, Tmp3; 2574 2575 SDOperand Result; 2576 SDNode *Node = Op.Val; 2577 2578 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 2579 if (I != PromotedNodes.end()) return I->second; 2580 2581 // Promotion needs an optimization step to clean up after it, and is not 2582 // careful to avoid operations the target does not support. Make sure that 2583 // all generated operations are legalized in the next iteration. 2584 NeedsAnotherIteration = true; 2585 2586 switch (Node->getOpcode()) { 2587 case ISD::CopyFromReg: 2588 assert(0 && "CopyFromReg must be legal!"); 2589 default: 2590 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 2591 assert(0 && "Do not know how to promote this operator!"); 2592 abort(); 2593 case ISD::UNDEF: 2594 Result = DAG.getNode(ISD::UNDEF, NVT); 2595 break; 2596 case ISD::Constant: 2597 if (VT != MVT::i1) 2598 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 2599 else 2600 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 2601 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 2602 break; 2603 case ISD::ConstantFP: 2604 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 2605 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 2606 break; 2607 2608 case ISD::SETCC: 2609 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 2610 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 2611 Node->getOperand(1), Node->getOperand(2)); 2612 Result = LegalizeOp(Result); 2613 break; 2614 2615 case ISD::TRUNCATE: 2616 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2617 case Legal: 2618 Result = LegalizeOp(Node->getOperand(0)); 2619 assert(Result.getValueType() >= NVT && 2620 "This truncation doesn't make sense!"); 2621 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 2622 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 2623 break; 2624 case Promote: 2625 // The truncation is not required, because we don't guarantee anything 2626 // about high bits anyway. 2627 Result = PromoteOp(Node->getOperand(0)); 2628 break; 2629 case Expand: 2630 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2631 // Truncate the low part of the expanded value to the result type 2632 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 2633 } 2634 break; 2635 case ISD::SIGN_EXTEND: 2636 case ISD::ZERO_EXTEND: 2637 case ISD::ANY_EXTEND: 2638 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2639 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 2640 case Legal: 2641 // Input is legal? Just do extend all the way to the larger type. 2642 Result = LegalizeOp(Node->getOperand(0)); 2643 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2644 break; 2645 case Promote: 2646 // Promote the reg if it's smaller. 2647 Result = PromoteOp(Node->getOperand(0)); 2648 // The high bits are not guaranteed to be anything. Insert an extend. 2649 if (Node->getOpcode() == ISD::SIGN_EXTEND) 2650 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 2651 DAG.getValueType(Node->getOperand(0).getValueType())); 2652 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 2653 Result = DAG.getZeroExtendInReg(Result, 2654 Node->getOperand(0).getValueType()); 2655 break; 2656 } 2657 break; 2658 case ISD::BIT_CONVERT: 2659 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2660 Result = PromoteOp(Result); 2661 break; 2662 2663 case ISD::FP_EXTEND: 2664 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 2665 case ISD::FP_ROUND: 2666 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2667 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 2668 case Promote: assert(0 && "Unreachable with 2 FP types!"); 2669 case Legal: 2670 // Input is legal? Do an FP_ROUND_INREG. 2671 Result = LegalizeOp(Node->getOperand(0)); 2672 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2673 DAG.getValueType(VT)); 2674 break; 2675 } 2676 break; 2677 2678 case ISD::SINT_TO_FP: 2679 case ISD::UINT_TO_FP: 2680 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2681 case Legal: 2682 Result = LegalizeOp(Node->getOperand(0)); 2683 // No extra round required here. 2684 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2685 break; 2686 2687 case Promote: 2688 Result = PromoteOp(Node->getOperand(0)); 2689 if (Node->getOpcode() == ISD::SINT_TO_FP) 2690 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2691 Result, 2692 DAG.getValueType(Node->getOperand(0).getValueType())); 2693 else 2694 Result = DAG.getZeroExtendInReg(Result, 2695 Node->getOperand(0).getValueType()); 2696 // No extra round required here. 2697 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2698 break; 2699 case Expand: 2700 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 2701 Node->getOperand(0)); 2702 // Round if we cannot tolerate excess precision. 2703 if (NoExcessFPPrecision) 2704 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2705 DAG.getValueType(VT)); 2706 break; 2707 } 2708 break; 2709 2710 case ISD::SIGN_EXTEND_INREG: 2711 Result = PromoteOp(Node->getOperand(0)); 2712 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 2713 Node->getOperand(1)); 2714 break; 2715 case ISD::FP_TO_SINT: 2716 case ISD::FP_TO_UINT: 2717 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2718 case Legal: 2719 Tmp1 = LegalizeOp(Node->getOperand(0)); 2720 break; 2721 case Promote: 2722 // The input result is prerounded, so we don't have to do anything 2723 // special. 2724 Tmp1 = PromoteOp(Node->getOperand(0)); 2725 break; 2726 case Expand: 2727 assert(0 && "not implemented"); 2728 } 2729 // If we're promoting a UINT to a larger size, check to see if the new node 2730 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 2731 // we can use that instead. This allows us to generate better code for 2732 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 2733 // legal, such as PowerPC. 2734 if (Node->getOpcode() == ISD::FP_TO_UINT && 2735 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 2736 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 2737 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 2738 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 2739 } else { 2740 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2741 } 2742 break; 2743 2744 case ISD::FABS: 2745 case ISD::FNEG: 2746 Tmp1 = PromoteOp(Node->getOperand(0)); 2747 assert(Tmp1.getValueType() == NVT); 2748 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2749 // NOTE: we do not have to do any extra rounding here for 2750 // NoExcessFPPrecision, because we know the input will have the appropriate 2751 // precision, and these operations don't modify precision at all. 2752 break; 2753 2754 case ISD::FSQRT: 2755 case ISD::FSIN: 2756 case ISD::FCOS: 2757 Tmp1 = PromoteOp(Node->getOperand(0)); 2758 assert(Tmp1.getValueType() == NVT); 2759 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2760 if(NoExcessFPPrecision) 2761 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2762 DAG.getValueType(VT)); 2763 break; 2764 2765 case ISD::AND: 2766 case ISD::OR: 2767 case ISD::XOR: 2768 case ISD::ADD: 2769 case ISD::SUB: 2770 case ISD::MUL: 2771 // The input may have strange things in the top bits of the registers, but 2772 // these operations don't care. They may have weird bits going out, but 2773 // that too is okay if they are integer operations. 2774 Tmp1 = PromoteOp(Node->getOperand(0)); 2775 Tmp2 = PromoteOp(Node->getOperand(1)); 2776 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 2777 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2778 break; 2779 case ISD::FADD: 2780 case ISD::FSUB: 2781 case ISD::FMUL: 2782 // The input may have strange things in the top bits of the registers, but 2783 // these operations don't care. 2784 Tmp1 = PromoteOp(Node->getOperand(0)); 2785 Tmp2 = PromoteOp(Node->getOperand(1)); 2786 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 2787 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2788 2789 // Floating point operations will give excess precision that we may not be 2790 // able to tolerate. If we DO allow excess precision, just leave it, 2791 // otherwise excise it. 2792 // FIXME: Why would we need to round FP ops more than integer ones? 2793 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 2794 if (NoExcessFPPrecision) 2795 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2796 DAG.getValueType(VT)); 2797 break; 2798 2799 case ISD::SDIV: 2800 case ISD::SREM: 2801 // These operators require that their input be sign extended. 2802 Tmp1 = PromoteOp(Node->getOperand(0)); 2803 Tmp2 = PromoteOp(Node->getOperand(1)); 2804 if (MVT::isInteger(NVT)) { 2805 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 2806 DAG.getValueType(VT)); 2807 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 2808 DAG.getValueType(VT)); 2809 } 2810 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2811 2812 // Perform FP_ROUND: this is probably overly pessimistic. 2813 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 2814 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2815 DAG.getValueType(VT)); 2816 break; 2817 case ISD::FDIV: 2818 case ISD::FREM: 2819 // These operators require that their input be fp extended. 2820 Tmp1 = PromoteOp(Node->getOperand(0)); 2821 Tmp2 = PromoteOp(Node->getOperand(1)); 2822 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2823 2824 // Perform FP_ROUND: this is probably overly pessimistic. 2825 if (NoExcessFPPrecision) 2826 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2827 DAG.getValueType(VT)); 2828 break; 2829 2830 case ISD::UDIV: 2831 case ISD::UREM: 2832 // These operators require that their input be zero extended. 2833 Tmp1 = PromoteOp(Node->getOperand(0)); 2834 Tmp2 = PromoteOp(Node->getOperand(1)); 2835 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 2836 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 2837 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 2838 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2839 break; 2840 2841 case ISD::SHL: 2842 Tmp1 = PromoteOp(Node->getOperand(0)); 2843 Tmp2 = LegalizeOp(Node->getOperand(1)); 2844 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2); 2845 break; 2846 case ISD::SRA: 2847 // The input value must be properly sign extended. 2848 Tmp1 = PromoteOp(Node->getOperand(0)); 2849 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 2850 DAG.getValueType(VT)); 2851 Tmp2 = LegalizeOp(Node->getOperand(1)); 2852 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2); 2853 break; 2854 case ISD::SRL: 2855 // The input value must be properly zero extended. 2856 Tmp1 = PromoteOp(Node->getOperand(0)); 2857 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 2858 Tmp2 = LegalizeOp(Node->getOperand(1)); 2859 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2); 2860 break; 2861 case ISD::LOAD: 2862 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2863 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2864 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp1, Tmp2, 2865 Node->getOperand(2), VT); 2866 // Remember that we legalized the chain. 2867 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2868 break; 2869 case ISD::SEXTLOAD: 2870 case ISD::ZEXTLOAD: 2871 case ISD::EXTLOAD: 2872 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2873 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2874 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Tmp1, Tmp2, 2875 Node->getOperand(2), 2876 cast<VTSDNode>(Node->getOperand(3))->getVT()); 2877 // Remember that we legalized the chain. 2878 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2879 break; 2880 case ISD::SELECT: 2881 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2882 case Expand: assert(0 && "It's impossible to expand bools"); 2883 case Legal: 2884 Tmp1 = LegalizeOp(Node->getOperand(0));// Legalize the condition. 2885 break; 2886 case Promote: 2887 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2888 break; 2889 } 2890 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 2891 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 2892 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3); 2893 break; 2894 case ISD::SELECT_CC: 2895 Tmp2 = PromoteOp(Node->getOperand(2)); // True 2896 Tmp3 = PromoteOp(Node->getOperand(3)); // False 2897 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 2898 Node->getOperand(1), Tmp2, Tmp3, 2899 Node->getOperand(4)); 2900 break; 2901 case ISD::TAILCALL: 2902 case ISD::CALL: { 2903 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2904 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 2905 2906 std::vector<SDOperand> Ops; 2907 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) 2908 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2909 2910 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 2911 "Can only promote single result calls"); 2912 std::vector<MVT::ValueType> RetTyVTs; 2913 RetTyVTs.reserve(2); 2914 RetTyVTs.push_back(NVT); 2915 RetTyVTs.push_back(MVT::Other); 2916 SDNode *NC = DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops, 2917 Node->getOpcode() == ISD::TAILCALL); 2918 Result = SDOperand(NC, 0); 2919 2920 // Insert the new chain mapping. 2921 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2922 break; 2923 } 2924 case ISD::CTPOP: 2925 case ISD::CTTZ: 2926 case ISD::CTLZ: 2927 Tmp1 = Node->getOperand(0); 2928 //Zero extend the argument 2929 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2930 // Perform the larger operation, then subtract if needed. 2931 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2932 switch(Node->getOpcode()) 2933 { 2934 case ISD::CTPOP: 2935 Result = Tmp1; 2936 break; 2937 case ISD::CTTZ: 2938 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 2939 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 2940 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ); 2941 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 2942 DAG.getConstant(getSizeInBits(VT),NVT), Tmp1); 2943 break; 2944 case ISD::CTLZ: 2945 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2946 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 2947 DAG.getConstant(getSizeInBits(NVT) - 2948 getSizeInBits(VT), NVT)); 2949 break; 2950 } 2951 break; 2952 } 2953 2954 assert(Result.Val && "Didn't set a result!"); 2955 AddPromotedOperand(Op, Result); 2956 return Result; 2957} 2958 2959/// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination. 2960/// The resultant code need not be legal. Note that SrcOp is the input operand 2961/// to the BIT_CONVERT, not the BIT_CONVERT node itself. 2962SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT, 2963 SDOperand SrcOp) { 2964 // Create the stack frame object. 2965 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 2966 unsigned ByteSize = MVT::getSizeInBits(DestVT)/8; 2967 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize); 2968 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy()); 2969 2970 // Emit a store to the stack slot. 2971 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 2972 SrcOp, FIPtr, DAG.getSrcValue(NULL)); 2973 // Result is a load from the stack slot. 2974 return DAG.getLoad(DestVT, Store, FIPtr, DAG.getSrcValue(0)); 2975} 2976 2977/// ExpandAddSub - Find a clever way to expand this add operation into 2978/// subcomponents. 2979void SelectionDAGLegalize:: 2980ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 2981 SDOperand &Lo, SDOperand &Hi) { 2982 // Expand the subcomponents. 2983 SDOperand LHSL, LHSH, RHSL, RHSH; 2984 ExpandOp(LHS, LHSL, LHSH); 2985 ExpandOp(RHS, RHSL, RHSH); 2986 2987 std::vector<SDOperand> Ops; 2988 Ops.push_back(LHSL); 2989 Ops.push_back(LHSH); 2990 Ops.push_back(RHSL); 2991 Ops.push_back(RHSH); 2992 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 2993 Lo = DAG.getNode(NodeOp, VTs, Ops); 2994 Hi = Lo.getValue(1); 2995} 2996 2997void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 2998 SDOperand Op, SDOperand Amt, 2999 SDOperand &Lo, SDOperand &Hi) { 3000 // Expand the subcomponents. 3001 SDOperand LHSL, LHSH; 3002 ExpandOp(Op, LHSL, LHSH); 3003 3004 std::vector<SDOperand> Ops; 3005 Ops.push_back(LHSL); 3006 Ops.push_back(LHSH); 3007 Ops.push_back(Amt); 3008 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 3009 Lo = DAG.getNode(NodeOp, VTs, Ops); 3010 Hi = Lo.getValue(1); 3011} 3012 3013 3014/// ExpandShift - Try to find a clever way to expand this shift operation out to 3015/// smaller elements. If we can't find a way that is more efficient than a 3016/// libcall on this target, return false. Otherwise, return true with the 3017/// low-parts expanded into Lo and Hi. 3018bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 3019 SDOperand &Lo, SDOperand &Hi) { 3020 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 3021 "This is not a shift!"); 3022 3023 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 3024 SDOperand ShAmt = LegalizeOp(Amt); 3025 MVT::ValueType ShTy = ShAmt.getValueType(); 3026 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 3027 unsigned NVTBits = MVT::getSizeInBits(NVT); 3028 3029 // Handle the case when Amt is an immediate. Other cases are currently broken 3030 // and are disabled. 3031 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 3032 unsigned Cst = CN->getValue(); 3033 // Expand the incoming operand to be shifted, so that we have its parts 3034 SDOperand InL, InH; 3035 ExpandOp(Op, InL, InH); 3036 switch(Opc) { 3037 case ISD::SHL: 3038 if (Cst > VTBits) { 3039 Lo = DAG.getConstant(0, NVT); 3040 Hi = DAG.getConstant(0, NVT); 3041 } else if (Cst > NVTBits) { 3042 Lo = DAG.getConstant(0, NVT); 3043 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 3044 } else if (Cst == NVTBits) { 3045 Lo = DAG.getConstant(0, NVT); 3046 Hi = InL; 3047 } else { 3048 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 3049 Hi = DAG.getNode(ISD::OR, NVT, 3050 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 3051 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 3052 } 3053 return true; 3054 case ISD::SRL: 3055 if (Cst > VTBits) { 3056 Lo = DAG.getConstant(0, NVT); 3057 Hi = DAG.getConstant(0, NVT); 3058 } else if (Cst > NVTBits) { 3059 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 3060 Hi = DAG.getConstant(0, NVT); 3061 } else if (Cst == NVTBits) { 3062 Lo = InH; 3063 Hi = DAG.getConstant(0, NVT); 3064 } else { 3065 Lo = DAG.getNode(ISD::OR, NVT, 3066 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 3067 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 3068 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 3069 } 3070 return true; 3071 case ISD::SRA: 3072 if (Cst > VTBits) { 3073 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 3074 DAG.getConstant(NVTBits-1, ShTy)); 3075 } else if (Cst > NVTBits) { 3076 Lo = DAG.getNode(ISD::SRA, NVT, InH, 3077 DAG.getConstant(Cst-NVTBits, ShTy)); 3078 Hi = DAG.getNode(ISD::SRA, NVT, InH, 3079 DAG.getConstant(NVTBits-1, ShTy)); 3080 } else if (Cst == NVTBits) { 3081 Lo = InH; 3082 Hi = DAG.getNode(ISD::SRA, NVT, InH, 3083 DAG.getConstant(NVTBits-1, ShTy)); 3084 } else { 3085 Lo = DAG.getNode(ISD::OR, NVT, 3086 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 3087 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 3088 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 3089 } 3090 return true; 3091 } 3092 } 3093 // FIXME: The following code for expanding shifts using ISD::SELECT is buggy, 3094 // so disable it for now. Currently targets are handling this via SHL_PARTS 3095 // and friends. 3096 return false; 3097 3098 // If we have an efficient select operation (or if the selects will all fold 3099 // away), lower to some complex code, otherwise just emit the libcall. 3100 if (!TLI.isOperationLegal(ISD::SELECT, NVT) && !isa<ConstantSDNode>(Amt)) 3101 return false; 3102 3103 SDOperand InL, InH; 3104 ExpandOp(Op, InL, InH); 3105 SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy, // NAmt = 32-ShAmt 3106 DAG.getConstant(NVTBits, ShTy), ShAmt); 3107 3108 // Compare the unmasked shift amount against 32. 3109 SDOperand Cond = DAG.getSetCC(TLI.getSetCCResultTy(), ShAmt, 3110 DAG.getConstant(NVTBits, ShTy), ISD::SETGE); 3111 3112 if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) { 3113 ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt, // ShAmt &= 31 3114 DAG.getConstant(NVTBits-1, ShTy)); 3115 NAmt = DAG.getNode(ISD::AND, ShTy, NAmt, // NAmt &= 31 3116 DAG.getConstant(NVTBits-1, ShTy)); 3117 } 3118 3119 if (Opc == ISD::SHL) { 3120 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt) 3121 DAG.getNode(ISD::SHL, NVT, InH, ShAmt), 3122 DAG.getNode(ISD::SRL, NVT, InL, NAmt)); 3123 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31 3124 3125 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 3126 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2); 3127 } else { 3128 SDOperand HiLoPart = DAG.getNode(ISD::SELECT, NVT, 3129 DAG.getSetCC(TLI.getSetCCResultTy(), NAmt, 3130 DAG.getConstant(32, ShTy), 3131 ISD::SETEQ), 3132 DAG.getConstant(0, NVT), 3133 DAG.getNode(ISD::SHL, NVT, InH, NAmt)); 3134 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << NAmt) | (Lo >> Amt) 3135 HiLoPart, 3136 DAG.getNode(ISD::SRL, NVT, InL, ShAmt)); 3137 SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt); // T2 = InH >> ShAmt&31 3138 3139 SDOperand HiPart; 3140 if (Opc == ISD::SRA) 3141 HiPart = DAG.getNode(ISD::SRA, NVT, InH, 3142 DAG.getConstant(NVTBits-1, ShTy)); 3143 else 3144 HiPart = DAG.getConstant(0, NVT); 3145 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 3146 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart, T2); 3147 } 3148 return true; 3149} 3150 3151/// FindLatestCallSeqStart - Scan up the dag to find the latest (highest 3152/// NodeDepth) node that is an CallSeqStart operation and occurs later than 3153/// Found. 3154static void FindLatestCallSeqStart(SDNode *Node, SDNode *&Found, 3155 std::set<SDNode*> &Visited) { 3156 if (Node->getNodeDepth() <= Found->getNodeDepth() || 3157 !Visited.insert(Node).second) return; 3158 3159 // If we found an CALLSEQ_START, we already know this node occurs later 3160 // than the Found node. Just remember this node and return. 3161 if (Node->getOpcode() == ISD::CALLSEQ_START) { 3162 Found = Node; 3163 return; 3164 } 3165 3166 // Otherwise, scan the operands of Node to see if any of them is a call. 3167 assert(Node->getNumOperands() != 0 && 3168 "All leaves should have depth equal to the entry node!"); 3169 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i) 3170 FindLatestCallSeqStart(Node->getOperand(i).Val, Found, Visited); 3171 3172 // Tail recurse for the last iteration. 3173 FindLatestCallSeqStart(Node->getOperand(Node->getNumOperands()-1).Val, 3174 Found, Visited); 3175} 3176 3177 3178/// FindEarliestCallSeqEnd - Scan down the dag to find the earliest (lowest 3179/// NodeDepth) node that is an CallSeqEnd operation and occurs more recent 3180/// than Found. 3181static void FindEarliestCallSeqEnd(SDNode *Node, SDNode *&Found, 3182 std::set<SDNode*> &Visited) { 3183 if ((Found && Node->getNodeDepth() >= Found->getNodeDepth()) || 3184 !Visited.insert(Node).second) return; 3185 3186 // If we found an CALLSEQ_END, we already know this node occurs earlier 3187 // than the Found node. Just remember this node and return. 3188 if (Node->getOpcode() == ISD::CALLSEQ_END) { 3189 Found = Node; 3190 return; 3191 } 3192 3193 // Otherwise, scan the operands of Node to see if any of them is a call. 3194 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 3195 if (UI == E) return; 3196 for (--E; UI != E; ++UI) 3197 FindEarliestCallSeqEnd(*UI, Found, Visited); 3198 3199 // Tail recurse for the last iteration. 3200 FindEarliestCallSeqEnd(*UI, Found, Visited); 3201} 3202 3203/// FindCallSeqEnd - Given a chained node that is part of a call sequence, 3204/// find the CALLSEQ_END node that terminates the call sequence. 3205static SDNode *FindCallSeqEnd(SDNode *Node) { 3206 if (Node->getOpcode() == ISD::CALLSEQ_END) 3207 return Node; 3208 if (Node->use_empty()) 3209 return 0; // No CallSeqEnd 3210 3211 SDOperand TheChain(Node, Node->getNumValues()-1); 3212 if (TheChain.getValueType() != MVT::Other) 3213 TheChain = SDOperand(Node, 0); 3214 if (TheChain.getValueType() != MVT::Other) 3215 return 0; 3216 3217 for (SDNode::use_iterator UI = Node->use_begin(), 3218 E = Node->use_end(); UI != E; ++UI) { 3219 3220 // Make sure to only follow users of our token chain. 3221 SDNode *User = *UI; 3222 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 3223 if (User->getOperand(i) == TheChain) 3224 if (SDNode *Result = FindCallSeqEnd(User)) 3225 return Result; 3226 } 3227 return 0; 3228} 3229 3230/// FindCallSeqStart - Given a chained node that is part of a call sequence, 3231/// find the CALLSEQ_START node that initiates the call sequence. 3232static SDNode *FindCallSeqStart(SDNode *Node) { 3233 assert(Node && "Didn't find callseq_start for a call??"); 3234 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 3235 3236 assert(Node->getOperand(0).getValueType() == MVT::Other && 3237 "Node doesn't have a token chain argument!"); 3238 return FindCallSeqStart(Node->getOperand(0).Val); 3239} 3240 3241 3242/// FindInputOutputChains - If we are replacing an operation with a call we need 3243/// to find the call that occurs before and the call that occurs after it to 3244/// properly serialize the calls in the block. The returned operand is the 3245/// input chain value for the new call (e.g. the entry node or the previous 3246/// call), and OutChain is set to be the chain node to update to point to the 3247/// end of the call chain. 3248static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain, 3249 SDOperand Entry) { 3250 SDNode *LatestCallSeqStart = Entry.Val; 3251 SDNode *LatestCallSeqEnd = 0; 3252 std::set<SDNode*> Visited; 3253 FindLatestCallSeqStart(OpNode, LatestCallSeqStart, Visited); 3254 Visited.clear(); 3255 //std::cerr<<"Found node: "; LatestCallSeqStart->dump(); std::cerr <<"\n"; 3256 3257 // It is possible that no ISD::CALLSEQ_START was found because there is no 3258 // previous call in the function. LatestCallStackDown may in that case be 3259 // the entry node itself. Do not attempt to find a matching CALLSEQ_END 3260 // unless LatestCallStackDown is an CALLSEQ_START. 3261 if (LatestCallSeqStart->getOpcode() == ISD::CALLSEQ_START) { 3262 LatestCallSeqEnd = FindCallSeqEnd(LatestCallSeqStart); 3263 //std::cerr<<"Found end node: "; LatestCallSeqEnd->dump(); std::cerr <<"\n"; 3264 } else { 3265 LatestCallSeqEnd = Entry.Val; 3266 } 3267 assert(LatestCallSeqEnd && "NULL return from FindCallSeqEnd"); 3268 3269 // Finally, find the first call that this must come before, first we find the 3270 // CallSeqEnd that ends the call. 3271 OutChain = 0; 3272 FindEarliestCallSeqEnd(OpNode, OutChain, Visited); 3273 Visited.clear(); 3274 3275 // If we found one, translate from the adj up to the callseq_start. 3276 if (OutChain) 3277 OutChain = FindCallSeqStart(OutChain); 3278 3279 return SDOperand(LatestCallSeqEnd, 0); 3280} 3281 3282/// SpliceCallInto - Given the result chain of a libcall (CallResult), and a 3283void SelectionDAGLegalize::SpliceCallInto(const SDOperand &CallResult, 3284 SDNode *OutChain) { 3285 // Nothing to splice it into? 3286 if (OutChain == 0) return; 3287 3288 assert(OutChain->getOperand(0).getValueType() == MVT::Other); 3289 //OutChain->dump(); 3290 3291 // Form a token factor node merging the old inval and the new inval. 3292 SDOperand InToken = DAG.getNode(ISD::TokenFactor, MVT::Other, CallResult, 3293 OutChain->getOperand(0)); 3294 // Change the node to refer to the new token. 3295 OutChain->setAdjCallChain(InToken); 3296} 3297 3298 3299// ExpandLibCall - Expand a node into a call to a libcall. If the result value 3300// does not fit into a register, return the lo part and set the hi part to the 3301// by-reg argument. If it does fit into a single register, return the result 3302// and leave the Hi part unset. 3303SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 3304 SDOperand &Hi) { 3305 SDNode *OutChain; 3306 SDOperand InChain = FindInputOutputChains(Node, OutChain, 3307 DAG.getEntryNode()); 3308 if (InChain.Val == 0) 3309 InChain = DAG.getEntryNode(); 3310 3311 TargetLowering::ArgListTy Args; 3312 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 3313 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 3314 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 3315 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy)); 3316 } 3317 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 3318 3319 // Splice the libcall in wherever FindInputOutputChains tells us to. 3320 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 3321 std::pair<SDOperand,SDOperand> CallInfo = 3322 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false, 3323 Callee, Args, DAG); 3324 3325 SDOperand Result; 3326 switch (getTypeAction(CallInfo.first.getValueType())) { 3327 default: assert(0 && "Unknown thing"); 3328 case Legal: 3329 Result = CallInfo.first; 3330 break; 3331 case Promote: 3332 assert(0 && "Cannot promote this yet!"); 3333 case Expand: 3334 ExpandOp(CallInfo.first, Result, Hi); 3335 CallInfo.second = LegalizeOp(CallInfo.second); 3336 break; 3337 } 3338 3339 SpliceCallInto(CallInfo.second, OutChain); 3340 NeedsAnotherIteration = true; 3341 return Result; 3342} 3343 3344 3345/// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the 3346/// destination type is legal. 3347SDOperand SelectionDAGLegalize:: 3348ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 3349 assert(isTypeLegal(DestTy) && "Destination type is not legal!"); 3350 assert(getTypeAction(Source.getValueType()) == Expand && 3351 "This is not an expansion!"); 3352 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 3353 3354 if (!isSigned) { 3355 assert(Source.getValueType() == MVT::i64 && 3356 "This only works for 64-bit -> FP"); 3357 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 3358 // incoming integer is set. To handle this, we dynamically test to see if 3359 // it is set, and, if so, add a fudge factor. 3360 SDOperand Lo, Hi; 3361 ExpandOp(Source, Lo, Hi); 3362 3363 // If this is unsigned, and not supported, first perform the conversion to 3364 // signed, then adjust the result if the sign bit is set. 3365 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 3366 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 3367 3368 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 3369 DAG.getConstant(0, Hi.getValueType()), 3370 ISD::SETLT); 3371 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 3372 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 3373 SignSet, Four, Zero); 3374 uint64_t FF = 0x5f800000ULL; 3375 if (TLI.isLittleEndian()) FF <<= 32; 3376 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 3377 3378 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 3379 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 3380 SDOperand FudgeInReg; 3381 if (DestTy == MVT::f32) 3382 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 3383 DAG.getSrcValue(NULL)); 3384 else { 3385 assert(DestTy == MVT::f64 && "Unexpected conversion"); 3386 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 3387 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 3388 } 3389 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 3390 } 3391 3392 // Check to see if the target has a custom way to lower this. If so, use it. 3393 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 3394 default: assert(0 && "This action not implemented for this operation!"); 3395 case TargetLowering::Legal: 3396 case TargetLowering::Expand: 3397 break; // This case is handled below. 3398 case TargetLowering::Custom: { 3399 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 3400 Source), DAG); 3401 if (NV.Val) 3402 return LegalizeOp(NV); 3403 break; // The target decided this was legal after all 3404 } 3405 } 3406 3407 // Expand the source, then glue it back together for the call. We must expand 3408 // the source in case it is shared (this pass of legalize must traverse it). 3409 SDOperand SrcLo, SrcHi; 3410 ExpandOp(Source, SrcLo, SrcHi); 3411 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 3412 3413 SDNode *OutChain = 0; 3414 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain, 3415 DAG.getEntryNode()); 3416 const char *FnName = 0; 3417 if (DestTy == MVT::f32) 3418 FnName = "__floatdisf"; 3419 else { 3420 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 3421 FnName = "__floatdidf"; 3422 } 3423 3424 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy()); 3425 3426 TargetLowering::ArgListTy Args; 3427 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType()); 3428 3429 Args.push_back(std::make_pair(Source, ArgTy)); 3430 3431 // We don't care about token chains for libcalls. We just use the entry 3432 // node as our input and ignore the output chain. This allows us to place 3433 // calls wherever we need them to satisfy data dependences. 3434 const Type *RetTy = MVT::getTypeForValueType(DestTy); 3435 3436 std::pair<SDOperand,SDOperand> CallResult = 3437 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, true, 3438 Callee, Args, DAG); 3439 3440 SpliceCallInto(CallResult.second, OutChain); 3441 return CallResult.first; 3442} 3443 3444 3445 3446/// ExpandOp - Expand the specified SDOperand into its two component pieces 3447/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 3448/// LegalizeNodes map is filled in for any results that are not expanded, the 3449/// ExpandedNodes map is filled in for any results that are expanded, and the 3450/// Lo/Hi values are returned. 3451void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 3452 MVT::ValueType VT = Op.getValueType(); 3453 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3454 SDNode *Node = Op.Val; 3455 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 3456 assert((MVT::isInteger(VT) || VT == MVT::Vector) && 3457 "Cannot expand FP values!"); 3458 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) && 3459 "Cannot expand to FP value or to larger int value!"); 3460 3461 // See if we already expanded it. 3462 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 3463 = ExpandedNodes.find(Op); 3464 if (I != ExpandedNodes.end()) { 3465 Lo = I->second.first; 3466 Hi = I->second.second; 3467 return; 3468 } 3469 3470 // Expanding to multiple registers needs to perform an optimization step, and 3471 // is not careful to avoid operations the target does not support. Make sure 3472 // that all generated operations are legalized in the next iteration. 3473 NeedsAnotherIteration = true; 3474 3475 switch (Node->getOpcode()) { 3476 case ISD::CopyFromReg: 3477 assert(0 && "CopyFromReg must be legal!"); 3478 default: 3479 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 3480 assert(0 && "Do not know how to expand this operator!"); 3481 abort(); 3482 case ISD::UNDEF: 3483 Lo = DAG.getNode(ISD::UNDEF, NVT); 3484 Hi = DAG.getNode(ISD::UNDEF, NVT); 3485 break; 3486 case ISD::Constant: { 3487 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 3488 Lo = DAG.getConstant(Cst, NVT); 3489 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 3490 break; 3491 } 3492 case ISD::ConstantVec: { 3493 unsigned NumElements = Node->getNumOperands(); 3494 // If we only have two elements left in the constant vector, just break it 3495 // apart into the two scalar constants it contains. Otherwise, bisect the 3496 // ConstantVec, and return each half as a new ConstantVec. 3497 // FIXME: this is hard coded as big endian, it may have to change to support 3498 // SSE and Alpha MVI 3499 if (NumElements == 2) { 3500 Hi = Node->getOperand(0); 3501 Lo = Node->getOperand(1); 3502 } else { 3503 NumElements /= 2; 3504 std::vector<SDOperand> LoOps, HiOps; 3505 for (unsigned I = 0, E = NumElements; I < E; ++I) { 3506 HiOps.push_back(Node->getOperand(I)); 3507 LoOps.push_back(Node->getOperand(I+NumElements)); 3508 } 3509 Lo = DAG.getNode(ISD::ConstantVec, MVT::Vector, LoOps); 3510 Hi = DAG.getNode(ISD::ConstantVec, MVT::Vector, HiOps); 3511 } 3512 break; 3513 } 3514 3515 case ISD::BUILD_PAIR: 3516 // Legalize both operands. FIXME: in the future we should handle the case 3517 // where the two elements are not legal. 3518 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!"); 3519 Lo = LegalizeOp(Node->getOperand(0)); 3520 Hi = LegalizeOp(Node->getOperand(1)); 3521 break; 3522 3523 case ISD::SIGN_EXTEND_INREG: 3524 ExpandOp(Node->getOperand(0), Lo, Hi); 3525 // Sign extend the lo-part. 3526 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 3527 DAG.getConstant(MVT::getSizeInBits(NVT)-1, 3528 TLI.getShiftAmountTy())); 3529 // sext_inreg the low part if needed. 3530 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 3531 break; 3532 3533 case ISD::CTPOP: 3534 ExpandOp(Node->getOperand(0), Lo, Hi); 3535 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 3536 DAG.getNode(ISD::CTPOP, NVT, Lo), 3537 DAG.getNode(ISD::CTPOP, NVT, Hi)); 3538 Hi = DAG.getConstant(0, NVT); 3539 break; 3540 3541 case ISD::CTLZ: { 3542 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 3543 ExpandOp(Node->getOperand(0), Lo, Hi); 3544 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 3545 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 3546 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 3547 ISD::SETNE); 3548 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 3549 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 3550 3551 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 3552 Hi = DAG.getConstant(0, NVT); 3553 break; 3554 } 3555 3556 case ISD::CTTZ: { 3557 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 3558 ExpandOp(Node->getOperand(0), Lo, Hi); 3559 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 3560 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 3561 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 3562 ISD::SETNE); 3563 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 3564 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 3565 3566 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 3567 Hi = DAG.getConstant(0, NVT); 3568 break; 3569 } 3570 3571 case ISD::LOAD: { 3572 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3573 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3574 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 3575 3576 // Increment the pointer to the other half. 3577 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 3578 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3579 getIntPtrConstant(IncrementSize)); 3580 //Is this safe? declaring that the two parts of the split load 3581 //are from the same instruction? 3582 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 3583 3584 // Build a factor node to remember that this load is independent of the 3585 // other one. 3586 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 3587 Hi.getValue(1)); 3588 3589 // Remember that we legalized the chain. 3590 AddLegalizedOperand(Op.getValue(1), TF); 3591 if (!TLI.isLittleEndian()) 3592 std::swap(Lo, Hi); 3593 break; 3594 } 3595 case ISD::VLOAD: { 3596 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3597 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3598 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue(); 3599 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3600 3601 // If we only have two elements, turn into a pair of scalar loads. 3602 // FIXME: handle case where a vector of two elements is fine, such as 3603 // 2 x double on SSE2. 3604 if (NumElements == 2) { 3605 Lo = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4)); 3606 // Increment the pointer to the other half. 3607 unsigned IncrementSize = MVT::getSizeInBits(EVT)/8; 3608 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3609 getIntPtrConstant(IncrementSize)); 3610 //Is this safe? declaring that the two parts of the split load 3611 //are from the same instruction? 3612 Hi = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4)); 3613 } else { 3614 NumElements /= 2; // Split the vector in half 3615 Lo = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4)); 3616 unsigned IncrementSize = NumElements * MVT::getSizeInBits(EVT)/8; 3617 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3618 getIntPtrConstant(IncrementSize)); 3619 //Is this safe? declaring that the two parts of the split load 3620 //are from the same instruction? 3621 Hi = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4)); 3622 } 3623 3624 // Build a factor node to remember that this load is independent of the 3625 // other one. 3626 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 3627 Hi.getValue(1)); 3628 3629 // Remember that we legalized the chain. 3630 AddLegalizedOperand(Op.getValue(1), TF); 3631 if (!TLI.isLittleEndian()) 3632 std::swap(Lo, Hi); 3633 break; 3634 } 3635 case ISD::VADD: 3636 case ISD::VSUB: 3637 case ISD::VMUL: { 3638 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue(); 3639 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3640 SDOperand LL, LH, RL, RH; 3641 3642 ExpandOp(Node->getOperand(0), LL, LH); 3643 ExpandOp(Node->getOperand(1), RL, RH); 3644 3645 // If we only have two elements, turn into a pair of scalar loads. 3646 // FIXME: handle case where a vector of two elements is fine, such as 3647 // 2 x double on SSE2. 3648 if (NumElements == 2) { 3649 unsigned Opc = getScalarizedOpcode(Node->getOpcode(), EVT); 3650 Lo = DAG.getNode(Opc, EVT, LL, RL); 3651 Hi = DAG.getNode(Opc, EVT, LH, RH); 3652 } else { 3653 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL, LL.getOperand(2), 3654 LL.getOperand(3)); 3655 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH, LH.getOperand(2), 3656 LH.getOperand(3)); 3657 } 3658 break; 3659 } 3660 case ISD::TAILCALL: 3661 case ISD::CALL: { 3662 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3663 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 3664 3665 bool Changed = false; 3666 std::vector<SDOperand> Ops; 3667 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 3668 Ops.push_back(LegalizeOp(Node->getOperand(i))); 3669 Changed |= Ops.back() != Node->getOperand(i); 3670 } 3671 3672 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 3673 "Can only expand a call once so far, not i64 -> i16!"); 3674 3675 std::vector<MVT::ValueType> RetTyVTs; 3676 RetTyVTs.reserve(3); 3677 RetTyVTs.push_back(NVT); 3678 RetTyVTs.push_back(NVT); 3679 RetTyVTs.push_back(MVT::Other); 3680 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee, Ops, 3681 Node->getOpcode() == ISD::TAILCALL); 3682 Lo = SDOperand(NC, 0); 3683 Hi = SDOperand(NC, 1); 3684 3685 // Insert the new chain mapping. 3686 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2)); 3687 break; 3688 } 3689 case ISD::AND: 3690 case ISD::OR: 3691 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 3692 SDOperand LL, LH, RL, RH; 3693 ExpandOp(Node->getOperand(0), LL, LH); 3694 ExpandOp(Node->getOperand(1), RL, RH); 3695 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 3696 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 3697 break; 3698 } 3699 case ISD::SELECT: { 3700 SDOperand C, LL, LH, RL, RH; 3701 3702 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3703 case Expand: assert(0 && "It's impossible to expand bools"); 3704 case Legal: 3705 C = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 3706 break; 3707 case Promote: 3708 C = PromoteOp(Node->getOperand(0)); // Promote the condition. 3709 break; 3710 } 3711 ExpandOp(Node->getOperand(1), LL, LH); 3712 ExpandOp(Node->getOperand(2), RL, RH); 3713 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL); 3714 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH); 3715 break; 3716 } 3717 case ISD::SELECT_CC: { 3718 SDOperand TL, TH, FL, FH; 3719 ExpandOp(Node->getOperand(2), TL, TH); 3720 ExpandOp(Node->getOperand(3), FL, FH); 3721 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3722 Node->getOperand(1), TL, FL, Node->getOperand(4)); 3723 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3724 Node->getOperand(1), TH, FH, Node->getOperand(4)); 3725 Lo = LegalizeOp(Lo); 3726 Hi = LegalizeOp(Hi); 3727 break; 3728 } 3729 case ISD::SEXTLOAD: { 3730 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3731 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3732 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3733 3734 if (EVT == NVT) 3735 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3736 else 3737 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3738 EVT); 3739 3740 // Remember that we legalized the chain. 3741 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3742 3743 // The high part is obtained by SRA'ing all but one of the bits of the lo 3744 // part. 3745 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 3746 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 3747 TLI.getShiftAmountTy())); 3748 Lo = LegalizeOp(Lo); 3749 Hi = LegalizeOp(Hi); 3750 break; 3751 } 3752 case ISD::ZEXTLOAD: { 3753 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3754 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3755 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3756 3757 if (EVT == NVT) 3758 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3759 else 3760 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3761 EVT); 3762 3763 // Remember that we legalized the chain. 3764 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3765 3766 // The high part is just a zero. 3767 Hi = LegalizeOp(DAG.getConstant(0, NVT)); 3768 Lo = LegalizeOp(Lo); 3769 break; 3770 } 3771 case ISD::EXTLOAD: { 3772 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3773 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3774 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3775 3776 if (EVT == NVT) 3777 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3778 else 3779 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3780 EVT); 3781 3782 // Remember that we legalized the chain. 3783 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3784 3785 // The high part is undefined. 3786 Hi = LegalizeOp(DAG.getNode(ISD::UNDEF, NVT)); 3787 Lo = LegalizeOp(Lo); 3788 break; 3789 } 3790 case ISD::ANY_EXTEND: { 3791 SDOperand In; 3792 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3793 case Expand: assert(0 && "expand-expand not implemented yet!"); 3794 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3795 case Promote: 3796 In = PromoteOp(Node->getOperand(0)); 3797 break; 3798 } 3799 3800 // The low part is any extension of the input (which degenerates to a copy). 3801 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, In); 3802 // The high part is undefined. 3803 Hi = DAG.getNode(ISD::UNDEF, NVT); 3804 break; 3805 } 3806 case ISD::SIGN_EXTEND: { 3807 SDOperand In; 3808 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3809 case Expand: assert(0 && "expand-expand not implemented yet!"); 3810 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3811 case Promote: 3812 In = PromoteOp(Node->getOperand(0)); 3813 // Emit the appropriate sign_extend_inreg to get the value we want. 3814 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), In, 3815 DAG.getValueType(Node->getOperand(0).getValueType())); 3816 break; 3817 } 3818 3819 // The low part is just a sign extension of the input (which degenerates to 3820 // a copy). 3821 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In); 3822 3823 // The high part is obtained by SRA'ing all but one of the bits of the lo 3824 // part. 3825 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 3826 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 3827 TLI.getShiftAmountTy())); 3828 break; 3829 } 3830 case ISD::ZERO_EXTEND: { 3831 SDOperand In; 3832 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3833 case Expand: assert(0 && "expand-expand not implemented yet!"); 3834 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3835 case Promote: 3836 In = PromoteOp(Node->getOperand(0)); 3837 // Emit the appropriate zero_extend_inreg to get the value we want. 3838 In = DAG.getZeroExtendInReg(In, Node->getOperand(0).getValueType()); 3839 break; 3840 } 3841 3842 // The low part is just a zero extension of the input (which degenerates to 3843 // a copy). 3844 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In); 3845 3846 // The high part is just a zero. 3847 Hi = DAG.getConstant(0, NVT); 3848 break; 3849 } 3850 3851 case ISD::BIT_CONVERT: { 3852 SDOperand Tmp = ExpandBIT_CONVERT(Node->getValueType(0), 3853 Node->getOperand(0)); 3854 ExpandOp(Tmp, Lo, Hi); 3855 break; 3856 } 3857 3858 case ISD::READCYCLECOUNTER: { 3859 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 3860 TargetLowering::Custom && 3861 "Must custom expand ReadCycleCounter"); 3862 SDOperand T = TLI.LowerOperation(Op, DAG); 3863 assert(T.Val && "Node must be custom expanded!"); 3864 Lo = LegalizeOp(T.getValue(0)); 3865 Hi = LegalizeOp(T.getValue(1)); 3866 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 3867 LegalizeOp(T.getValue(2))); 3868 break; 3869 } 3870 3871 // These operators cannot be expanded directly, emit them as calls to 3872 // library functions. 3873 case ISD::FP_TO_SINT: 3874 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 3875 SDOperand Op; 3876 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3877 case Expand: assert(0 && "cannot expand FP!"); 3878 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 3879 case Promote: Op = PromoteOp(Node->getOperand(0)); break; 3880 } 3881 3882 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 3883 3884 // Now that the custom expander is done, expand the result, which is still 3885 // VT. 3886 if (Op.Val) { 3887 ExpandOp(Op, Lo, Hi); 3888 break; 3889 } 3890 } 3891 3892 if (Node->getOperand(0).getValueType() == MVT::f32) 3893 Lo = ExpandLibCall("__fixsfdi", Node, Hi); 3894 else 3895 Lo = ExpandLibCall("__fixdfdi", Node, Hi); 3896 break; 3897 3898 case ISD::FP_TO_UINT: 3899 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 3900 SDOperand Op = DAG.getNode(ISD::FP_TO_UINT, VT, 3901 LegalizeOp(Node->getOperand(0))); 3902 // Now that the custom expander is done, expand the result, which is still 3903 // VT. 3904 Op = TLI.LowerOperation(Op, DAG); 3905 if (Op.Val) { 3906 ExpandOp(Op, Lo, Hi); 3907 break; 3908 } 3909 } 3910 3911 if (Node->getOperand(0).getValueType() == MVT::f32) 3912 Lo = ExpandLibCall("__fixunssfdi", Node, Hi); 3913 else 3914 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi); 3915 break; 3916 3917 case ISD::SHL: { 3918 // If the target wants custom lowering, do so. 3919 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 3920 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), 3921 LegalizeOp(Node->getOperand(1))); 3922 Op = TLI.LowerOperation(Op, DAG); 3923 if (Op.Val) { 3924 // Now that the custom expander is done, expand the result, which is 3925 // still VT. 3926 ExpandOp(Op, Lo, Hi); 3927 break; 3928 } 3929 } 3930 3931 // If we can emit an efficient shift operation, do so now. 3932 if (ExpandShift(ISD::SHL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3933 break; 3934 3935 // If this target supports SHL_PARTS, use it. 3936 TargetLowering::LegalizeAction Action = 3937 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 3938 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 3939 Action == TargetLowering::Custom) { 3940 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), Node->getOperand(1), 3941 Lo, Hi); 3942 break; 3943 } 3944 3945 // Otherwise, emit a libcall. 3946 Lo = ExpandLibCall("__ashldi3", Node, Hi); 3947 break; 3948 } 3949 3950 case ISD::SRA: { 3951 // If the target wants custom lowering, do so. 3952 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 3953 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), 3954 LegalizeOp(Node->getOperand(1))); 3955 Op = TLI.LowerOperation(Op, DAG); 3956 if (Op.Val) { 3957 // Now that the custom expander is done, expand the result, which is 3958 // still VT. 3959 ExpandOp(Op, Lo, Hi); 3960 break; 3961 } 3962 } 3963 3964 // If we can emit an efficient shift operation, do so now. 3965 if (ExpandShift(ISD::SRA, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3966 break; 3967 3968 // If this target supports SRA_PARTS, use it. 3969 TargetLowering::LegalizeAction Action = 3970 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 3971 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 3972 Action == TargetLowering::Custom) { 3973 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), Node->getOperand(1), 3974 Lo, Hi); 3975 break; 3976 } 3977 3978 // Otherwise, emit a libcall. 3979 Lo = ExpandLibCall("__ashrdi3", Node, Hi); 3980 break; 3981 } 3982 3983 case ISD::SRL: { 3984 // If the target wants custom lowering, do so. 3985 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 3986 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), 3987 LegalizeOp(Node->getOperand(1))); 3988 Op = TLI.LowerOperation(Op, DAG); 3989 if (Op.Val) { 3990 // Now that the custom expander is done, expand the result, which is 3991 // still VT. 3992 ExpandOp(Op, Lo, Hi); 3993 break; 3994 } 3995 } 3996 3997 // If we can emit an efficient shift operation, do so now. 3998 if (ExpandShift(ISD::SRL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3999 break; 4000 4001 // If this target supports SRL_PARTS, use it. 4002 TargetLowering::LegalizeAction Action = 4003 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 4004 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 4005 Action == TargetLowering::Custom) { 4006 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), Node->getOperand(1), 4007 Lo, Hi); 4008 break; 4009 } 4010 4011 // Otherwise, emit a libcall. 4012 Lo = ExpandLibCall("__lshrdi3", Node, Hi); 4013 break; 4014 } 4015 4016 case ISD::ADD: 4017 ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1), 4018 Lo, Hi); 4019 break; 4020 case ISD::SUB: 4021 ExpandByParts(ISD::SUB_PARTS, Node->getOperand(0), Node->getOperand(1), 4022 Lo, Hi); 4023 break; 4024 case ISD::MUL: { 4025 if (TLI.isOperationLegal(ISD::MULHU, NVT)) { 4026 SDOperand LL, LH, RL, RH; 4027 ExpandOp(Node->getOperand(0), LL, LH); 4028 ExpandOp(Node->getOperand(1), RL, RH); 4029 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1; 4030 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp 4031 // extended the sign bit of the low half through the upper half, and if so 4032 // emit a MULHS instead of the alternate sequence that is valid for any 4033 // i64 x i64 multiply. 4034 if (TLI.isOperationLegal(ISD::MULHS, NVT) && 4035 // is RH an extension of the sign bit of RL? 4036 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL && 4037 RH.getOperand(1).getOpcode() == ISD::Constant && 4038 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH && 4039 // is LH an extension of the sign bit of LL? 4040 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL && 4041 LH.getOperand(1).getOpcode() == ISD::Constant && 4042 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) { 4043 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 4044 } else { 4045 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 4046 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 4047 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 4048 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 4049 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 4050 } 4051 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 4052 } else { 4053 Lo = ExpandLibCall("__muldi3" , Node, Hi); break; 4054 } 4055 break; 4056 } 4057 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break; 4058 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break; 4059 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break; 4060 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break; 4061 } 4062 4063 // Make sure the resultant values have been legalized themselves, unless this 4064 // is a type that requires multi-step expansion. 4065 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 4066 Lo = LegalizeOp(Lo); 4067 Hi = LegalizeOp(Hi); 4068 } 4069 4070 // Remember in a map if the values will be reused later. 4071 bool isNew = 4072 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 4073 assert(isNew && "Value already expanded?!?"); 4074} 4075 4076 4077// SelectionDAG::Legalize - This is the entry point for the file. 4078// 4079void SelectionDAG::Legalize() { 4080 /// run - This is the main entry point to this class. 4081 /// 4082 SelectionDAGLegalize(*this).Run(); 4083} 4084 4085