LegalizeDAG.cpp revision fc52163a45b9ea147db1c20a1db3edff0f0bf652
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Analysis/DebugInfo.h" 15#include "llvm/CodeGen/Analysis.h" 16#include "llvm/CodeGen/MachineFunction.h" 17#include "llvm/CodeGen/MachineFrameInfo.h" 18#include "llvm/CodeGen/MachineJumpTableInfo.h" 19#include "llvm/CodeGen/MachineModuleInfo.h" 20#include "llvm/CodeGen/PseudoSourceValue.h" 21#include "llvm/CodeGen/SelectionDAG.h" 22#include "llvm/Target/TargetFrameLowering.h" 23#include "llvm/Target/TargetLowering.h" 24#include "llvm/Target/TargetData.h" 25#include "llvm/Target/TargetMachine.h" 26#include "llvm/Target/TargetOptions.h" 27#include "llvm/CallingConv.h" 28#include "llvm/Constants.h" 29#include "llvm/DerivedTypes.h" 30#include "llvm/Function.h" 31#include "llvm/GlobalVariable.h" 32#include "llvm/LLVMContext.h" 33#include "llvm/Support/CommandLine.h" 34#include "llvm/Support/Debug.h" 35#include "llvm/Support/ErrorHandling.h" 36#include "llvm/Support/MathExtras.h" 37#include "llvm/Support/raw_ostream.h" 38#include "llvm/ADT/DenseMap.h" 39#include "llvm/ADT/SmallVector.h" 40#include "llvm/ADT/SmallPtrSet.h" 41using namespace llvm; 42 43//===----------------------------------------------------------------------===// 44/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 45/// hacks on it until the target machine can handle it. This involves 46/// eliminating value sizes the machine cannot handle (promoting small sizes to 47/// large sizes or splitting up large values into small values) as well as 48/// eliminating operations the machine cannot handle. 49/// 50/// This code also does a small amount of optimization and recognition of idioms 51/// as part of its processing. For example, if a target does not support a 52/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 53/// will attempt merge setcc and brc instructions into brcc's. 54/// 55namespace { 56class SelectionDAGLegalize { 57 const TargetMachine &TM; 58 const TargetLowering &TLI; 59 SelectionDAG &DAG; 60 CodeGenOpt::Level OptLevel; 61 62 // Libcall insertion helpers. 63 64 /// LastCALLSEQ - This keeps track of the CALLSEQ_END node that has been 65 /// legalized. We use this to ensure that calls are properly serialized 66 /// against each other, including inserted libcalls. 67 SmallVector<SDValue, 8> LastCALLSEQ; 68 69 // Track CALLSEQ_BEGIN/CALLSEQ_END nesting. 70 int depthCALLSEQ; 71 72 enum LegalizeAction { 73 Legal, // The target natively supports this operation. 74 Promote, // This operation should be executed in a larger type. 75 Expand // Try to expand this to other ops, otherwise use a libcall. 76 }; 77 78 /// ValueTypeActions - This is a bitvector that contains two bits for each 79 /// value type, where the two bits correspond to the LegalizeAction enum. 80 /// This can be queried with "getTypeAction(VT)". 81 TargetLowering::ValueTypeActionImpl ValueTypeActions; 82 83 /// LegalizedNodes - For nodes that are of legal width, and that have more 84 /// than one use, this map indicates what regularized operand to use. This 85 /// allows us to avoid legalizing the same thing more than once. 86 DenseMap<SDValue, SDValue> LegalizedNodes; 87 88 void AddLegalizedOperand(SDValue From, SDValue To) { 89 LegalizedNodes.insert(std::make_pair(From, To)); 90 // If someone requests legalization of the new node, return itself. 91 if (From != To) 92 LegalizedNodes.insert(std::make_pair(To, To)); 93 94 // Transfer SDDbgValues. 95 DAG.TransferDbgValues(From, To); 96 } 97 98public: 99 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol); 100 101 /// getTypeAction - Return how we should legalize values of this type, either 102 /// it is already legal or we need to expand it into multiple registers of 103 /// smaller integer type, or we need to promote it to a larger type. 104 LegalizeAction getTypeAction(EVT VT) const { 105 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 106 } 107 108 /// isTypeLegal - Return true if this type is legal on this target. 109 /// 110 bool isTypeLegal(EVT VT) const { 111 return getTypeAction(VT) == Legal; 112 } 113 114 void LegalizeDAG(); 115 116private: 117 /// LegalizeOp - We know that the specified value has a legal type. 118 /// Recursively ensure that the operands have legal types, then return the 119 /// result. 120 SDValue LegalizeOp(SDValue O); 121 122 SDValue OptimizeFloatStore(StoreSDNode *ST); 123 124 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 125 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 126 /// is necessary to spill the vector being inserted into to memory, perform 127 /// the insert there, and then read the result back. 128 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, 129 SDValue Idx, DebugLoc dl); 130 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, 131 SDValue Idx, DebugLoc dl); 132 133 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 134 /// performs the same shuffe in terms of order or result bytes, but on a type 135 /// whose vector element type is narrower than the original shuffle type. 136 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 137 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 138 SDValue N1, SDValue N2, 139 SmallVectorImpl<int> &Mask) const; 140 141 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 142 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 143 144 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, 145 DebugLoc dl); 146 147 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned); 148 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC, 149 SDNode *Node, bool isSigned); 150 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32, 151 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80, 152 RTLIB::Libcall Call_PPCF128); 153 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned, 154 RTLIB::Libcall Call_I8, 155 RTLIB::Libcall Call_I16, 156 RTLIB::Libcall Call_I32, 157 RTLIB::Libcall Call_I64, 158 RTLIB::Libcall Call_I128); 159 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results); 160 161 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl); 162 SDValue ExpandBUILD_VECTOR(SDNode *Node); 163 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); 164 void ExpandDYNAMIC_STACKALLOC(SDNode *Node, 165 SmallVectorImpl<SDValue> &Results); 166 SDValue ExpandFCOPYSIGN(SDNode *Node); 167 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT, 168 DebugLoc dl); 169 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned, 170 DebugLoc dl); 171 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned, 172 DebugLoc dl); 173 174 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl); 175 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl); 176 177 SDValue ExpandExtractFromVectorThroughStack(SDValue Op); 178 SDValue ExpandInsertToVectorThroughStack(SDValue Op); 179 SDValue ExpandVectorBuildThroughStack(SDNode* Node); 180 181 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node); 182 183 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 184 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 185 186 SDValue getLastCALLSEQ() { return LastCALLSEQ.back(); /*[depthCALLSEQ];*/ } 187 void setLastCALLSEQ(const SDValue s) { LastCALLSEQ.back() /*[depthCALLSEQ]*/ = s; } 188 void pushLastCALLSEQ(SDValue s) { 189 depthCALLSEQ++; 190 LastCALLSEQ.push_back(s); 191 } 192 void popLastCALLSEQ() { 193 LastCALLSEQ.pop_back(); 194 depthCALLSEQ--; 195 assert(depthCALLSEQ >= 0 && "excess pop of LastCALLSEQ"); 196 } 197}; 198} 199 200/// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 201/// performs the same shuffe in terms of order or result bytes, but on a type 202/// whose vector element type is narrower than the original shuffle type. 203/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 204SDValue 205SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 206 SDValue N1, SDValue N2, 207 SmallVectorImpl<int> &Mask) const { 208 unsigned NumMaskElts = VT.getVectorNumElements(); 209 unsigned NumDestElts = NVT.getVectorNumElements(); 210 unsigned NumEltsGrowth = NumDestElts / NumMaskElts; 211 212 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 213 214 if (NumEltsGrowth == 1) 215 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]); 216 217 SmallVector<int, 8> NewMask; 218 for (unsigned i = 0; i != NumMaskElts; ++i) { 219 int Idx = Mask[i]; 220 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 221 if (Idx < 0) 222 NewMask.push_back(-1); 223 else 224 NewMask.push_back(Idx * NumEltsGrowth + j); 225 } 226 } 227 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?"); 228 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?"); 229 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]); 230} 231 232SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, 233 CodeGenOpt::Level ol) 234 : TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()), 235 DAG(dag), OptLevel(ol), 236 ValueTypeActions(TLI.getValueTypeActions()) { 237 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 238 "Too many value types for ValueTypeActions to hold!"); 239} 240 241void SelectionDAGLegalize::LegalizeDAG() { 242 depthCALLSEQ = 0; 243 pushLastCALLSEQ(DAG.getEntryNode()); 244 245 // The legalize process is inherently a bottom-up recursive process (users 246 // legalize their uses before themselves). Given infinite stack space, we 247 // could just start legalizing on the root and traverse the whole graph. In 248 // practice however, this causes us to run out of stack space on large basic 249 // blocks. To avoid this problem, compute an ordering of the nodes where each 250 // node is only legalized after all of its operands are legalized. 251 DAG.AssignTopologicalOrder(); 252 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 253 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I) 254 LegalizeOp(SDValue(I, 0)); 255 256 // Finally, it's possible the root changed. Get the new root. 257 SDValue OldRoot = DAG.getRoot(); 258 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 259 DAG.setRoot(LegalizedNodes[OldRoot]); 260 261 LegalizedNodes.clear(); 262 263 // Remove dead nodes now. 264 DAG.RemoveDeadNodes(); 265} 266 267 268/// FindCallEndFromCallStart - Given a chained node that is part of a call 269/// sequence, find the CALLSEQ_END node that terminates the call sequence. 270static SDNode *FindCallEndFromCallStart(SDNode *Node, int depth = 0) { 271 int next_depth = depth; 272 if (Node->getOpcode() == ISD::CALLSEQ_START) 273 next_depth = depth + 1; 274 if (Node->getOpcode() == ISD::CALLSEQ_END) { 275 assert(depth > 0 && "negative depth!"); 276 if (depth == 1) 277 return Node; 278 else 279 next_depth = depth - 1; 280 } 281 if (Node->use_empty()) 282 return 0; // No CallSeqEnd 283 284 // The chain is usually at the end. 285 SDValue TheChain(Node, Node->getNumValues()-1); 286 if (TheChain.getValueType() != MVT::Other) { 287 // Sometimes it's at the beginning. 288 TheChain = SDValue(Node, 0); 289 if (TheChain.getValueType() != MVT::Other) { 290 // Otherwise, hunt for it. 291 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 292 if (Node->getValueType(i) == MVT::Other) { 293 TheChain = SDValue(Node, i); 294 break; 295 } 296 297 // Otherwise, we walked into a node without a chain. 298 if (TheChain.getValueType() != MVT::Other) 299 return 0; 300 } 301 } 302 303 for (SDNode::use_iterator UI = Node->use_begin(), 304 E = Node->use_end(); UI != E; ++UI) { 305 306 // Make sure to only follow users of our token chain. 307 SDNode *User = *UI; 308 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 309 if (User->getOperand(i) == TheChain) 310 if (SDNode *Result = FindCallEndFromCallStart(User, next_depth)) 311 return Result; 312 } 313 return 0; 314} 315 316/// FindCallStartFromCallEnd - Given a chained node that is part of a call 317/// sequence, find the CALLSEQ_START node that initiates the call sequence. 318static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 319 int nested = 0; 320 assert(Node && "Didn't find callseq_start for a call??"); 321 while (Node->getOpcode() != ISD::CALLSEQ_START || nested) { 322 Node = Node->getOperand(0).getNode(); 323 assert(Node->getOperand(0).getValueType() == MVT::Other && 324 "Node doesn't have a token chain argument!"); 325 switch (Node->getOpcode()) { 326 default: 327 break; 328 case ISD::CALLSEQ_START: 329 if (!nested) 330 return Node; 331 nested--; 332 break; 333 case ISD::CALLSEQ_END: 334 nested++; 335 break; 336 } 337 } 338 return 0; 339} 340 341/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 342/// see if any uses can reach Dest. If no dest operands can get to dest, 343/// legalize them, legalize ourself, and return false, otherwise, return true. 344/// 345/// Keep track of the nodes we fine that actually do lead to Dest in 346/// NodesLeadingTo. This avoids retraversing them exponential number of times. 347/// 348bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 349 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 350 if (N == Dest) return true; // N certainly leads to Dest :) 351 352 // If we've already processed this node and it does lead to Dest, there is no 353 // need to reprocess it. 354 if (NodesLeadingTo.count(N)) return true; 355 356 // If the first result of this node has been already legalized, then it cannot 357 // reach N. 358 if (LegalizedNodes.count(SDValue(N, 0))) return false; 359 360 // Okay, this node has not already been legalized. Check and legalize all 361 // operands. If none lead to Dest, then we can legalize this node. 362 bool OperandsLeadToDest = false; 363 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 364 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 365 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, 366 NodesLeadingTo); 367 368 if (OperandsLeadToDest) { 369 NodesLeadingTo.insert(N); 370 return true; 371 } 372 373 // Okay, this node looks safe, legalize it and return false. 374 LegalizeOp(SDValue(N, 0)); 375 return false; 376} 377 378/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 379/// a load from the constant pool. 380static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 381 SelectionDAG &DAG, const TargetLowering &TLI) { 382 bool Extend = false; 383 DebugLoc dl = CFP->getDebugLoc(); 384 385 // If a FP immediate is precise when represented as a float and if the 386 // target can do an extending load from float to double, we put it into 387 // the constant pool as a float, even if it's is statically typed as a 388 // double. This shrinks FP constants and canonicalizes them for targets where 389 // an FP extending load is the same cost as a normal load (such as on the x87 390 // fp stack or PPC FP unit). 391 EVT VT = CFP->getValueType(0); 392 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue()); 393 if (!UseCP) { 394 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion"); 395 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), 396 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 397 } 398 399 EVT OrigVT = VT; 400 EVT SVT = VT; 401 while (SVT != MVT::f32) { 402 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); 403 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) && 404 // Only do this if the target has a native EXTLOAD instruction from 405 // smaller type. 406 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && 407 TLI.ShouldShrinkFPConstant(OrigVT)) { 408 const Type *SType = SVT.getTypeForEVT(*DAG.getContext()); 409 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 410 VT = SVT; 411 Extend = true; 412 } 413 } 414 415 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 416 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 417 if (Extend) 418 return DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT, 419 DAG.getEntryNode(), 420 CPIdx, MachinePointerInfo::getConstantPool(), 421 VT, false, false, Alignment); 422 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx, 423 MachinePointerInfo::getConstantPool(), false, false, 424 Alignment); 425} 426 427/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 428static 429SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 430 const TargetLowering &TLI) { 431 SDValue Chain = ST->getChain(); 432 SDValue Ptr = ST->getBasePtr(); 433 SDValue Val = ST->getValue(); 434 EVT VT = Val.getValueType(); 435 int Alignment = ST->getAlignment(); 436 DebugLoc dl = ST->getDebugLoc(); 437 if (ST->getMemoryVT().isFloatingPoint() || 438 ST->getMemoryVT().isVector()) { 439 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 440 if (TLI.isTypeLegal(intVT)) { 441 // Expand to a bitconvert of the value to the integer type of the 442 // same size, then a (misaligned) int store. 443 // FIXME: Does not handle truncating floating point stores! 444 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val); 445 return DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(), 446 ST->isVolatile(), ST->isNonTemporal(), Alignment); 447 } else { 448 // Do a (aligned) store to a stack slot, then copy from the stack slot 449 // to the final destination using (unaligned) integer loads and stores. 450 EVT StoredVT = ST->getMemoryVT(); 451 EVT RegVT = 452 TLI.getRegisterType(*DAG.getContext(), 453 EVT::getIntegerVT(*DAG.getContext(), 454 StoredVT.getSizeInBits())); 455 unsigned StoredBytes = StoredVT.getSizeInBits() / 8; 456 unsigned RegBytes = RegVT.getSizeInBits() / 8; 457 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; 458 459 // Make sure the stack slot is also aligned for the register type. 460 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); 461 462 // Perform the original store, only redirected to the stack slot. 463 SDValue Store = DAG.getTruncStore(Chain, dl, 464 Val, StackPtr, MachinePointerInfo(), 465 StoredVT, false, false, 0); 466 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 467 SmallVector<SDValue, 8> Stores; 468 unsigned Offset = 0; 469 470 // Do all but one copies using the full register width. 471 for (unsigned i = 1; i < NumRegs; i++) { 472 // Load one integer register's worth from the stack slot. 473 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, 474 MachinePointerInfo(), 475 false, false, 0); 476 // Store it to the final location. Remember the store. 477 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr, 478 ST->getPointerInfo().getWithOffset(Offset), 479 ST->isVolatile(), ST->isNonTemporal(), 480 MinAlign(ST->getAlignment(), Offset))); 481 // Increment the pointers. 482 Offset += RegBytes; 483 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 484 Increment); 485 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 486 } 487 488 // The last store may be partial. Do a truncating store. On big-endian 489 // machines this requires an extending load from the stack slot to ensure 490 // that the bits are in the right place. 491 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 492 8 * (StoredBytes - Offset)); 493 494 // Load from the stack slot. 495 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, 496 MachinePointerInfo(), 497 MemVT, false, false, 0); 498 499 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr, 500 ST->getPointerInfo() 501 .getWithOffset(Offset), 502 MemVT, ST->isVolatile(), 503 ST->isNonTemporal(), 504 MinAlign(ST->getAlignment(), Offset))); 505 // The order of the stores doesn't matter - say it with a TokenFactor. 506 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 507 Stores.size()); 508 } 509 } 510 assert(ST->getMemoryVT().isInteger() && 511 !ST->getMemoryVT().isVector() && 512 "Unaligned store of unknown type."); 513 // Get the half-size VT 514 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext()); 515 int NumBits = NewStoredVT.getSizeInBits(); 516 int IncrementSize = NumBits / 8; 517 518 // Divide the stored value in two parts. 519 SDValue ShiftAmount = DAG.getConstant(NumBits, 520 TLI.getShiftAmountTy(Val.getValueType())); 521 SDValue Lo = Val; 522 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 523 524 // Store the two parts 525 SDValue Store1, Store2; 526 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr, 527 ST->getPointerInfo(), NewStoredVT, 528 ST->isVolatile(), ST->isNonTemporal(), Alignment); 529 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 530 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 531 Alignment = MinAlign(Alignment, IncrementSize); 532 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr, 533 ST->getPointerInfo().getWithOffset(IncrementSize), 534 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(), 535 Alignment); 536 537 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); 538} 539 540/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 541static 542SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 543 const TargetLowering &TLI) { 544 SDValue Chain = LD->getChain(); 545 SDValue Ptr = LD->getBasePtr(); 546 EVT VT = LD->getValueType(0); 547 EVT LoadedVT = LD->getMemoryVT(); 548 DebugLoc dl = LD->getDebugLoc(); 549 if (VT.isFloatingPoint() || VT.isVector()) { 550 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits()); 551 if (TLI.isTypeLegal(intVT)) { 552 // Expand to a (misaligned) integer load of the same size, 553 // then bitconvert to floating point or vector. 554 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getPointerInfo(), 555 LD->isVolatile(), 556 LD->isNonTemporal(), LD->getAlignment()); 557 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad); 558 if (VT.isFloatingPoint() && LoadedVT != VT) 559 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result); 560 561 SDValue Ops[] = { Result, Chain }; 562 return DAG.getMergeValues(Ops, 2, dl); 563 } 564 565 // Copy the value to a (aligned) stack slot using (unaligned) integer 566 // loads and stores, then do a (aligned) load from the stack slot. 567 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT); 568 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8; 569 unsigned RegBytes = RegVT.getSizeInBits() / 8; 570 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; 571 572 // Make sure the stack slot is also aligned for the register type. 573 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); 574 575 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 576 SmallVector<SDValue, 8> Stores; 577 SDValue StackPtr = StackBase; 578 unsigned Offset = 0; 579 580 // Do all but one copies using the full register width. 581 for (unsigned i = 1; i < NumRegs; i++) { 582 // Load one integer register's worth from the original location. 583 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, 584 LD->getPointerInfo().getWithOffset(Offset), 585 LD->isVolatile(), LD->isNonTemporal(), 586 MinAlign(LD->getAlignment(), Offset)); 587 // Follow the load with a store to the stack slot. Remember the store. 588 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr, 589 MachinePointerInfo(), false, false, 0)); 590 // Increment the pointers. 591 Offset += RegBytes; 592 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 593 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 594 Increment); 595 } 596 597 // The last copy may be partial. Do an extending load. 598 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 599 8 * (LoadedBytes - Offset)); 600 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, 601 LD->getPointerInfo().getWithOffset(Offset), 602 MemVT, LD->isVolatile(), 603 LD->isNonTemporal(), 604 MinAlign(LD->getAlignment(), Offset)); 605 // Follow the load with a store to the stack slot. Remember the store. 606 // On big-endian machines this requires a truncating store to ensure 607 // that the bits end up in the right place. 608 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr, 609 MachinePointerInfo(), MemVT, 610 false, false, 0)); 611 612 // The order of the stores doesn't matter - say it with a TokenFactor. 613 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 614 Stores.size()); 615 616 // Finally, perform the original load only redirected to the stack slot. 617 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase, 618 MachinePointerInfo(), LoadedVT, false, false, 0); 619 620 // Callers expect a MERGE_VALUES node. 621 SDValue Ops[] = { Load, TF }; 622 return DAG.getMergeValues(Ops, 2, dl); 623 } 624 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 625 "Unaligned load of unsupported type."); 626 627 // Compute the new VT that is half the size of the old one. This is an 628 // integer MVT. 629 unsigned NumBits = LoadedVT.getSizeInBits(); 630 EVT NewLoadedVT; 631 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2); 632 NumBits >>= 1; 633 634 unsigned Alignment = LD->getAlignment(); 635 unsigned IncrementSize = NumBits / 8; 636 ISD::LoadExtType HiExtType = LD->getExtensionType(); 637 638 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 639 if (HiExtType == ISD::NON_EXTLOAD) 640 HiExtType = ISD::ZEXTLOAD; 641 642 // Load the value in two parts 643 SDValue Lo, Hi; 644 if (TLI.isLittleEndian()) { 645 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(), 646 NewLoadedVT, LD->isVolatile(), 647 LD->isNonTemporal(), Alignment); 648 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 649 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 650 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, 651 LD->getPointerInfo().getWithOffset(IncrementSize), 652 NewLoadedVT, LD->isVolatile(), 653 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize)); 654 } else { 655 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(), 656 NewLoadedVT, LD->isVolatile(), 657 LD->isNonTemporal(), Alignment); 658 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 659 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 660 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, 661 LD->getPointerInfo().getWithOffset(IncrementSize), 662 NewLoadedVT, LD->isVolatile(), 663 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize)); 664 } 665 666 // aggregate the two parts 667 SDValue ShiftAmount = DAG.getConstant(NumBits, 668 TLI.getShiftAmountTy(Hi.getValueType())); 669 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); 670 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); 671 672 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 673 Hi.getValue(1)); 674 675 SDValue Ops[] = { Result, TF }; 676 return DAG.getMergeValues(Ops, 2, dl); 677} 678 679/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 680/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 681/// is necessary to spill the vector being inserted into to memory, perform 682/// the insert there, and then read the result back. 683SDValue SelectionDAGLegalize:: 684PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx, 685 DebugLoc dl) { 686 SDValue Tmp1 = Vec; 687 SDValue Tmp2 = Val; 688 SDValue Tmp3 = Idx; 689 690 // If the target doesn't support this, we have to spill the input vector 691 // to a temporary stack slot, update the element, then reload it. This is 692 // badness. We could also load the value into a vector register (either 693 // with a "move to register" or "extload into register" instruction, then 694 // permute it into place, if the idx is a constant and if the idx is 695 // supported by the target. 696 EVT VT = Tmp1.getValueType(); 697 EVT EltVT = VT.getVectorElementType(); 698 EVT IdxVT = Tmp3.getValueType(); 699 EVT PtrVT = TLI.getPointerTy(); 700 SDValue StackPtr = DAG.CreateStackTemporary(VT); 701 702 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 703 704 // Store the vector. 705 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr, 706 MachinePointerInfo::getFixedStack(SPFI), 707 false, false, 0); 708 709 // Truncate or zero extend offset to target pointer type. 710 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 711 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3); 712 // Add the offset to the index. 713 unsigned EltSize = EltVT.getSizeInBits()/8; 714 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 715 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr); 716 // Store the scalar value. 717 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT, 718 false, false, 0); 719 // Load the updated vector. 720 return DAG.getLoad(VT, dl, Ch, StackPtr, 721 MachinePointerInfo::getFixedStack(SPFI), false, false, 0); 722} 723 724 725SDValue SelectionDAGLegalize:: 726ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) { 727 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) { 728 // SCALAR_TO_VECTOR requires that the type of the value being inserted 729 // match the element type of the vector being created, except for 730 // integers in which case the inserted value can be over width. 731 EVT EltVT = Vec.getValueType().getVectorElementType(); 732 if (Val.getValueType() == EltVT || 733 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) { 734 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 735 Vec.getValueType(), Val); 736 737 unsigned NumElts = Vec.getValueType().getVectorNumElements(); 738 // We generate a shuffle of InVec and ScVec, so the shuffle mask 739 // should be 0,1,2,3,4,5... with the appropriate element replaced with 740 // elt 0 of the RHS. 741 SmallVector<int, 8> ShufOps; 742 for (unsigned i = 0; i != NumElts; ++i) 743 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts); 744 745 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec, 746 &ShufOps[0]); 747 } 748 } 749 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl); 750} 751 752SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) { 753 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 754 // FIXME: We shouldn't do this for TargetConstantFP's. 755 // FIXME: move this to the DAG Combiner! Note that we can't regress due 756 // to phase ordering between legalized code and the dag combiner. This 757 // probably means that we need to integrate dag combiner and legalizer 758 // together. 759 // We generally can't do this one for long doubles. 760 SDValue Tmp1 = ST->getChain(); 761 SDValue Tmp2 = ST->getBasePtr(); 762 SDValue Tmp3; 763 unsigned Alignment = ST->getAlignment(); 764 bool isVolatile = ST->isVolatile(); 765 bool isNonTemporal = ST->isNonTemporal(); 766 DebugLoc dl = ST->getDebugLoc(); 767 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 768 if (CFP->getValueType(0) == MVT::f32 && 769 getTypeAction(MVT::i32) == Legal) { 770 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 771 bitcastToAPInt().zextOrTrunc(32), 772 MVT::i32); 773 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), 774 isVolatile, isNonTemporal, Alignment); 775 } 776 777 if (CFP->getValueType(0) == MVT::f64) { 778 // If this target supports 64-bit registers, do a single 64-bit store. 779 if (getTypeAction(MVT::i64) == Legal) { 780 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 781 zextOrTrunc(64), MVT::i64); 782 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), 783 isVolatile, isNonTemporal, Alignment); 784 } 785 786 if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) { 787 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 788 // stores. If the target supports neither 32- nor 64-bits, this 789 // xform is certainly not worth it. 790 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt(); 791 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32); 792 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 793 if (TLI.isBigEndian()) std::swap(Lo, Hi); 794 795 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getPointerInfo(), isVolatile, 796 isNonTemporal, Alignment); 797 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 798 DAG.getIntPtrConstant(4)); 799 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, 800 ST->getPointerInfo().getWithOffset(4), 801 isVolatile, isNonTemporal, MinAlign(Alignment, 4U)); 802 803 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 804 } 805 } 806 } 807 return SDValue(0, 0); 808} 809 810/// LegalizeOp - We know that the specified value has a legal type, and 811/// that its operands are legal. Now ensure that the operation itself 812/// is legal, recursively ensuring that the operands' operations remain 813/// legal. 814SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { 815 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 816 return Op; 817 818 SDNode *Node = Op.getNode(); 819 DebugLoc dl = Node->getDebugLoc(); 820 821 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 822 assert(getTypeAction(Node->getValueType(i)) == Legal && 823 "Unexpected illegal type!"); 824 825 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 826 assert((isTypeLegal(Node->getOperand(i).getValueType()) || 827 Node->getOperand(i).getOpcode() == ISD::TargetConstant) && 828 "Unexpected illegal type!"); 829 830 // Note that LegalizeOp may be reentered even from single-use nodes, which 831 // means that we always must cache transformed nodes. 832 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 833 if (I != LegalizedNodes.end()) return I->second; 834 835 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 836 SDValue Result = Op; 837 bool isCustom = false; 838 839 // Figure out the correct action; the way to query this varies by opcode 840 TargetLowering::LegalizeAction Action = TargetLowering::Legal; 841 bool SimpleFinishLegalizing = true; 842 switch (Node->getOpcode()) { 843 case ISD::INTRINSIC_W_CHAIN: 844 case ISD::INTRINSIC_WO_CHAIN: 845 case ISD::INTRINSIC_VOID: 846 case ISD::VAARG: 847 case ISD::STACKSAVE: 848 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other); 849 break; 850 case ISD::SINT_TO_FP: 851 case ISD::UINT_TO_FP: 852 case ISD::EXTRACT_VECTOR_ELT: 853 Action = TLI.getOperationAction(Node->getOpcode(), 854 Node->getOperand(0).getValueType()); 855 break; 856 case ISD::FP_ROUND_INREG: 857 case ISD::SIGN_EXTEND_INREG: { 858 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT(); 859 Action = TLI.getOperationAction(Node->getOpcode(), InnerType); 860 break; 861 } 862 case ISD::SELECT_CC: 863 case ISD::SETCC: 864 case ISD::BR_CC: { 865 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 : 866 Node->getOpcode() == ISD::SETCC ? 2 : 1; 867 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0; 868 EVT OpVT = Node->getOperand(CompareOperand).getValueType(); 869 ISD::CondCode CCCode = 870 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get(); 871 Action = TLI.getCondCodeAction(CCCode, OpVT); 872 if (Action == TargetLowering::Legal) { 873 if (Node->getOpcode() == ISD::SELECT_CC) 874 Action = TLI.getOperationAction(Node->getOpcode(), 875 Node->getValueType(0)); 876 else 877 Action = TLI.getOperationAction(Node->getOpcode(), OpVT); 878 } 879 break; 880 } 881 case ISD::LOAD: 882 case ISD::STORE: 883 // FIXME: Model these properly. LOAD and STORE are complicated, and 884 // STORE expects the unlegalized operand in some cases. 885 SimpleFinishLegalizing = false; 886 break; 887 case ISD::CALLSEQ_START: 888 case ISD::CALLSEQ_END: 889 // FIXME: This shouldn't be necessary. These nodes have special properties 890 // dealing with the recursive nature of legalization. Removing this 891 // special case should be done as part of making LegalizeDAG non-recursive. 892 SimpleFinishLegalizing = false; 893 break; 894 case ISD::EXTRACT_ELEMENT: 895 case ISD::FLT_ROUNDS_: 896 case ISD::SADDO: 897 case ISD::SSUBO: 898 case ISD::UADDO: 899 case ISD::USUBO: 900 case ISD::SMULO: 901 case ISD::UMULO: 902 case ISD::FPOWI: 903 case ISD::MERGE_VALUES: 904 case ISD::EH_RETURN: 905 case ISD::FRAME_TO_ARGS_OFFSET: 906 case ISD::EH_SJLJ_SETJMP: 907 case ISD::EH_SJLJ_LONGJMP: 908 case ISD::EH_SJLJ_DISPATCHSETUP: 909 // These operations lie about being legal: when they claim to be legal, 910 // they should actually be expanded. 911 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 912 if (Action == TargetLowering::Legal) 913 Action = TargetLowering::Expand; 914 break; 915 case ISD::TRAMPOLINE: 916 case ISD::FRAMEADDR: 917 case ISD::RETURNADDR: 918 // These operations lie about being legal: when they claim to be legal, 919 // they should actually be custom-lowered. 920 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 921 if (Action == TargetLowering::Legal) 922 Action = TargetLowering::Custom; 923 break; 924 case ISD::BUILD_VECTOR: 925 // A weird case: legalization for BUILD_VECTOR never legalizes the 926 // operands! 927 // FIXME: This really sucks... changing it isn't semantically incorrect, 928 // but it massively pessimizes the code for floating-point BUILD_VECTORs 929 // because ConstantFP operands get legalized into constant pool loads 930 // before the BUILD_VECTOR code can see them. It doesn't usually bite, 931 // though, because BUILD_VECTORS usually get lowered into other nodes 932 // which get legalized properly. 933 SimpleFinishLegalizing = false; 934 break; 935 default: 936 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 937 Action = TargetLowering::Legal; 938 } else { 939 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 940 } 941 break; 942 } 943 944 if (SimpleFinishLegalizing) { 945 SmallVector<SDValue, 8> Ops, ResultVals; 946 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 947 Ops.push_back(LegalizeOp(Node->getOperand(i))); 948 switch (Node->getOpcode()) { 949 default: break; 950 case ISD::BR: 951 case ISD::BRIND: 952 case ISD::BR_JT: 953 case ISD::BR_CC: 954 case ISD::BRCOND: 955 assert(depthCALLSEQ == 1 && "branch inside CALLSEQ_BEGIN/END?"); 956 // Branches tweak the chain to include LastCALLSEQ 957 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0], 958 getLastCALLSEQ()); 959 Ops[0] = LegalizeOp(Ops[0]); 960 setLastCALLSEQ(DAG.getEntryNode()); 961 break; 962 case ISD::SHL: 963 case ISD::SRL: 964 case ISD::SRA: 965 case ISD::ROTL: 966 case ISD::ROTR: 967 // Legalizing shifts/rotates requires adjusting the shift amount 968 // to the appropriate width. 969 if (!Ops[1].getValueType().isVector()) 970 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[0].getValueType(), 971 Ops[1])); 972 break; 973 case ISD::SRL_PARTS: 974 case ISD::SRA_PARTS: 975 case ISD::SHL_PARTS: 976 // Legalizing shifts/rotates requires adjusting the shift amount 977 // to the appropriate width. 978 if (!Ops[2].getValueType().isVector()) 979 Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[0].getValueType(), 980 Ops[2])); 981 break; 982 } 983 984 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), Ops.data(), 985 Ops.size()), 0); 986 switch (Action) { 987 case TargetLowering::Legal: 988 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 989 ResultVals.push_back(Result.getValue(i)); 990 break; 991 case TargetLowering::Custom: 992 // FIXME: The handling for custom lowering with multiple results is 993 // a complete mess. 994 Tmp1 = TLI.LowerOperation(Result, DAG); 995 if (Tmp1.getNode()) { 996 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 997 if (e == 1) 998 ResultVals.push_back(Tmp1); 999 else 1000 ResultVals.push_back(Tmp1.getValue(i)); 1001 } 1002 break; 1003 } 1004 1005 // FALL THROUGH 1006 case TargetLowering::Expand: 1007 ExpandNode(Result.getNode(), ResultVals); 1008 break; 1009 case TargetLowering::Promote: 1010 PromoteNode(Result.getNode(), ResultVals); 1011 break; 1012 } 1013 if (!ResultVals.empty()) { 1014 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) { 1015 if (ResultVals[i] != SDValue(Node, i)) 1016 ResultVals[i] = LegalizeOp(ResultVals[i]); 1017 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]); 1018 } 1019 return ResultVals[Op.getResNo()]; 1020 } 1021 } 1022 1023 switch (Node->getOpcode()) { 1024 default: 1025#ifndef NDEBUG 1026 dbgs() << "NODE: "; 1027 Node->dump( &DAG); 1028 dbgs() << "\n"; 1029#endif 1030 assert(0 && "Do not know how to legalize this operator!"); 1031 1032 case ISD::BUILD_VECTOR: 1033 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 1034 default: assert(0 && "This action is not supported yet!"); 1035 case TargetLowering::Custom: 1036 Tmp3 = TLI.LowerOperation(Result, DAG); 1037 if (Tmp3.getNode()) { 1038 Result = Tmp3; 1039 break; 1040 } 1041 // FALLTHROUGH 1042 case TargetLowering::Expand: 1043 Result = ExpandBUILD_VECTOR(Result.getNode()); 1044 break; 1045 } 1046 break; 1047 case ISD::CALLSEQ_START: { 1048 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1049 assert(CallEnd && "didn't find CALLSEQ_END!"); 1050 1051 // Recursively Legalize all of the inputs of the call end that do not lead 1052 // to this call start. This ensures that any libcalls that need be inserted 1053 // are inserted *before* the CALLSEQ_START. 1054 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1055 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1056 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node, 1057 NodesLeadingTo); 1058 } 1059 1060 // Now that we have legalized all of the inputs (which may have inserted 1061 // libcalls), create the new CALLSEQ_START node. 1062 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1063 1064 // Merge in the last call to ensure that this call starts after the last 1065 // call ended. 1066 if (getLastCALLSEQ().getOpcode() != ISD::EntryToken) { 1067 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1068 Tmp1, getLastCALLSEQ()); 1069 Tmp1 = LegalizeOp(Tmp1); 1070 } 1071 1072 // Do not try to legalize the target-specific arguments (#1+). 1073 if (Tmp1 != Node->getOperand(0)) { 1074 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1075 Ops[0] = Tmp1; 1076 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), &Ops[0], 1077 Ops.size()), Result.getResNo()); 1078 } 1079 1080 // Remember that the CALLSEQ_START is legalized. 1081 AddLegalizedOperand(Op.getValue(0), Result); 1082 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1083 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1084 1085 // Now that the callseq_start and all of the non-call nodes above this call 1086 // sequence have been legalized, legalize the call itself. During this 1087 // process, no libcalls can/will be inserted, guaranteeing that no calls 1088 // can overlap. 1089 // Note that we are selecting this call! 1090 setLastCALLSEQ(SDValue(CallEnd, 0)); 1091 1092 // Legalize the call, starting from the CALLSEQ_END. 1093 LegalizeOp(getLastCALLSEQ()); 1094 return Result; 1095 } 1096 case ISD::CALLSEQ_END: 1097 { 1098 SDNode *myCALLSEQ_BEGIN = FindCallStartFromCallEnd(Node); 1099 1100 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1101 // will cause this node to be legalized as well as handling libcalls right. 1102 if (getLastCALLSEQ().getNode() != Node) { 1103 LegalizeOp(SDValue(myCALLSEQ_BEGIN, 0)); 1104 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 1105 assert(I != LegalizedNodes.end() && 1106 "Legalizing the call start should have legalized this node!"); 1107 return I->second; 1108 } 1109 1110 pushLastCALLSEQ(SDValue(myCALLSEQ_BEGIN, 0)); 1111 } 1112 1113 // Otherwise, the call start has been legalized and everything is going 1114 // according to plan. Just legalize ourselves normally here. 1115 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1116 // Do not try to legalize the target-specific arguments (#1+), except for 1117 // an optional flag input. 1118 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Glue){ 1119 if (Tmp1 != Node->getOperand(0)) { 1120 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1121 Ops[0] = Tmp1; 1122 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1123 &Ops[0], Ops.size()), 1124 Result.getResNo()); 1125 } 1126 } else { 1127 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1128 if (Tmp1 != Node->getOperand(0) || 1129 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1130 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1131 Ops[0] = Tmp1; 1132 Ops.back() = Tmp2; 1133 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1134 &Ops[0], Ops.size()), 1135 Result.getResNo()); 1136 } 1137 } 1138 // This finishes up call legalization. 1139 popLastCALLSEQ(); 1140 1141 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1142 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1143 if (Node->getNumValues() == 2) 1144 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1145 return Result.getValue(Op.getResNo()); 1146 case ISD::LOAD: { 1147 LoadSDNode *LD = cast<LoadSDNode>(Node); 1148 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1149 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1150 1151 ISD::LoadExtType ExtType = LD->getExtensionType(); 1152 if (ExtType == ISD::NON_EXTLOAD) { 1153 EVT VT = Node->getValueType(0); 1154 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1155 Tmp1, Tmp2, LD->getOffset()), 1156 Result.getResNo()); 1157 Tmp3 = Result.getValue(0); 1158 Tmp4 = Result.getValue(1); 1159 1160 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1161 default: assert(0 && "This action is not supported yet!"); 1162 case TargetLowering::Legal: 1163 // If this is an unaligned load and the target doesn't support it, 1164 // expand it. 1165 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 1166 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1167 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1168 if (LD->getAlignment() < ABIAlignment){ 1169 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), 1170 DAG, TLI); 1171 Tmp3 = Result.getOperand(0); 1172 Tmp4 = Result.getOperand(1); 1173 Tmp3 = LegalizeOp(Tmp3); 1174 Tmp4 = LegalizeOp(Tmp4); 1175 } 1176 } 1177 break; 1178 case TargetLowering::Custom: 1179 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1180 if (Tmp1.getNode()) { 1181 Tmp3 = LegalizeOp(Tmp1); 1182 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1183 } 1184 break; 1185 case TargetLowering::Promote: { 1186 // Only promote a load of vector type to another. 1187 assert(VT.isVector() && "Cannot promote this load!"); 1188 // Change base type to a different vector type. 1189 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1190 1191 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getPointerInfo(), 1192 LD->isVolatile(), LD->isNonTemporal(), 1193 LD->getAlignment()); 1194 Tmp3 = LegalizeOp(DAG.getNode(ISD::BITCAST, dl, VT, Tmp1)); 1195 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1196 break; 1197 } 1198 } 1199 // Since loads produce two values, make sure to remember that we 1200 // legalized both of them. 1201 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 1202 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 1203 return Op.getResNo() ? Tmp4 : Tmp3; 1204 } 1205 1206 EVT SrcVT = LD->getMemoryVT(); 1207 unsigned SrcWidth = SrcVT.getSizeInBits(); 1208 unsigned Alignment = LD->getAlignment(); 1209 bool isVolatile = LD->isVolatile(); 1210 bool isNonTemporal = LD->isNonTemporal(); 1211 1212 if (SrcWidth != SrcVT.getStoreSizeInBits() && 1213 // Some targets pretend to have an i1 loading operation, and actually 1214 // load an i8. This trick is correct for ZEXTLOAD because the top 7 1215 // bits are guaranteed to be zero; it helps the optimizers understand 1216 // that these bits are zero. It is also useful for EXTLOAD, since it 1217 // tells the optimizers that those bits are undefined. It would be 1218 // nice to have an effective generic way of getting these benefits... 1219 // Until such a way is found, don't insist on promoting i1 here. 1220 (SrcVT != MVT::i1 || 1221 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 1222 // Promote to a byte-sized load if not loading an integral number of 1223 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 1224 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 1225 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth); 1226 SDValue Ch; 1227 1228 // The extra bits are guaranteed to be zero, since we stored them that 1229 // way. A zext load from NVT thus automatically gives zext from SrcVT. 1230 1231 ISD::LoadExtType NewExtType = 1232 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 1233 1234 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0), 1235 Tmp1, Tmp2, LD->getPointerInfo(), 1236 NVT, isVolatile, isNonTemporal, Alignment); 1237 1238 Ch = Result.getValue(1); // The chain. 1239 1240 if (ExtType == ISD::SEXTLOAD) 1241 // Having the top bits zero doesn't help when sign extending. 1242 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1243 Result.getValueType(), 1244 Result, DAG.getValueType(SrcVT)); 1245 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 1246 // All the top bits are guaranteed to be zero - inform the optimizers. 1247 Result = DAG.getNode(ISD::AssertZext, dl, 1248 Result.getValueType(), Result, 1249 DAG.getValueType(SrcVT)); 1250 1251 Tmp1 = LegalizeOp(Result); 1252 Tmp2 = LegalizeOp(Ch); 1253 } else if (SrcWidth & (SrcWidth - 1)) { 1254 // If not loading a power-of-2 number of bits, expand as two loads. 1255 assert(!SrcVT.isVector() && "Unsupported extload!"); 1256 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 1257 assert(RoundWidth < SrcWidth); 1258 unsigned ExtraWidth = SrcWidth - RoundWidth; 1259 assert(ExtraWidth < RoundWidth); 1260 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1261 "Load size not an integral number of bytes!"); 1262 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 1263 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 1264 SDValue Lo, Hi, Ch; 1265 unsigned IncrementSize; 1266 1267 if (TLI.isLittleEndian()) { 1268 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 1269 // Load the bottom RoundWidth bits. 1270 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), 1271 Tmp1, Tmp2, 1272 LD->getPointerInfo(), RoundVT, isVolatile, 1273 isNonTemporal, Alignment); 1274 1275 // Load the remaining ExtraWidth bits. 1276 IncrementSize = RoundWidth / 8; 1277 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1278 DAG.getIntPtrConstant(IncrementSize)); 1279 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 1280 LD->getPointerInfo().getWithOffset(IncrementSize), 1281 ExtraVT, isVolatile, isNonTemporal, 1282 MinAlign(Alignment, IncrementSize)); 1283 1284 // Build a factor node to remember that this load is independent of 1285 // the other one. 1286 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1287 Hi.getValue(1)); 1288 1289 // Move the top bits to the right place. 1290 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1291 DAG.getConstant(RoundWidth, 1292 TLI.getShiftAmountTy(Hi.getValueType()))); 1293 1294 // Join the hi and lo parts. 1295 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1296 } else { 1297 // Big endian - avoid unaligned loads. 1298 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 1299 // Load the top RoundWidth bits. 1300 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 1301 LD->getPointerInfo(), RoundVT, isVolatile, 1302 isNonTemporal, Alignment); 1303 1304 // Load the remaining ExtraWidth bits. 1305 IncrementSize = RoundWidth / 8; 1306 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1307 DAG.getIntPtrConstant(IncrementSize)); 1308 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, 1309 dl, Node->getValueType(0), Tmp1, Tmp2, 1310 LD->getPointerInfo().getWithOffset(IncrementSize), 1311 ExtraVT, isVolatile, isNonTemporal, 1312 MinAlign(Alignment, IncrementSize)); 1313 1314 // Build a factor node to remember that this load is independent of 1315 // the other one. 1316 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1317 Hi.getValue(1)); 1318 1319 // Move the top bits to the right place. 1320 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1321 DAG.getConstant(ExtraWidth, 1322 TLI.getShiftAmountTy(Hi.getValueType()))); 1323 1324 // Join the hi and lo parts. 1325 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1326 } 1327 1328 Tmp1 = LegalizeOp(Result); 1329 Tmp2 = LegalizeOp(Ch); 1330 } else { 1331 switch (TLI.getLoadExtAction(ExtType, SrcVT)) { 1332 default: assert(0 && "This action is not supported yet!"); 1333 case TargetLowering::Custom: 1334 isCustom = true; 1335 // FALLTHROUGH 1336 case TargetLowering::Legal: 1337 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1338 Tmp1, Tmp2, LD->getOffset()), 1339 Result.getResNo()); 1340 Tmp1 = Result.getValue(0); 1341 Tmp2 = Result.getValue(1); 1342 1343 if (isCustom) { 1344 Tmp3 = TLI.LowerOperation(Result, DAG); 1345 if (Tmp3.getNode()) { 1346 Tmp1 = LegalizeOp(Tmp3); 1347 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1348 } 1349 } else { 1350 // If this is an unaligned load and the target doesn't support it, 1351 // expand it. 1352 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 1353 const Type *Ty = 1354 LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1355 unsigned ABIAlignment = 1356 TLI.getTargetData()->getABITypeAlignment(Ty); 1357 if (LD->getAlignment() < ABIAlignment){ 1358 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), 1359 DAG, TLI); 1360 Tmp1 = Result.getOperand(0); 1361 Tmp2 = Result.getOperand(1); 1362 Tmp1 = LegalizeOp(Tmp1); 1363 Tmp2 = LegalizeOp(Tmp2); 1364 } 1365 } 1366 } 1367 break; 1368 case TargetLowering::Expand: 1369 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && isTypeLegal(SrcVT)) { 1370 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, 1371 LD->getPointerInfo(), 1372 LD->isVolatile(), LD->isNonTemporal(), 1373 LD->getAlignment()); 1374 unsigned ExtendOp; 1375 switch (ExtType) { 1376 case ISD::EXTLOAD: 1377 ExtendOp = (SrcVT.isFloatingPoint() ? 1378 ISD::FP_EXTEND : ISD::ANY_EXTEND); 1379 break; 1380 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break; 1381 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break; 1382 default: llvm_unreachable("Unexpected extend load type!"); 1383 } 1384 Result = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load); 1385 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1386 Tmp2 = LegalizeOp(Load.getValue(1)); 1387 break; 1388 } 1389 // FIXME: This does not work for vectors on most targets. Sign- and 1390 // zero-extend operations are currently folded into extending loads, 1391 // whether they are legal or not, and then we end up here without any 1392 // support for legalizing them. 1393 assert(ExtType != ISD::EXTLOAD && 1394 "EXTLOAD should always be supported!"); 1395 // Turn the unsupported load into an EXTLOAD followed by an explicit 1396 // zero/sign extend inreg. 1397 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0), 1398 Tmp1, Tmp2, LD->getPointerInfo(), SrcVT, 1399 LD->isVolatile(), LD->isNonTemporal(), 1400 LD->getAlignment()); 1401 SDValue ValRes; 1402 if (ExtType == ISD::SEXTLOAD) 1403 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1404 Result.getValueType(), 1405 Result, DAG.getValueType(SrcVT)); 1406 else 1407 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType()); 1408 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1409 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1410 break; 1411 } 1412 } 1413 1414 // Since loads produce two values, make sure to remember that we legalized 1415 // both of them. 1416 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 1417 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 1418 return Op.getResNo() ? Tmp2 : Tmp1; 1419 } 1420 case ISD::STORE: { 1421 StoreSDNode *ST = cast<StoreSDNode>(Node); 1422 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 1423 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 1424 unsigned Alignment = ST->getAlignment(); 1425 bool isVolatile = ST->isVolatile(); 1426 bool isNonTemporal = ST->isNonTemporal(); 1427 1428 if (!ST->isTruncatingStore()) { 1429 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) { 1430 Result = SDValue(OptStore, 0); 1431 break; 1432 } 1433 1434 { 1435 Tmp3 = LegalizeOp(ST->getValue()); 1436 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1437 Tmp1, Tmp3, Tmp2, 1438 ST->getOffset()), 1439 Result.getResNo()); 1440 1441 EVT VT = Tmp3.getValueType(); 1442 switch (TLI.getOperationAction(ISD::STORE, VT)) { 1443 default: assert(0 && "This action is not supported yet!"); 1444 case TargetLowering::Legal: 1445 // If this is an unaligned store and the target doesn't support it, 1446 // expand it. 1447 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 1448 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1449 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty); 1450 if (ST->getAlignment() < ABIAlignment) 1451 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), 1452 DAG, TLI); 1453 } 1454 break; 1455 case TargetLowering::Custom: 1456 Tmp1 = TLI.LowerOperation(Result, DAG); 1457 if (Tmp1.getNode()) Result = Tmp1; 1458 break; 1459 case TargetLowering::Promote: 1460 assert(VT.isVector() && "Unknown legal promote case!"); 1461 Tmp3 = DAG.getNode(ISD::BITCAST, dl, 1462 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 1463 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, 1464 ST->getPointerInfo(), isVolatile, 1465 isNonTemporal, Alignment); 1466 break; 1467 } 1468 break; 1469 } 1470 } else { 1471 Tmp3 = LegalizeOp(ST->getValue()); 1472 1473 EVT StVT = ST->getMemoryVT(); 1474 unsigned StWidth = StVT.getSizeInBits(); 1475 1476 if (StWidth != StVT.getStoreSizeInBits()) { 1477 // Promote to a byte-sized store with upper bits zero if not 1478 // storing an integral number of bytes. For example, promote 1479 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 1480 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), 1481 StVT.getStoreSizeInBits()); 1482 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT); 1483 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), 1484 NVT, isVolatile, isNonTemporal, Alignment); 1485 } else if (StWidth & (StWidth - 1)) { 1486 // If not storing a power-of-2 number of bits, expand as two stores. 1487 assert(!StVT.isVector() && "Unsupported truncstore!"); 1488 unsigned RoundWidth = 1 << Log2_32(StWidth); 1489 assert(RoundWidth < StWidth); 1490 unsigned ExtraWidth = StWidth - RoundWidth; 1491 assert(ExtraWidth < RoundWidth); 1492 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1493 "Store size not an integral number of bytes!"); 1494 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 1495 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 1496 SDValue Lo, Hi; 1497 unsigned IncrementSize; 1498 1499 if (TLI.isLittleEndian()) { 1500 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 1501 // Store the bottom RoundWidth bits. 1502 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), 1503 RoundVT, 1504 isVolatile, isNonTemporal, Alignment); 1505 1506 // Store the remaining ExtraWidth bits. 1507 IncrementSize = RoundWidth / 8; 1508 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1509 DAG.getIntPtrConstant(IncrementSize)); 1510 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1511 DAG.getConstant(RoundWidth, 1512 TLI.getShiftAmountTy(Tmp3.getValueType()))); 1513 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, 1514 ST->getPointerInfo().getWithOffset(IncrementSize), 1515 ExtraVT, isVolatile, isNonTemporal, 1516 MinAlign(Alignment, IncrementSize)); 1517 } else { 1518 // Big endian - avoid unaligned stores. 1519 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 1520 // Store the top RoundWidth bits. 1521 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1522 DAG.getConstant(ExtraWidth, 1523 TLI.getShiftAmountTy(Tmp3.getValueType()))); 1524 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getPointerInfo(), 1525 RoundVT, isVolatile, isNonTemporal, Alignment); 1526 1527 // Store the remaining ExtraWidth bits. 1528 IncrementSize = RoundWidth / 8; 1529 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1530 DAG.getIntPtrConstant(IncrementSize)); 1531 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, 1532 ST->getPointerInfo().getWithOffset(IncrementSize), 1533 ExtraVT, isVolatile, isNonTemporal, 1534 MinAlign(Alignment, IncrementSize)); 1535 } 1536 1537 // The order of the stores doesn't matter. 1538 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 1539 } else { 1540 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 1541 Tmp2 != ST->getBasePtr()) 1542 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1543 Tmp1, Tmp3, Tmp2, 1544 ST->getOffset()), 1545 Result.getResNo()); 1546 1547 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 1548 default: assert(0 && "This action is not supported yet!"); 1549 case TargetLowering::Legal: 1550 // If this is an unaligned store and the target doesn't support it, 1551 // expand it. 1552 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 1553 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1554 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty); 1555 if (ST->getAlignment() < ABIAlignment) 1556 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), 1557 DAG, TLI); 1558 } 1559 break; 1560 case TargetLowering::Custom: 1561 Result = TLI.LowerOperation(Result, DAG); 1562 break; 1563 case Expand: 1564 // TRUNCSTORE:i16 i32 -> STORE i16 1565 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 1566 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3); 1567 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), 1568 isVolatile, isNonTemporal, Alignment); 1569 break; 1570 } 1571 } 1572 } 1573 break; 1574 } 1575 } 1576 assert(Result.getValueType() == Op.getValueType() && 1577 "Bad legalization!"); 1578 1579 // Make sure that the generated code is itself legal. 1580 if (Result != Op) 1581 Result = LegalizeOp(Result); 1582 1583 // Note that LegalizeOp may be reentered even from single-use nodes, which 1584 // means that we always must cache transformed nodes. 1585 AddLegalizedOperand(Op, Result); 1586 return Result; 1587} 1588 1589SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) { 1590 SDValue Vec = Op.getOperand(0); 1591 SDValue Idx = Op.getOperand(1); 1592 DebugLoc dl = Op.getDebugLoc(); 1593 // Store the value to a temporary stack slot, then LOAD the returned part. 1594 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 1595 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, 1596 MachinePointerInfo(), false, false, 0); 1597 1598 // Add the offset to the index. 1599 unsigned EltSize = 1600 Vec.getValueType().getVectorElementType().getSizeInBits()/8; 1601 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, 1602 DAG.getConstant(EltSize, Idx.getValueType())); 1603 1604 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 1605 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); 1606 else 1607 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); 1608 1609 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr); 1610 1611 if (Op.getValueType().isVector()) 1612 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(), 1613 false, false, 0); 1614 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr, 1615 MachinePointerInfo(), 1616 Vec.getValueType().getVectorElementType(), 1617 false, false, 0); 1618} 1619 1620SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) { 1621 assert(Op.getValueType().isVector() && "Non-vector insert subvector!"); 1622 1623 SDValue Vec = Op.getOperand(0); 1624 SDValue Part = Op.getOperand(1); 1625 SDValue Idx = Op.getOperand(2); 1626 DebugLoc dl = Op.getDebugLoc(); 1627 1628 // Store the value to a temporary stack slot, then LOAD the returned part. 1629 1630 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 1631 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 1632 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI); 1633 1634 // First store the whole vector. 1635 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo, 1636 false, false, 0); 1637 1638 // Then store the inserted part. 1639 1640 // Add the offset to the index. 1641 unsigned EltSize = 1642 Vec.getValueType().getVectorElementType().getSizeInBits()/8; 1643 1644 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, 1645 DAG.getConstant(EltSize, Idx.getValueType())); 1646 1647 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 1648 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); 1649 else 1650 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); 1651 1652 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, 1653 StackPtr); 1654 1655 // Store the subvector. 1656 Ch = DAG.getStore(DAG.getEntryNode(), dl, Part, SubStackPtr, 1657 MachinePointerInfo(), false, false, 0); 1658 1659 // Finally, load the updated vector. 1660 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo, 1661 false, false, 0); 1662} 1663 1664SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) { 1665 // We can't handle this case efficiently. Allocate a sufficiently 1666 // aligned object on the stack, store each element into it, then load 1667 // the result as a vector. 1668 // Create the stack frame object. 1669 EVT VT = Node->getValueType(0); 1670 EVT EltVT = VT.getVectorElementType(); 1671 DebugLoc dl = Node->getDebugLoc(); 1672 SDValue FIPtr = DAG.CreateStackTemporary(VT); 1673 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex(); 1674 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI); 1675 1676 // Emit a store of each element to the stack slot. 1677 SmallVector<SDValue, 8> Stores; 1678 unsigned TypeByteSize = EltVT.getSizeInBits() / 8; 1679 // Store (in the right endianness) the elements to memory. 1680 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1681 // Ignore undef elements. 1682 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 1683 1684 unsigned Offset = TypeByteSize*i; 1685 1686 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 1687 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx); 1688 1689 // If the destination vector element type is narrower than the source 1690 // element type, only store the bits necessary. 1691 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) { 1692 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl, 1693 Node->getOperand(i), Idx, 1694 PtrInfo.getWithOffset(Offset), 1695 EltVT, false, false, 0)); 1696 } else 1697 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, 1698 Node->getOperand(i), Idx, 1699 PtrInfo.getWithOffset(Offset), 1700 false, false, 0)); 1701 } 1702 1703 SDValue StoreChain; 1704 if (!Stores.empty()) // Not all undef elements? 1705 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1706 &Stores[0], Stores.size()); 1707 else 1708 StoreChain = DAG.getEntryNode(); 1709 1710 // Result is a load from the stack slot. 1711 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo, false, false, 0); 1712} 1713 1714SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) { 1715 DebugLoc dl = Node->getDebugLoc(); 1716 SDValue Tmp1 = Node->getOperand(0); 1717 SDValue Tmp2 = Node->getOperand(1); 1718 1719 // Get the sign bit of the RHS. First obtain a value that has the same 1720 // sign as the sign bit, i.e. negative if and only if the sign bit is 1. 1721 SDValue SignBit; 1722 EVT FloatVT = Tmp2.getValueType(); 1723 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits()); 1724 if (isTypeLegal(IVT)) { 1725 // Convert to an integer with the same sign bit. 1726 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2); 1727 } else { 1728 // Store the float to memory, then load the sign part out as an integer. 1729 MVT LoadTy = TLI.getPointerTy(); 1730 // First create a temporary that is aligned for both the load and store. 1731 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy); 1732 // Then store the float to it. 1733 SDValue Ch = 1734 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(), 1735 false, false, 0); 1736 if (TLI.isBigEndian()) { 1737 assert(FloatVT.isByteSized() && "Unsupported floating point type!"); 1738 // Load out a legal integer with the same sign bit as the float. 1739 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(), 1740 false, false, 0); 1741 } else { // Little endian 1742 SDValue LoadPtr = StackPtr; 1743 // The float may be wider than the integer we are going to load. Advance 1744 // the pointer so that the loaded integer will contain the sign bit. 1745 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits(); 1746 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8; 1747 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), 1748 LoadPtr, DAG.getIntPtrConstant(ByteOffset)); 1749 // Load a legal integer containing the sign bit. 1750 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(), 1751 false, false, 0); 1752 // Move the sign bit to the top bit of the loaded integer. 1753 unsigned BitShift = LoadTy.getSizeInBits() - 1754 (FloatVT.getSizeInBits() - 8 * ByteOffset); 1755 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?"); 1756 if (BitShift) 1757 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit, 1758 DAG.getConstant(BitShift, 1759 TLI.getShiftAmountTy(SignBit.getValueType()))); 1760 } 1761 } 1762 // Now get the sign bit proper, by seeing whether the value is negative. 1763 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()), 1764 SignBit, DAG.getConstant(0, SignBit.getValueType()), 1765 ISD::SETLT); 1766 // Get the absolute value of the result. 1767 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1); 1768 // Select between the nabs and abs value based on the sign bit of 1769 // the input. 1770 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit, 1771 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal), 1772 AbsVal); 1773} 1774 1775void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node, 1776 SmallVectorImpl<SDValue> &Results) { 1777 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1778 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1779 " not tell us which reg is the stack pointer!"); 1780 DebugLoc dl = Node->getDebugLoc(); 1781 EVT VT = Node->getValueType(0); 1782 SDValue Tmp1 = SDValue(Node, 0); 1783 SDValue Tmp2 = SDValue(Node, 1); 1784 SDValue Tmp3 = Node->getOperand(2); 1785 SDValue Chain = Tmp1.getOperand(0); 1786 1787 // Chain the dynamic stack allocation so that it doesn't modify the stack 1788 // pointer when other instructions are using the stack. 1789 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 1790 1791 SDValue Size = Tmp2.getOperand(1); 1792 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); 1793 Chain = SP.getValue(1); 1794 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); 1795 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 1796 if (Align > StackAlign) 1797 SP = DAG.getNode(ISD::AND, dl, VT, SP, 1798 DAG.getConstant(-(uint64_t)Align, VT)); 1799 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value 1800 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain 1801 1802 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), 1803 DAG.getIntPtrConstant(0, true), SDValue()); 1804 1805 Results.push_back(Tmp1); 1806 Results.push_back(Tmp2); 1807} 1808 1809/// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and 1810/// condition code CC on the current target. This routine expands SETCC with 1811/// illegal condition code into AND / OR of multiple SETCC values. 1812void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, 1813 SDValue &LHS, SDValue &RHS, 1814 SDValue &CC, 1815 DebugLoc dl) { 1816 EVT OpVT = LHS.getValueType(); 1817 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 1818 switch (TLI.getCondCodeAction(CCCode, OpVT)) { 1819 default: assert(0 && "Unknown condition code action!"); 1820 case TargetLowering::Legal: 1821 // Nothing to do. 1822 break; 1823 case TargetLowering::Expand: { 1824 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; 1825 unsigned Opc = 0; 1826 switch (CCCode) { 1827 default: assert(0 && "Don't know how to expand this condition!"); 1828 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break; 1829 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1830 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1831 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1832 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1833 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1834 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1835 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1836 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1837 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1838 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1839 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1840 // FIXME: Implement more expansions. 1841 } 1842 1843 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1); 1844 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2); 1845 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2); 1846 RHS = SDValue(); 1847 CC = SDValue(); 1848 break; 1849 } 1850 } 1851} 1852 1853/// EmitStackConvert - Emit a store/load combination to the stack. This stores 1854/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 1855/// a load from the stack slot to DestVT, extending it if needed. 1856/// The resultant code need not be legal. 1857SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, 1858 EVT SlotVT, 1859 EVT DestVT, 1860 DebugLoc dl) { 1861 // Create the stack frame object. 1862 unsigned SrcAlign = 1863 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType(). 1864 getTypeForEVT(*DAG.getContext())); 1865 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); 1866 1867 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 1868 int SPFI = StackPtrFI->getIndex(); 1869 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI); 1870 1871 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 1872 unsigned SlotSize = SlotVT.getSizeInBits(); 1873 unsigned DestSize = DestVT.getSizeInBits(); 1874 const Type *DestType = DestVT.getTypeForEVT(*DAG.getContext()); 1875 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(DestType); 1876 1877 // Emit a store to the stack slot. Use a truncstore if the input value is 1878 // later than DestVT. 1879 SDValue Store; 1880 1881 if (SrcSize > SlotSize) 1882 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1883 PtrInfo, SlotVT, false, false, SrcAlign); 1884 else { 1885 assert(SrcSize == SlotSize && "Invalid store"); 1886 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1887 PtrInfo, false, false, SrcAlign); 1888 } 1889 1890 // Result is a load from the stack slot. 1891 if (SlotSize == DestSize) 1892 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo, 1893 false, false, DestAlign); 1894 1895 assert(SlotSize < DestSize && "Unknown extension!"); 1896 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, 1897 PtrInfo, SlotVT, false, false, DestAlign); 1898} 1899 1900SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 1901 DebugLoc dl = Node->getDebugLoc(); 1902 // Create a vector sized/aligned stack slot, store the value to element #0, 1903 // then load the whole vector back out. 1904 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 1905 1906 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 1907 int SPFI = StackPtrFI->getIndex(); 1908 1909 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0), 1910 StackPtr, 1911 MachinePointerInfo::getFixedStack(SPFI), 1912 Node->getValueType(0).getVectorElementType(), 1913 false, false, 0); 1914 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr, 1915 MachinePointerInfo::getFixedStack(SPFI), 1916 false, false, 0); 1917} 1918 1919 1920/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 1921/// support the operation, but do support the resultant vector type. 1922SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 1923 unsigned NumElems = Node->getNumOperands(); 1924 SDValue Value1, Value2; 1925 DebugLoc dl = Node->getDebugLoc(); 1926 EVT VT = Node->getValueType(0); 1927 EVT OpVT = Node->getOperand(0).getValueType(); 1928 EVT EltVT = VT.getVectorElementType(); 1929 1930 // If the only non-undef value is the low element, turn this into a 1931 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 1932 bool isOnlyLowElement = true; 1933 bool MoreThanTwoValues = false; 1934 bool isConstant = true; 1935 for (unsigned i = 0; i < NumElems; ++i) { 1936 SDValue V = Node->getOperand(i); 1937 if (V.getOpcode() == ISD::UNDEF) 1938 continue; 1939 if (i > 0) 1940 isOnlyLowElement = false; 1941 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) 1942 isConstant = false; 1943 1944 if (!Value1.getNode()) { 1945 Value1 = V; 1946 } else if (!Value2.getNode()) { 1947 if (V != Value1) 1948 Value2 = V; 1949 } else if (V != Value1 && V != Value2) { 1950 MoreThanTwoValues = true; 1951 } 1952 } 1953 1954 if (!Value1.getNode()) 1955 return DAG.getUNDEF(VT); 1956 1957 if (isOnlyLowElement) 1958 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0)); 1959 1960 // If all elements are constants, create a load from the constant pool. 1961 if (isConstant) { 1962 std::vector<Constant*> CV; 1963 for (unsigned i = 0, e = NumElems; i != e; ++i) { 1964 if (ConstantFPSDNode *V = 1965 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 1966 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue())); 1967 } else if (ConstantSDNode *V = 1968 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 1969 if (OpVT==EltVT) 1970 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue())); 1971 else { 1972 // If OpVT and EltVT don't match, EltVT is not legal and the 1973 // element values have been promoted/truncated earlier. Undo this; 1974 // we don't want a v16i8 to become a v16i32 for example. 1975 const ConstantInt *CI = V->getConstantIntValue(); 1976 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()), 1977 CI->getZExtValue())); 1978 } 1979 } else { 1980 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 1981 const Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext()); 1982 CV.push_back(UndefValue::get(OpNTy)); 1983 } 1984 } 1985 Constant *CP = ConstantVector::get(CV); 1986 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 1987 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 1988 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 1989 MachinePointerInfo::getConstantPool(), 1990 false, false, Alignment); 1991 } 1992 1993 if (!MoreThanTwoValues) { 1994 SmallVector<int, 8> ShuffleVec(NumElems, -1); 1995 for (unsigned i = 0; i < NumElems; ++i) { 1996 SDValue V = Node->getOperand(i); 1997 if (V.getOpcode() == ISD::UNDEF) 1998 continue; 1999 ShuffleVec[i] = V == Value1 ? 0 : NumElems; 2000 } 2001 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) { 2002 // Get the splatted value into the low element of a vector register. 2003 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1); 2004 SDValue Vec2; 2005 if (Value2.getNode()) 2006 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2); 2007 else 2008 Vec2 = DAG.getUNDEF(VT); 2009 2010 // Return shuffle(LowValVec, undef, <0,0,0,0>) 2011 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data()); 2012 } 2013 } 2014 2015 // Otherwise, we can't handle this case efficiently. 2016 return ExpandVectorBuildThroughStack(Node); 2017} 2018 2019// ExpandLibCall - Expand a node into a call to a libcall. If the result value 2020// does not fit into a register, return the lo part and set the hi part to the 2021// by-reg argument. If it does fit into a single register, return the result 2022// and leave the Hi part unset. 2023SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 2024 bool isSigned) { 2025 // The input chain to this libcall is the entry node of the function. 2026 // Legalizing the call will automatically add the previous call to the 2027 // dependence. 2028 SDValue InChain = DAG.getEntryNode(); 2029 2030 TargetLowering::ArgListTy Args; 2031 TargetLowering::ArgListEntry Entry; 2032 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2033 EVT ArgVT = Node->getOperand(i).getValueType(); 2034 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 2035 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 2036 Entry.isSExt = isSigned; 2037 Entry.isZExt = !isSigned; 2038 Args.push_back(Entry); 2039 } 2040 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 2041 TLI.getPointerTy()); 2042 2043 // Splice the libcall in wherever FindInputOutputChains tells us to. 2044 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext()); 2045 2046 // isTailCall may be true since the callee does not reference caller stack 2047 // frame. Check if it's in the right position. 2048 bool isTailCall = isInTailCallPosition(DAG, Node, TLI); 2049 std::pair<SDValue, SDValue> CallInfo = 2050 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 2051 0, TLI.getLibcallCallingConv(LC), isTailCall, 2052 /*isReturnValueUsed=*/true, 2053 Callee, Args, DAG, Node->getDebugLoc()); 2054 2055 if (!CallInfo.second.getNode()) 2056 // It's a tailcall, return the chain (which is the DAG root). 2057 return DAG.getRoot(); 2058 2059 // Legalize the call sequence, starting with the chain. This will advance 2060 // the LastCALLSEQ to the legalized version of the CALLSEQ_END node that 2061 // was added by LowerCallTo (guaranteeing proper serialization of calls). 2062 LegalizeOp(CallInfo.second); 2063 return CallInfo.first; 2064} 2065 2066// ExpandChainLibCall - Expand a node into a call to a libcall. Similar to 2067// ExpandLibCall except that the first operand is the in-chain. 2068std::pair<SDValue, SDValue> 2069SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC, 2070 SDNode *Node, 2071 bool isSigned) { 2072 SDValue InChain = Node->getOperand(0); 2073 2074 TargetLowering::ArgListTy Args; 2075 TargetLowering::ArgListEntry Entry; 2076 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) { 2077 EVT ArgVT = Node->getOperand(i).getValueType(); 2078 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 2079 Entry.Node = Node->getOperand(i); 2080 Entry.Ty = ArgTy; 2081 Entry.isSExt = isSigned; 2082 Entry.isZExt = !isSigned; 2083 Args.push_back(Entry); 2084 } 2085 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 2086 TLI.getPointerTy()); 2087 2088 // Splice the libcall in wherever FindInputOutputChains tells us to. 2089 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext()); 2090 std::pair<SDValue, SDValue> CallInfo = 2091 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 2092 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false, 2093 /*isReturnValueUsed=*/true, 2094 Callee, Args, DAG, Node->getDebugLoc()); 2095 2096 // Legalize the call sequence, starting with the chain. This will advance 2097 // the LastCALLSEQ to the legalized version of the CALLSEQ_END node that 2098 // was added by LowerCallTo (guaranteeing proper serialization of calls). 2099 LegalizeOp(CallInfo.second); 2100 return CallInfo; 2101} 2102 2103SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node, 2104 RTLIB::Libcall Call_F32, 2105 RTLIB::Libcall Call_F64, 2106 RTLIB::Libcall Call_F80, 2107 RTLIB::Libcall Call_PPCF128) { 2108 RTLIB::Libcall LC; 2109 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 2110 default: assert(0 && "Unexpected request for libcall!"); 2111 case MVT::f32: LC = Call_F32; break; 2112 case MVT::f64: LC = Call_F64; break; 2113 case MVT::f80: LC = Call_F80; break; 2114 case MVT::ppcf128: LC = Call_PPCF128; break; 2115 } 2116 return ExpandLibCall(LC, Node, false); 2117} 2118 2119SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned, 2120 RTLIB::Libcall Call_I8, 2121 RTLIB::Libcall Call_I16, 2122 RTLIB::Libcall Call_I32, 2123 RTLIB::Libcall Call_I64, 2124 RTLIB::Libcall Call_I128) { 2125 RTLIB::Libcall LC; 2126 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 2127 default: assert(0 && "Unexpected request for libcall!"); 2128 case MVT::i8: LC = Call_I8; break; 2129 case MVT::i16: LC = Call_I16; break; 2130 case MVT::i32: LC = Call_I32; break; 2131 case MVT::i64: LC = Call_I64; break; 2132 case MVT::i128: LC = Call_I128; break; 2133 } 2134 return ExpandLibCall(LC, Node, isSigned); 2135} 2136 2137/// isDivRemLibcallAvailable - Return true if divmod libcall is available. 2138static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned, 2139 const TargetLowering &TLI) { 2140 RTLIB::Libcall LC; 2141 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 2142 default: assert(0 && "Unexpected request for libcall!"); 2143 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break; 2144 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break; 2145 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break; 2146 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break; 2147 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break; 2148 } 2149 2150 return TLI.getLibcallName(LC) != 0; 2151} 2152 2153/// UseDivRem - Only issue divrem libcall if both quotient and remainder are 2154/// needed. 2155static bool UseDivRem(SDNode *Node, bool isSigned, bool isDIV) { 2156 unsigned OtherOpcode = 0; 2157 if (isSigned) 2158 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV; 2159 else 2160 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV; 2161 2162 SDValue Op0 = Node->getOperand(0); 2163 SDValue Op1 = Node->getOperand(1); 2164 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(), 2165 UE = Op0.getNode()->use_end(); UI != UE; ++UI) { 2166 SDNode *User = *UI; 2167 if (User == Node) 2168 continue; 2169 if (User->getOpcode() == OtherOpcode && 2170 User->getOperand(0) == Op0 && 2171 User->getOperand(1) == Op1) 2172 return true; 2173 } 2174 return false; 2175} 2176 2177/// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem 2178/// pairs. 2179void 2180SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node, 2181 SmallVectorImpl<SDValue> &Results) { 2182 unsigned Opcode = Node->getOpcode(); 2183 bool isSigned = Opcode == ISD::SDIVREM; 2184 2185 RTLIB::Libcall LC; 2186 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 2187 default: assert(0 && "Unexpected request for libcall!"); 2188 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break; 2189 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break; 2190 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break; 2191 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break; 2192 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break; 2193 } 2194 2195 // The input chain to this libcall is the entry node of the function. 2196 // Legalizing the call will automatically add the previous call to the 2197 // dependence. 2198 SDValue InChain = DAG.getEntryNode(); 2199 2200 EVT RetVT = Node->getValueType(0); 2201 const Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); 2202 2203 TargetLowering::ArgListTy Args; 2204 TargetLowering::ArgListEntry Entry; 2205 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2206 EVT ArgVT = Node->getOperand(i).getValueType(); 2207 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 2208 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 2209 Entry.isSExt = isSigned; 2210 Entry.isZExt = !isSigned; 2211 Args.push_back(Entry); 2212 } 2213 2214 // Also pass the return address of the remainder. 2215 SDValue FIPtr = DAG.CreateStackTemporary(RetVT); 2216 Entry.Node = FIPtr; 2217 Entry.Ty = RetTy->getPointerTo(); 2218 Entry.isSExt = isSigned; 2219 Entry.isZExt = !isSigned; 2220 Args.push_back(Entry); 2221 2222 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 2223 TLI.getPointerTy()); 2224 2225 // Splice the libcall in wherever FindInputOutputChains tells us to. 2226 DebugLoc dl = Node->getDebugLoc(); 2227 std::pair<SDValue, SDValue> CallInfo = 2228 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 2229 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false, 2230 /*isReturnValueUsed=*/true, Callee, Args, DAG, dl); 2231 2232 // Legalize the call sequence, starting with the chain. This will advance 2233 // the LastCALLSEQ to the legalized version of the CALLSEQ_END node that 2234 // was added by LowerCallTo (guaranteeing proper serialization of calls). 2235 LegalizeOp(CallInfo.second); 2236 2237 // Remainder is loaded back from the stack frame. 2238 SDValue Rem = DAG.getLoad(RetVT, dl, getLastCALLSEQ(), FIPtr, 2239 MachinePointerInfo(), false, false, 0); 2240 Results.push_back(CallInfo.first); 2241 Results.push_back(Rem); 2242} 2243 2244/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 2245/// INT_TO_FP operation of the specified operand when the target requests that 2246/// we expand it. At this point, we know that the result and operand types are 2247/// legal for the target. 2248SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 2249 SDValue Op0, 2250 EVT DestVT, 2251 DebugLoc dl) { 2252 if (Op0.getValueType() == MVT::i32) { 2253 // simple 32-bit [signed|unsigned] integer to float/double expansion 2254 2255 // Get the stack frame index of a 8 byte buffer. 2256 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); 2257 2258 // word offset constant for Hi/Lo address computation 2259 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 2260 // set up Hi and Lo (into buffer) address based on endian 2261 SDValue Hi = StackSlot; 2262 SDValue Lo = DAG.getNode(ISD::ADD, dl, 2263 TLI.getPointerTy(), StackSlot, WordOff); 2264 if (TLI.isLittleEndian()) 2265 std::swap(Hi, Lo); 2266 2267 // if signed map to unsigned space 2268 SDValue Op0Mapped; 2269 if (isSigned) { 2270 // constant used to invert sign bit (signed to unsigned mapping) 2271 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); 2272 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit); 2273 } else { 2274 Op0Mapped = Op0; 2275 } 2276 // store the lo of the constructed double - based on integer input 2277 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, 2278 Op0Mapped, Lo, MachinePointerInfo(), 2279 false, false, 0); 2280 // initial hi portion of constructed double 2281 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 2282 // store the hi of the constructed double - biased exponent 2283 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi, 2284 MachinePointerInfo(), 2285 false, false, 0); 2286 // load the constructed double 2287 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, 2288 MachinePointerInfo(), false, false, 0); 2289 // FP constant to bias correct the final result 2290 SDValue Bias = DAG.getConstantFP(isSigned ? 2291 BitsToDouble(0x4330000080000000ULL) : 2292 BitsToDouble(0x4330000000000000ULL), 2293 MVT::f64); 2294 // subtract the bias 2295 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); 2296 // final result 2297 SDValue Result; 2298 // handle final rounding 2299 if (DestVT == MVT::f64) { 2300 // do nothing 2301 Result = Sub; 2302 } else if (DestVT.bitsLT(MVT::f64)) { 2303 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 2304 DAG.getIntPtrConstant(0)); 2305 } else if (DestVT.bitsGT(MVT::f64)) { 2306 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 2307 } 2308 return Result; 2309 } 2310 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 2311 // Code below here assumes !isSigned without checking again. 2312 2313 // Implementation of unsigned i64 to f64 following the algorithm in 2314 // __floatundidf in compiler_rt. This implementation has the advantage 2315 // of performing rounding correctly, both in the default rounding mode 2316 // and in all alternate rounding modes. 2317 // TODO: Generalize this for use with other types. 2318 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) { 2319 SDValue TwoP52 = 2320 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64); 2321 SDValue TwoP84PlusTwoP52 = 2322 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64); 2323 SDValue TwoP84 = 2324 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64); 2325 2326 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32); 2327 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, 2328 DAG.getConstant(32, MVT::i64)); 2329 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52); 2330 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84); 2331 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr); 2332 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr); 2333 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt, 2334 TwoP84PlusTwoP52); 2335 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub); 2336 } 2337 2338 // Implementation of unsigned i64 to f32. 2339 // TODO: Generalize this for use with other types. 2340 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) { 2341 // For unsigned conversions, convert them to signed conversions using the 2342 // algorithm from the x86_64 __floatundidf in compiler_rt. 2343 if (!isSigned) { 2344 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0); 2345 2346 SDValue ShiftConst = 2347 DAG.getConstant(1, TLI.getShiftAmountTy(Op0.getValueType())); 2348 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst); 2349 SDValue AndConst = DAG.getConstant(1, MVT::i64); 2350 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst); 2351 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr); 2352 2353 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or); 2354 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt); 2355 2356 // TODO: This really should be implemented using a branch rather than a 2357 // select. We happen to get lucky and machinesink does the right 2358 // thing most of the time. This would be a good candidate for a 2359 //pseudo-op, or, even better, for whole-function isel. 2360 SDValue SignBitTest = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64), 2361 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT); 2362 return DAG.getNode(ISD::SELECT, dl, MVT::f32, SignBitTest, Slow, Fast); 2363 } 2364 2365 // Otherwise, implement the fully general conversion. 2366 2367 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, 2368 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64)); 2369 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, 2370 DAG.getConstant(UINT64_C(0x800), MVT::i64)); 2371 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, 2372 DAG.getConstant(UINT64_C(0x7ff), MVT::i64)); 2373 SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64), 2374 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE); 2375 SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0); 2376 SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64), 2377 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64), 2378 ISD::SETUGE); 2379 SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0); 2380 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType()); 2381 2382 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2, 2383 DAG.getConstant(32, SHVT)); 2384 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh); 2385 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc); 2386 SDValue TwoP32 = 2387 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64); 2388 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt); 2389 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2); 2390 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo); 2391 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2); 2392 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd, 2393 DAG.getIntPtrConstant(0)); 2394 } 2395 2396 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); 2397 2398 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()), 2399 Op0, DAG.getConstant(0, Op0.getValueType()), 2400 ISD::SETLT); 2401 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 2402 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), 2403 SignSet, Four, Zero); 2404 2405 // If the sign bit of the integer is set, the large number will be treated 2406 // as a negative number. To counteract this, the dynamic code adds an 2407 // offset depending on the data type. 2408 uint64_t FF; 2409 switch (Op0.getValueType().getSimpleVT().SimpleTy) { 2410 default: assert(0 && "Unsupported integer type!"); 2411 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 2412 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 2413 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 2414 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 2415 } 2416 if (TLI.isLittleEndian()) FF <<= 32; 2417 Constant *FudgeFactor = ConstantInt::get( 2418 Type::getInt64Ty(*DAG.getContext()), FF); 2419 2420 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 2421 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 2422 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset); 2423 Alignment = std::min(Alignment, 4u); 2424 SDValue FudgeInReg; 2425 if (DestVT == MVT::f32) 2426 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx, 2427 MachinePointerInfo::getConstantPool(), 2428 false, false, Alignment); 2429 else { 2430 FudgeInReg = 2431 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, 2432 DAG.getEntryNode(), CPIdx, 2433 MachinePointerInfo::getConstantPool(), 2434 MVT::f32, false, false, Alignment)); 2435 } 2436 2437 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg); 2438} 2439 2440/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 2441/// *INT_TO_FP operation of the specified operand when the target requests that 2442/// we promote it. At this point, we know that the result and operand types are 2443/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 2444/// operation that takes a larger input. 2445SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, 2446 EVT DestVT, 2447 bool isSigned, 2448 DebugLoc dl) { 2449 // First step, figure out the appropriate *INT_TO_FP operation to use. 2450 EVT NewInTy = LegalOp.getValueType(); 2451 2452 unsigned OpToUse = 0; 2453 2454 // Scan for the appropriate larger type to use. 2455 while (1) { 2456 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1); 2457 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 2458 2459 // If the target supports SINT_TO_FP of this type, use it. 2460 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) { 2461 OpToUse = ISD::SINT_TO_FP; 2462 break; 2463 } 2464 if (isSigned) continue; 2465 2466 // If the target supports UINT_TO_FP of this type, use it. 2467 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) { 2468 OpToUse = ISD::UINT_TO_FP; 2469 break; 2470 } 2471 2472 // Otherwise, try a larger type. 2473 } 2474 2475 // Okay, we found the operation and type to use. Zero extend our input to the 2476 // desired type then run the operation on it. 2477 return DAG.getNode(OpToUse, dl, DestVT, 2478 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 2479 dl, NewInTy, LegalOp)); 2480} 2481 2482/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 2483/// FP_TO_*INT operation of the specified operand when the target requests that 2484/// we promote it. At this point, we know that the result and operand types are 2485/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 2486/// operation that returns a larger result. 2487SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, 2488 EVT DestVT, 2489 bool isSigned, 2490 DebugLoc dl) { 2491 // First step, figure out the appropriate FP_TO*INT operation to use. 2492 EVT NewOutTy = DestVT; 2493 2494 unsigned OpToUse = 0; 2495 2496 // Scan for the appropriate larger type to use. 2497 while (1) { 2498 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1); 2499 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 2500 2501 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) { 2502 OpToUse = ISD::FP_TO_SINT; 2503 break; 2504 } 2505 2506 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) { 2507 OpToUse = ISD::FP_TO_UINT; 2508 break; 2509 } 2510 2511 // Otherwise, try a larger type. 2512 } 2513 2514 2515 // Okay, we found the operation and type to use. 2516 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp); 2517 2518 // Truncate the result of the extended FP_TO_*INT operation to the desired 2519 // size. 2520 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation); 2521} 2522 2523/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 2524/// 2525SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) { 2526 EVT VT = Op.getValueType(); 2527 EVT SHVT = TLI.getShiftAmountTy(VT); 2528 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 2529 switch (VT.getSimpleVT().SimpleTy) { 2530 default: assert(0 && "Unhandled Expand type in BSWAP!"); 2531 case MVT::i16: 2532 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2533 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2534 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 2535 case MVT::i32: 2536 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2537 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2538 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2539 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2540 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 2541 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 2542 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2543 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2544 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2545 case MVT::i64: 2546 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2547 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2548 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2549 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2550 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2551 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2552 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2553 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2554 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 2555 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 2556 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 2557 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 2558 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 2559 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 2560 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7); 2561 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5); 2562 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2563 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2564 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6); 2565 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2566 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4); 2567 } 2568} 2569 2570/// SplatByte - Distribute ByteVal over NumBits bits. 2571// FIXME: Move this helper to a common place. 2572static APInt SplatByte(unsigned NumBits, uint8_t ByteVal) { 2573 APInt Val = APInt(NumBits, ByteVal); 2574 unsigned Shift = 8; 2575 for (unsigned i = NumBits; i > 8; i >>= 1) { 2576 Val = (Val << Shift) | Val; 2577 Shift <<= 1; 2578 } 2579 return Val; 2580} 2581 2582/// ExpandBitCount - Expand the specified bitcount instruction into operations. 2583/// 2584SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op, 2585 DebugLoc dl) { 2586 switch (Opc) { 2587 default: assert(0 && "Cannot expand this yet!"); 2588 case ISD::CTPOP: { 2589 EVT VT = Op.getValueType(); 2590 EVT ShVT = TLI.getShiftAmountTy(VT); 2591 unsigned Len = VT.getSizeInBits(); 2592 2593 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 && 2594 "CTPOP not implemented for this type."); 2595 2596 // This is the "best" algorithm from 2597 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel 2598 2599 SDValue Mask55 = DAG.getConstant(SplatByte(Len, 0x55), VT); 2600 SDValue Mask33 = DAG.getConstant(SplatByte(Len, 0x33), VT); 2601 SDValue Mask0F = DAG.getConstant(SplatByte(Len, 0x0F), VT); 2602 SDValue Mask01 = DAG.getConstant(SplatByte(Len, 0x01), VT); 2603 2604 // v = v - ((v >> 1) & 0x55555555...) 2605 Op = DAG.getNode(ISD::SUB, dl, VT, Op, 2606 DAG.getNode(ISD::AND, dl, VT, 2607 DAG.getNode(ISD::SRL, dl, VT, Op, 2608 DAG.getConstant(1, ShVT)), 2609 Mask55)); 2610 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...) 2611 Op = DAG.getNode(ISD::ADD, dl, VT, 2612 DAG.getNode(ISD::AND, dl, VT, Op, Mask33), 2613 DAG.getNode(ISD::AND, dl, VT, 2614 DAG.getNode(ISD::SRL, dl, VT, Op, 2615 DAG.getConstant(2, ShVT)), 2616 Mask33)); 2617 // v = (v + (v >> 4)) & 0x0F0F0F0F... 2618 Op = DAG.getNode(ISD::AND, dl, VT, 2619 DAG.getNode(ISD::ADD, dl, VT, Op, 2620 DAG.getNode(ISD::SRL, dl, VT, Op, 2621 DAG.getConstant(4, ShVT))), 2622 Mask0F); 2623 // v = (v * 0x01010101...) >> (Len - 8) 2624 Op = DAG.getNode(ISD::SRL, dl, VT, 2625 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01), 2626 DAG.getConstant(Len - 8, ShVT)); 2627 2628 return Op; 2629 } 2630 case ISD::CTLZ: { 2631 // for now, we do this: 2632 // x = x | (x >> 1); 2633 // x = x | (x >> 2); 2634 // ... 2635 // x = x | (x >>16); 2636 // x = x | (x >>32); // for 64-bit input 2637 // return popcount(~x); 2638 // 2639 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 2640 EVT VT = Op.getValueType(); 2641 EVT ShVT = TLI.getShiftAmountTy(VT); 2642 unsigned len = VT.getSizeInBits(); 2643 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2644 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2645 Op = DAG.getNode(ISD::OR, dl, VT, Op, 2646 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3)); 2647 } 2648 Op = DAG.getNOT(dl, Op, VT); 2649 return DAG.getNode(ISD::CTPOP, dl, VT, Op); 2650 } 2651 case ISD::CTTZ: { 2652 // for now, we use: { return popcount(~x & (x - 1)); } 2653 // unless the target has ctlz but not ctpop, in which case we use: 2654 // { return 32 - nlz(~x & (x-1)); } 2655 // see also http://www.hackersdelight.org/HDcode/ntz.cc 2656 EVT VT = Op.getValueType(); 2657 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT, 2658 DAG.getNOT(dl, Op, VT), 2659 DAG.getNode(ISD::SUB, dl, VT, Op, 2660 DAG.getConstant(1, VT))); 2661 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 2662 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) && 2663 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) 2664 return DAG.getNode(ISD::SUB, dl, VT, 2665 DAG.getConstant(VT.getSizeInBits(), VT), 2666 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3)); 2667 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3); 2668 } 2669 } 2670} 2671 2672std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) { 2673 unsigned Opc = Node->getOpcode(); 2674 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT(); 2675 RTLIB::Libcall LC; 2676 2677 switch (Opc) { 2678 default: 2679 llvm_unreachable("Unhandled atomic intrinsic Expand!"); 2680 break; 2681 case ISD::ATOMIC_SWAP: 2682 switch (VT.SimpleTy) { 2683 default: llvm_unreachable("Unexpected value type for atomic!"); 2684 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break; 2685 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break; 2686 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break; 2687 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break; 2688 } 2689 break; 2690 case ISD::ATOMIC_CMP_SWAP: 2691 switch (VT.SimpleTy) { 2692 default: llvm_unreachable("Unexpected value type for atomic!"); 2693 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break; 2694 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break; 2695 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break; 2696 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break; 2697 } 2698 break; 2699 case ISD::ATOMIC_LOAD_ADD: 2700 switch (VT.SimpleTy) { 2701 default: llvm_unreachable("Unexpected value type for atomic!"); 2702 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break; 2703 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break; 2704 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break; 2705 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break; 2706 } 2707 break; 2708 case ISD::ATOMIC_LOAD_SUB: 2709 switch (VT.SimpleTy) { 2710 default: llvm_unreachable("Unexpected value type for atomic!"); 2711 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break; 2712 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break; 2713 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break; 2714 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break; 2715 } 2716 break; 2717 case ISD::ATOMIC_LOAD_AND: 2718 switch (VT.SimpleTy) { 2719 default: llvm_unreachable("Unexpected value type for atomic!"); 2720 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break; 2721 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break; 2722 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break; 2723 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break; 2724 } 2725 break; 2726 case ISD::ATOMIC_LOAD_OR: 2727 switch (VT.SimpleTy) { 2728 default: llvm_unreachable("Unexpected value type for atomic!"); 2729 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break; 2730 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break; 2731 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break; 2732 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break; 2733 } 2734 break; 2735 case ISD::ATOMIC_LOAD_XOR: 2736 switch (VT.SimpleTy) { 2737 default: llvm_unreachable("Unexpected value type for atomic!"); 2738 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break; 2739 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break; 2740 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break; 2741 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break; 2742 } 2743 break; 2744 case ISD::ATOMIC_LOAD_NAND: 2745 switch (VT.SimpleTy) { 2746 default: llvm_unreachable("Unexpected value type for atomic!"); 2747 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break; 2748 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break; 2749 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break; 2750 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break; 2751 } 2752 break; 2753 } 2754 2755 return ExpandChainLibCall(LC, Node, false); 2756} 2757 2758void SelectionDAGLegalize::ExpandNode(SDNode *Node, 2759 SmallVectorImpl<SDValue> &Results) { 2760 DebugLoc dl = Node->getDebugLoc(); 2761 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 2762 switch (Node->getOpcode()) { 2763 case ISD::CTPOP: 2764 case ISD::CTLZ: 2765 case ISD::CTTZ: 2766 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl); 2767 Results.push_back(Tmp1); 2768 break; 2769 case ISD::BSWAP: 2770 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl)); 2771 break; 2772 case ISD::FRAMEADDR: 2773 case ISD::RETURNADDR: 2774 case ISD::FRAME_TO_ARGS_OFFSET: 2775 Results.push_back(DAG.getConstant(0, Node->getValueType(0))); 2776 break; 2777 case ISD::FLT_ROUNDS_: 2778 Results.push_back(DAG.getConstant(1, Node->getValueType(0))); 2779 break; 2780 case ISD::EH_RETURN: 2781 case ISD::EH_LABEL: 2782 case ISD::PREFETCH: 2783 case ISD::VAEND: 2784 case ISD::EH_SJLJ_LONGJMP: 2785 case ISD::EH_SJLJ_DISPATCHSETUP: 2786 // If the target didn't expand these, there's nothing to do, so just 2787 // preserve the chain and be done. 2788 Results.push_back(Node->getOperand(0)); 2789 break; 2790 case ISD::EH_SJLJ_SETJMP: 2791 // If the target didn't expand this, just return 'zero' and preserve the 2792 // chain. 2793 Results.push_back(DAG.getConstant(0, MVT::i32)); 2794 Results.push_back(Node->getOperand(0)); 2795 break; 2796 case ISD::MEMBARRIER: { 2797 // If the target didn't lower this, lower it to '__sync_synchronize()' call 2798 TargetLowering::ArgListTy Args; 2799 std::pair<SDValue, SDValue> CallResult = 2800 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()), 2801 false, false, false, false, 0, CallingConv::C, 2802 /*isTailCall=*/false, 2803 /*isReturnValueUsed=*/true, 2804 DAG.getExternalSymbol("__sync_synchronize", 2805 TLI.getPointerTy()), 2806 Args, DAG, dl); 2807 Results.push_back(CallResult.second); 2808 break; 2809 } 2810 // By default, atomic intrinsics are marked Legal and lowered. Targets 2811 // which don't support them directly, however, may want libcalls, in which 2812 // case they mark them Expand, and we get here. 2813 case ISD::ATOMIC_SWAP: 2814 case ISD::ATOMIC_LOAD_ADD: 2815 case ISD::ATOMIC_LOAD_SUB: 2816 case ISD::ATOMIC_LOAD_AND: 2817 case ISD::ATOMIC_LOAD_OR: 2818 case ISD::ATOMIC_LOAD_XOR: 2819 case ISD::ATOMIC_LOAD_NAND: 2820 case ISD::ATOMIC_LOAD_MIN: 2821 case ISD::ATOMIC_LOAD_MAX: 2822 case ISD::ATOMIC_LOAD_UMIN: 2823 case ISD::ATOMIC_LOAD_UMAX: 2824 case ISD::ATOMIC_CMP_SWAP: { 2825 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node); 2826 Results.push_back(Tmp.first); 2827 Results.push_back(Tmp.second); 2828 break; 2829 } 2830 case ISD::DYNAMIC_STACKALLOC: 2831 ExpandDYNAMIC_STACKALLOC(Node, Results); 2832 break; 2833 case ISD::MERGE_VALUES: 2834 for (unsigned i = 0; i < Node->getNumValues(); i++) 2835 Results.push_back(Node->getOperand(i)); 2836 break; 2837 case ISD::UNDEF: { 2838 EVT VT = Node->getValueType(0); 2839 if (VT.isInteger()) 2840 Results.push_back(DAG.getConstant(0, VT)); 2841 else { 2842 assert(VT.isFloatingPoint() && "Unknown value type!"); 2843 Results.push_back(DAG.getConstantFP(0, VT)); 2844 } 2845 break; 2846 } 2847 case ISD::TRAP: { 2848 // If this operation is not supported, lower it to 'abort()' call 2849 TargetLowering::ArgListTy Args; 2850 std::pair<SDValue, SDValue> CallResult = 2851 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()), 2852 false, false, false, false, 0, CallingConv::C, 2853 /*isTailCall=*/false, 2854 /*isReturnValueUsed=*/true, 2855 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 2856 Args, DAG, dl); 2857 Results.push_back(CallResult.second); 2858 break; 2859 } 2860 case ISD::FP_ROUND: 2861 case ISD::BITCAST: 2862 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 2863 Node->getValueType(0), dl); 2864 Results.push_back(Tmp1); 2865 break; 2866 case ISD::FP_EXTEND: 2867 Tmp1 = EmitStackConvert(Node->getOperand(0), 2868 Node->getOperand(0).getValueType(), 2869 Node->getValueType(0), dl); 2870 Results.push_back(Tmp1); 2871 break; 2872 case ISD::SIGN_EXTEND_INREG: { 2873 // NOTE: we could fall back on load/store here too for targets without 2874 // SAR. However, it is doubtful that any exist. 2875 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2876 EVT VT = Node->getValueType(0); 2877 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT); 2878 if (VT.isVector()) 2879 ShiftAmountTy = VT; 2880 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 2881 ExtraVT.getScalarType().getSizeInBits(); 2882 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy); 2883 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0), 2884 Node->getOperand(0), ShiftCst); 2885 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst); 2886 Results.push_back(Tmp1); 2887 break; 2888 } 2889 case ISD::FP_ROUND_INREG: { 2890 // The only way we can lower this is to turn it into a TRUNCSTORE, 2891 // EXTLOAD pair, targeting a temporary location (a stack slot). 2892 2893 // NOTE: there is a choice here between constantly creating new stack 2894 // slots and always reusing the same one. We currently always create 2895 // new ones, as reuse may inhibit scheduling. 2896 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2897 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT, 2898 Node->getValueType(0), dl); 2899 Results.push_back(Tmp1); 2900 break; 2901 } 2902 case ISD::SINT_TO_FP: 2903 case ISD::UINT_TO_FP: 2904 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP, 2905 Node->getOperand(0), Node->getValueType(0), dl); 2906 Results.push_back(Tmp1); 2907 break; 2908 case ISD::FP_TO_UINT: { 2909 SDValue True, False; 2910 EVT VT = Node->getOperand(0).getValueType(); 2911 EVT NVT = Node->getValueType(0); 2912 APFloat apf(APInt::getNullValue(VT.getSizeInBits())); 2913 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 2914 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 2915 Tmp1 = DAG.getConstantFP(apf, VT); 2916 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), 2917 Node->getOperand(0), 2918 Tmp1, ISD::SETLT); 2919 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); 2920 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, 2921 DAG.getNode(ISD::FSUB, dl, VT, 2922 Node->getOperand(0), Tmp1)); 2923 False = DAG.getNode(ISD::XOR, dl, NVT, False, 2924 DAG.getConstant(x, NVT)); 2925 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False); 2926 Results.push_back(Tmp1); 2927 break; 2928 } 2929 case ISD::VAARG: { 2930 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2931 EVT VT = Node->getValueType(0); 2932 Tmp1 = Node->getOperand(0); 2933 Tmp2 = Node->getOperand(1); 2934 unsigned Align = Node->getConstantOperandVal(3); 2935 2936 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, 2937 MachinePointerInfo(V), false, false, 0); 2938 SDValue VAList = VAListLoad; 2939 2940 if (Align > TLI.getMinStackArgumentAlignment()) { 2941 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2"); 2942 2943 VAList = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 2944 DAG.getConstant(Align - 1, 2945 TLI.getPointerTy())); 2946 2947 VAList = DAG.getNode(ISD::AND, dl, TLI.getPointerTy(), VAList, 2948 DAG.getConstant(-(int64_t)Align, 2949 TLI.getPointerTy())); 2950 } 2951 2952 // Increment the pointer, VAList, to the next vaarg 2953 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 2954 DAG.getConstant(TLI.getTargetData()-> 2955 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())), 2956 TLI.getPointerTy())); 2957 // Store the incremented VAList to the legalized pointer 2958 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2, 2959 MachinePointerInfo(V), false, false, 0); 2960 // Load the actual argument out of the pointer VAList 2961 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(), 2962 false, false, 0)); 2963 Results.push_back(Results[0].getValue(1)); 2964 break; 2965 } 2966 case ISD::VACOPY: { 2967 // This defaults to loading a pointer from the input and storing it to the 2968 // output, returning the chain. 2969 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 2970 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 2971 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0), 2972 Node->getOperand(2), MachinePointerInfo(VS), 2973 false, false, 0); 2974 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), 2975 MachinePointerInfo(VD), false, false, 0); 2976 Results.push_back(Tmp1); 2977 break; 2978 } 2979 case ISD::EXTRACT_VECTOR_ELT: 2980 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1) 2981 // This must be an access of the only element. Return it. 2982 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), 2983 Node->getOperand(0)); 2984 else 2985 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0)); 2986 Results.push_back(Tmp1); 2987 break; 2988 case ISD::EXTRACT_SUBVECTOR: 2989 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0))); 2990 break; 2991 case ISD::INSERT_SUBVECTOR: 2992 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0))); 2993 break; 2994 case ISD::CONCAT_VECTORS: { 2995 Results.push_back(ExpandVectorBuildThroughStack(Node)); 2996 break; 2997 } 2998 case ISD::SCALAR_TO_VECTOR: 2999 Results.push_back(ExpandSCALAR_TO_VECTOR(Node)); 3000 break; 3001 case ISD::INSERT_VECTOR_ELT: 3002 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0), 3003 Node->getOperand(1), 3004 Node->getOperand(2), dl)); 3005 break; 3006 case ISD::VECTOR_SHUFFLE: { 3007 SmallVector<int, 8> Mask; 3008 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 3009 3010 EVT VT = Node->getValueType(0); 3011 EVT EltVT = VT.getVectorElementType(); 3012 if (getTypeAction(EltVT) == Promote) 3013 EltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT); 3014 unsigned NumElems = VT.getVectorNumElements(); 3015 SmallVector<SDValue, 8> Ops; 3016 for (unsigned i = 0; i != NumElems; ++i) { 3017 if (Mask[i] < 0) { 3018 Ops.push_back(DAG.getUNDEF(EltVT)); 3019 continue; 3020 } 3021 unsigned Idx = Mask[i]; 3022 if (Idx < NumElems) 3023 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 3024 Node->getOperand(0), 3025 DAG.getIntPtrConstant(Idx))); 3026 else 3027 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 3028 Node->getOperand(1), 3029 DAG.getIntPtrConstant(Idx - NumElems))); 3030 } 3031 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size()); 3032 Results.push_back(Tmp1); 3033 break; 3034 } 3035 case ISD::EXTRACT_ELEMENT: { 3036 EVT OpTy = Node->getOperand(0).getValueType(); 3037 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { 3038 // 1 -> Hi 3039 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0), 3040 DAG.getConstant(OpTy.getSizeInBits()/2, 3041 TLI.getShiftAmountTy(Node->getOperand(0).getValueType()))); 3042 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1); 3043 } else { 3044 // 0 -> Lo 3045 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), 3046 Node->getOperand(0)); 3047 } 3048 Results.push_back(Tmp1); 3049 break; 3050 } 3051 case ISD::STACKSAVE: 3052 // Expand to CopyFromReg if the target set 3053 // StackPointerRegisterToSaveRestore. 3054 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 3055 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP, 3056 Node->getValueType(0))); 3057 Results.push_back(Results[0].getValue(1)); 3058 } else { 3059 Results.push_back(DAG.getUNDEF(Node->getValueType(0))); 3060 Results.push_back(Node->getOperand(0)); 3061 } 3062 break; 3063 case ISD::STACKRESTORE: 3064 // Expand to CopyToReg if the target set 3065 // StackPointerRegisterToSaveRestore. 3066 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 3067 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP, 3068 Node->getOperand(1))); 3069 } else { 3070 Results.push_back(Node->getOperand(0)); 3071 } 3072 break; 3073 case ISD::FCOPYSIGN: 3074 Results.push_back(ExpandFCOPYSIGN(Node)); 3075 break; 3076 case ISD::FNEG: 3077 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 3078 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 3079 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1, 3080 Node->getOperand(0)); 3081 Results.push_back(Tmp1); 3082 break; 3083 case ISD::FABS: { 3084 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 3085 EVT VT = Node->getValueType(0); 3086 Tmp1 = Node->getOperand(0); 3087 Tmp2 = DAG.getConstantFP(0.0, VT); 3088 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), 3089 Tmp1, Tmp2, ISD::SETUGT); 3090 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1); 3091 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3); 3092 Results.push_back(Tmp1); 3093 break; 3094 } 3095 case ISD::FSQRT: 3096 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 3097 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128)); 3098 break; 3099 case ISD::FSIN: 3100 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64, 3101 RTLIB::SIN_F80, RTLIB::SIN_PPCF128)); 3102 break; 3103 case ISD::FCOS: 3104 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64, 3105 RTLIB::COS_F80, RTLIB::COS_PPCF128)); 3106 break; 3107 case ISD::FLOG: 3108 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64, 3109 RTLIB::LOG_F80, RTLIB::LOG_PPCF128)); 3110 break; 3111 case ISD::FLOG2: 3112 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 3113 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128)); 3114 break; 3115 case ISD::FLOG10: 3116 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 3117 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128)); 3118 break; 3119 case ISD::FEXP: 3120 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64, 3121 RTLIB::EXP_F80, RTLIB::EXP_PPCF128)); 3122 break; 3123 case ISD::FEXP2: 3124 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 3125 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128)); 3126 break; 3127 case ISD::FTRUNC: 3128 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 3129 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128)); 3130 break; 3131 case ISD::FFLOOR: 3132 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 3133 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128)); 3134 break; 3135 case ISD::FCEIL: 3136 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 3137 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128)); 3138 break; 3139 case ISD::FRINT: 3140 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64, 3141 RTLIB::RINT_F80, RTLIB::RINT_PPCF128)); 3142 break; 3143 case ISD::FNEARBYINT: 3144 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32, 3145 RTLIB::NEARBYINT_F64, 3146 RTLIB::NEARBYINT_F80, 3147 RTLIB::NEARBYINT_PPCF128)); 3148 break; 3149 case ISD::FPOWI: 3150 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64, 3151 RTLIB::POWI_F80, RTLIB::POWI_PPCF128)); 3152 break; 3153 case ISD::FPOW: 3154 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64, 3155 RTLIB::POW_F80, RTLIB::POW_PPCF128)); 3156 break; 3157 case ISD::FDIV: 3158 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64, 3159 RTLIB::DIV_F80, RTLIB::DIV_PPCF128)); 3160 break; 3161 case ISD::FREM: 3162 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64, 3163 RTLIB::REM_F80, RTLIB::REM_PPCF128)); 3164 break; 3165 case ISD::FP16_TO_FP32: 3166 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false)); 3167 break; 3168 case ISD::FP32_TO_FP16: 3169 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false)); 3170 break; 3171 case ISD::ConstantFP: { 3172 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 3173 // Check to see if this FP immediate is already legal. 3174 // If this is a legal constant, turn it into a TargetConstantFP node. 3175 if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0))) 3176 Results.push_back(SDValue(Node, 0)); 3177 else 3178 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI)); 3179 break; 3180 } 3181 case ISD::EHSELECTION: { 3182 unsigned Reg = TLI.getExceptionSelectorRegister(); 3183 assert(Reg && "Can't expand to unknown register!"); 3184 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg, 3185 Node->getValueType(0))); 3186 Results.push_back(Results[0].getValue(1)); 3187 break; 3188 } 3189 case ISD::EXCEPTIONADDR: { 3190 unsigned Reg = TLI.getExceptionAddressRegister(); 3191 assert(Reg && "Can't expand to unknown register!"); 3192 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg, 3193 Node->getValueType(0))); 3194 Results.push_back(Results[0].getValue(1)); 3195 break; 3196 } 3197 case ISD::SUB: { 3198 EVT VT = Node->getValueType(0); 3199 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) && 3200 TLI.isOperationLegalOrCustom(ISD::XOR, VT) && 3201 "Don't know how to expand this subtraction!"); 3202 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1), 3203 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT)); 3204 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT)); 3205 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1)); 3206 break; 3207 } 3208 case ISD::UREM: 3209 case ISD::SREM: { 3210 EVT VT = Node->getValueType(0); 3211 SDVTList VTs = DAG.getVTList(VT, VT); 3212 bool isSigned = Node->getOpcode() == ISD::SREM; 3213 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV; 3214 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 3215 Tmp2 = Node->getOperand(0); 3216 Tmp3 = Node->getOperand(1); 3217 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) || 3218 (isDivRemLibcallAvailable(Node, isSigned, TLI) && 3219 UseDivRem(Node, isSigned, false))) { 3220 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1); 3221 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) { 3222 // X % Y -> X-X/Y*Y 3223 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3); 3224 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3); 3225 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1); 3226 } else if (isSigned) 3227 Tmp1 = ExpandIntLibCall(Node, true, 3228 RTLIB::SREM_I8, 3229 RTLIB::SREM_I16, RTLIB::SREM_I32, 3230 RTLIB::SREM_I64, RTLIB::SREM_I128); 3231 else 3232 Tmp1 = ExpandIntLibCall(Node, false, 3233 RTLIB::UREM_I8, 3234 RTLIB::UREM_I16, RTLIB::UREM_I32, 3235 RTLIB::UREM_I64, RTLIB::UREM_I128); 3236 Results.push_back(Tmp1); 3237 break; 3238 } 3239 case ISD::UDIV: 3240 case ISD::SDIV: { 3241 bool isSigned = Node->getOpcode() == ISD::SDIV; 3242 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 3243 EVT VT = Node->getValueType(0); 3244 SDVTList VTs = DAG.getVTList(VT, VT); 3245 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) || 3246 (isDivRemLibcallAvailable(Node, isSigned, TLI) && 3247 UseDivRem(Node, isSigned, true))) 3248 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0), 3249 Node->getOperand(1)); 3250 else if (isSigned) 3251 Tmp1 = ExpandIntLibCall(Node, true, 3252 RTLIB::SDIV_I8, 3253 RTLIB::SDIV_I16, RTLIB::SDIV_I32, 3254 RTLIB::SDIV_I64, RTLIB::SDIV_I128); 3255 else 3256 Tmp1 = ExpandIntLibCall(Node, false, 3257 RTLIB::UDIV_I8, 3258 RTLIB::UDIV_I16, RTLIB::UDIV_I32, 3259 RTLIB::UDIV_I64, RTLIB::UDIV_I128); 3260 Results.push_back(Tmp1); 3261 break; 3262 } 3263 case ISD::MULHU: 3264 case ISD::MULHS: { 3265 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : 3266 ISD::SMUL_LOHI; 3267 EVT VT = Node->getValueType(0); 3268 SDVTList VTs = DAG.getVTList(VT, VT); 3269 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) && 3270 "If this wasn't legal, it shouldn't have been created!"); 3271 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0), 3272 Node->getOperand(1)); 3273 Results.push_back(Tmp1.getValue(1)); 3274 break; 3275 } 3276 case ISD::SDIVREM: 3277 case ISD::UDIVREM: 3278 // Expand into divrem libcall 3279 ExpandDivRemLibCall(Node, Results); 3280 break; 3281 case ISD::MUL: { 3282 EVT VT = Node->getValueType(0); 3283 SDVTList VTs = DAG.getVTList(VT, VT); 3284 // See if multiply or divide can be lowered using two-result operations. 3285 // We just need the low half of the multiply; try both the signed 3286 // and unsigned forms. If the target supports both SMUL_LOHI and 3287 // UMUL_LOHI, form a preference by checking which forms of plain 3288 // MULH it supports. 3289 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT); 3290 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT); 3291 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT); 3292 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT); 3293 unsigned OpToUse = 0; 3294 if (HasSMUL_LOHI && !HasMULHS) { 3295 OpToUse = ISD::SMUL_LOHI; 3296 } else if (HasUMUL_LOHI && !HasMULHU) { 3297 OpToUse = ISD::UMUL_LOHI; 3298 } else if (HasSMUL_LOHI) { 3299 OpToUse = ISD::SMUL_LOHI; 3300 } else if (HasUMUL_LOHI) { 3301 OpToUse = ISD::UMUL_LOHI; 3302 } 3303 if (OpToUse) { 3304 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0), 3305 Node->getOperand(1))); 3306 break; 3307 } 3308 Tmp1 = ExpandIntLibCall(Node, false, 3309 RTLIB::MUL_I8, 3310 RTLIB::MUL_I16, RTLIB::MUL_I32, 3311 RTLIB::MUL_I64, RTLIB::MUL_I128); 3312 Results.push_back(Tmp1); 3313 break; 3314 } 3315 case ISD::SADDO: 3316 case ISD::SSUBO: { 3317 SDValue LHS = Node->getOperand(0); 3318 SDValue RHS = Node->getOperand(1); 3319 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 3320 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 3321 LHS, RHS); 3322 Results.push_back(Sum); 3323 EVT OType = Node->getValueType(1); 3324 3325 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 3326 3327 // LHSSign -> LHS >= 0 3328 // RHSSign -> RHS >= 0 3329 // SumSign -> Sum >= 0 3330 // 3331 // Add: 3332 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 3333 // Sub: 3334 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 3335 // 3336 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); 3337 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); 3338 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, 3339 Node->getOpcode() == ISD::SADDO ? 3340 ISD::SETEQ : ISD::SETNE); 3341 3342 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); 3343 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); 3344 3345 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); 3346 Results.push_back(Cmp); 3347 break; 3348 } 3349 case ISD::UADDO: 3350 case ISD::USUBO: { 3351 SDValue LHS = Node->getOperand(0); 3352 SDValue RHS = Node->getOperand(1); 3353 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ? 3354 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 3355 LHS, RHS); 3356 Results.push_back(Sum); 3357 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS, 3358 Node->getOpcode () == ISD::UADDO ? 3359 ISD::SETULT : ISD::SETUGT)); 3360 break; 3361 } 3362 case ISD::UMULO: 3363 case ISD::SMULO: { 3364 EVT VT = Node->getValueType(0); 3365 SDValue LHS = Node->getOperand(0); 3366 SDValue RHS = Node->getOperand(1); 3367 SDValue BottomHalf; 3368 SDValue TopHalf; 3369 static const unsigned Ops[2][3] = 3370 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND }, 3371 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }}; 3372 bool isSigned = Node->getOpcode() == ISD::SMULO; 3373 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) { 3374 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS); 3375 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS); 3376 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) { 3377 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS, 3378 RHS); 3379 TopHalf = BottomHalf.getValue(1); 3380 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(), 3381 VT.getSizeInBits() * 2))) { 3382 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2); 3383 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS); 3384 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS); 3385 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS); 3386 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 3387 DAG.getIntPtrConstant(0)); 3388 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 3389 DAG.getIntPtrConstant(1)); 3390 } else { 3391 // We can fall back to a libcall with an illegal type for the MUL if we 3392 // have a libcall big enough. 3393 // Also, we can fall back to a division in some cases, but that's a big 3394 // performance hit in the general case. 3395 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2); 3396 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3397 if (WideVT == MVT::i16) 3398 LC = RTLIB::MUL_I16; 3399 else if (WideVT == MVT::i32) 3400 LC = RTLIB::MUL_I32; 3401 else if (WideVT == MVT::i64) 3402 LC = RTLIB::MUL_I64; 3403 else if (WideVT == MVT::i128) 3404 LC = RTLIB::MUL_I128; 3405 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!"); 3406 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS); 3407 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS); 3408 3409 SDValue Ret = ExpandLibCall(LC, Node, isSigned); 3410 BottomHalf = DAG.getNode(ISD::TRUNCATE, dl, VT, Ret); 3411 TopHalf = DAG.getNode(ISD::SRL, dl, Ret.getValueType(), Ret, 3412 DAG.getConstant(VT.getSizeInBits(), TLI.getPointerTy())); 3413 TopHalf = DAG.getNode(ISD::TRUNCATE, dl, VT, TopHalf); 3414 } 3415 if (isSigned) { 3416 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, 3417 TLI.getShiftAmountTy(BottomHalf.getValueType())); 3418 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1); 3419 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1, 3420 ISD::SETNE); 3421 } else { 3422 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, 3423 DAG.getConstant(0, VT), ISD::SETNE); 3424 } 3425 Results.push_back(BottomHalf); 3426 Results.push_back(TopHalf); 3427 break; 3428 } 3429 case ISD::BUILD_PAIR: { 3430 EVT PairTy = Node->getValueType(0); 3431 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0)); 3432 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1)); 3433 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2, 3434 DAG.getConstant(PairTy.getSizeInBits()/2, 3435 TLI.getShiftAmountTy(PairTy))); 3436 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2)); 3437 break; 3438 } 3439 case ISD::SELECT: 3440 Tmp1 = Node->getOperand(0); 3441 Tmp2 = Node->getOperand(1); 3442 Tmp3 = Node->getOperand(2); 3443 if (Tmp1.getOpcode() == ISD::SETCC) { 3444 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1), 3445 Tmp2, Tmp3, 3446 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 3447 } else { 3448 Tmp1 = DAG.getSelectCC(dl, Tmp1, 3449 DAG.getConstant(0, Tmp1.getValueType()), 3450 Tmp2, Tmp3, ISD::SETNE); 3451 } 3452 Results.push_back(Tmp1); 3453 break; 3454 case ISD::BR_JT: { 3455 SDValue Chain = Node->getOperand(0); 3456 SDValue Table = Node->getOperand(1); 3457 SDValue Index = Node->getOperand(2); 3458 3459 EVT PTy = TLI.getPointerTy(); 3460 3461 const TargetData &TD = *TLI.getTargetData(); 3462 unsigned EntrySize = 3463 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD); 3464 3465 Index = DAG.getNode(ISD::MUL, dl, PTy, 3466 Index, DAG.getConstant(EntrySize, PTy)); 3467 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 3468 3469 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); 3470 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr, 3471 MachinePointerInfo::getJumpTable(), MemVT, 3472 false, false, 0); 3473 Addr = LD; 3474 if (TM.getRelocationModel() == Reloc::PIC_) { 3475 // For PIC, the sequence is: 3476 // BRIND(load(Jumptable + index) + RelocBase) 3477 // RelocBase can be JumpTable, GOT or some sort of global base. 3478 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, 3479 TLI.getPICJumpTableRelocBase(Table, DAG)); 3480 } 3481 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr); 3482 Results.push_back(Tmp1); 3483 break; 3484 } 3485 case ISD::BRCOND: 3486 // Expand brcond's setcc into its constituent parts and create a BR_CC 3487 // Node. 3488 Tmp1 = Node->getOperand(0); 3489 Tmp2 = Node->getOperand(1); 3490 if (Tmp2.getOpcode() == ISD::SETCC) { 3491 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, 3492 Tmp1, Tmp2.getOperand(2), 3493 Tmp2.getOperand(0), Tmp2.getOperand(1), 3494 Node->getOperand(2)); 3495 } else { 3496 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, 3497 DAG.getCondCode(ISD::SETNE), Tmp2, 3498 DAG.getConstant(0, Tmp2.getValueType()), 3499 Node->getOperand(2)); 3500 } 3501 Results.push_back(Tmp1); 3502 break; 3503 case ISD::SETCC: { 3504 Tmp1 = Node->getOperand(0); 3505 Tmp2 = Node->getOperand(1); 3506 Tmp3 = Node->getOperand(2); 3507 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl); 3508 3509 // If we expanded the SETCC into an AND/OR, return the new node 3510 if (Tmp2.getNode() == 0) { 3511 Results.push_back(Tmp1); 3512 break; 3513 } 3514 3515 // Otherwise, SETCC for the given comparison type must be completely 3516 // illegal; expand it into a SELECT_CC. 3517 EVT VT = Node->getValueType(0); 3518 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, 3519 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3); 3520 Results.push_back(Tmp1); 3521 break; 3522 } 3523 case ISD::SELECT_CC: { 3524 Tmp1 = Node->getOperand(0); // LHS 3525 Tmp2 = Node->getOperand(1); // RHS 3526 Tmp3 = Node->getOperand(2); // True 3527 Tmp4 = Node->getOperand(3); // False 3528 SDValue CC = Node->getOperand(4); 3529 3530 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()), 3531 Tmp1, Tmp2, CC, dl); 3532 3533 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!"); 3534 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 3535 CC = DAG.getCondCode(ISD::SETNE); 3536 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2, 3537 Tmp3, Tmp4, CC); 3538 Results.push_back(Tmp1); 3539 break; 3540 } 3541 case ISD::BR_CC: { 3542 Tmp1 = Node->getOperand(0); // Chain 3543 Tmp2 = Node->getOperand(2); // LHS 3544 Tmp3 = Node->getOperand(3); // RHS 3545 Tmp4 = Node->getOperand(1); // CC 3546 3547 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()), 3548 Tmp2, Tmp3, Tmp4, dl); 3549 assert(depthCALLSEQ == 1 && "branch inside CALLSEQ_BEGIN/END?"); 3550 setLastCALLSEQ(DAG.getEntryNode()); 3551 3552 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!"); 3553 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 3554 Tmp4 = DAG.getCondCode(ISD::SETNE); 3555 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2, 3556 Tmp3, Node->getOperand(4)); 3557 Results.push_back(Tmp1); 3558 break; 3559 } 3560 case ISD::GLOBAL_OFFSET_TABLE: 3561 case ISD::GlobalAddress: 3562 case ISD::GlobalTLSAddress: 3563 case ISD::ExternalSymbol: 3564 case ISD::ConstantPool: 3565 case ISD::JumpTable: 3566 case ISD::INTRINSIC_W_CHAIN: 3567 case ISD::INTRINSIC_WO_CHAIN: 3568 case ISD::INTRINSIC_VOID: 3569 // FIXME: Custom lowering for these operations shouldn't return null! 3570 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 3571 Results.push_back(SDValue(Node, i)); 3572 break; 3573 } 3574} 3575void SelectionDAGLegalize::PromoteNode(SDNode *Node, 3576 SmallVectorImpl<SDValue> &Results) { 3577 EVT OVT = Node->getValueType(0); 3578 if (Node->getOpcode() == ISD::UINT_TO_FP || 3579 Node->getOpcode() == ISD::SINT_TO_FP || 3580 Node->getOpcode() == ISD::SETCC) { 3581 OVT = Node->getOperand(0).getValueType(); 3582 } 3583 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3584 DebugLoc dl = Node->getDebugLoc(); 3585 SDValue Tmp1, Tmp2, Tmp3; 3586 switch (Node->getOpcode()) { 3587 case ISD::CTTZ: 3588 case ISD::CTLZ: 3589 case ISD::CTPOP: 3590 // Zero extend the argument. 3591 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3592 // Perform the larger operation. 3593 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); 3594 if (Node->getOpcode() == ISD::CTTZ) { 3595 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3596 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), 3597 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT), 3598 ISD::SETEQ); 3599 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, 3600 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 3601 } else if (Node->getOpcode() == ISD::CTLZ) { 3602 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3603 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1, 3604 DAG.getConstant(NVT.getSizeInBits() - 3605 OVT.getSizeInBits(), NVT)); 3606 } 3607 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1)); 3608 break; 3609 case ISD::BSWAP: { 3610 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 3611 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3612 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); 3613 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, 3614 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT))); 3615 Results.push_back(Tmp1); 3616 break; 3617 } 3618 case ISD::FP_TO_UINT: 3619 case ISD::FP_TO_SINT: 3620 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0), 3621 Node->getOpcode() == ISD::FP_TO_SINT, dl); 3622 Results.push_back(Tmp1); 3623 break; 3624 case ISD::UINT_TO_FP: 3625 case ISD::SINT_TO_FP: 3626 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0), 3627 Node->getOpcode() == ISD::SINT_TO_FP, dl); 3628 Results.push_back(Tmp1); 3629 break; 3630 case ISD::AND: 3631 case ISD::OR: 3632 case ISD::XOR: { 3633 unsigned ExtOp, TruncOp; 3634 if (OVT.isVector()) { 3635 ExtOp = ISD::BITCAST; 3636 TruncOp = ISD::BITCAST; 3637 } else { 3638 assert(OVT.isInteger() && "Cannot promote logic operation"); 3639 ExtOp = ISD::ANY_EXTEND; 3640 TruncOp = ISD::TRUNCATE; 3641 } 3642 // Promote each of the values to the new type. 3643 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3644 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3645 // Perform the larger operation, then convert back 3646 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 3647 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1)); 3648 break; 3649 } 3650 case ISD::SELECT: { 3651 unsigned ExtOp, TruncOp; 3652 if (Node->getValueType(0).isVector()) { 3653 ExtOp = ISD::BITCAST; 3654 TruncOp = ISD::BITCAST; 3655 } else if (Node->getValueType(0).isInteger()) { 3656 ExtOp = ISD::ANY_EXTEND; 3657 TruncOp = ISD::TRUNCATE; 3658 } else { 3659 ExtOp = ISD::FP_EXTEND; 3660 TruncOp = ISD::FP_ROUND; 3661 } 3662 Tmp1 = Node->getOperand(0); 3663 // Promote each of the values to the new type. 3664 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3665 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2)); 3666 // Perform the larger operation, then round down. 3667 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3); 3668 if (TruncOp != ISD::FP_ROUND) 3669 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1); 3670 else 3671 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1, 3672 DAG.getIntPtrConstant(0)); 3673 Results.push_back(Tmp1); 3674 break; 3675 } 3676 case ISD::VECTOR_SHUFFLE: { 3677 SmallVector<int, 8> Mask; 3678 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 3679 3680 // Cast the two input vectors. 3681 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0)); 3682 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1)); 3683 3684 // Convert the shuffle mask to the right # elements. 3685 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask); 3686 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1); 3687 Results.push_back(Tmp1); 3688 break; 3689 } 3690 case ISD::SETCC: { 3691 unsigned ExtOp = ISD::FP_EXTEND; 3692 if (NVT.isInteger()) { 3693 ISD::CondCode CCCode = 3694 cast<CondCodeSDNode>(Node->getOperand(2))->get(); 3695 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3696 } 3697 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3698 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3699 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), 3700 Tmp1, Tmp2, Node->getOperand(2))); 3701 break; 3702 } 3703 } 3704} 3705 3706// SelectionDAG::Legalize - This is the entry point for the file. 3707// 3708void SelectionDAG::Legalize(CodeGenOpt::Level OptLevel) { 3709 /// run - This is the main entry point to this class. 3710 /// 3711 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG(); 3712} 3713 3714