ScheduleDAGSDNodes.cpp revision 79ce276083ced01256a0eb7d80731e4948ca6e87
1//===--- ScheduleDAGSDNodes.cpp - Implement the ScheduleDAGSDNodes class --===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the ScheduleDAG class, which is a base class used by 11// scheduling implementation classes. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "pre-RA-sched" 16#include "llvm/CodeGen/ScheduleDAGSDNodes.h" 17#include "llvm/CodeGen/SelectionDAG.h" 18#include "llvm/Target/TargetMachine.h" 19#include "llvm/Target/TargetInstrInfo.h" 20#include "llvm/Target/TargetRegisterInfo.h" 21#include "llvm/Support/Debug.h" 22#include "llvm/Support/raw_ostream.h" 23using namespace llvm; 24 25ScheduleDAGSDNodes::ScheduleDAGSDNodes(MachineFunction &mf) 26 : ScheduleDAG(mf) { 27} 28 29SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) { 30 SUnit *SU = NewSUnit(Old->getNode()); 31 SU->OrigNode = Old->OrigNode; 32 SU->Latency = Old->Latency; 33 SU->isTwoAddress = Old->isTwoAddress; 34 SU->isCommutable = Old->isCommutable; 35 SU->hasPhysRegDefs = Old->hasPhysRegDefs; 36 return SU; 37} 38 39/// CheckForPhysRegDependency - Check if the dependency between def and use of 40/// a specified operand is a physical register dependency. If so, returns the 41/// register and the cost of copying the register. 42static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, 43 const TargetRegisterInfo *TRI, 44 const TargetInstrInfo *TII, 45 unsigned &PhysReg, int &Cost) { 46 if (Op != 2 || User->getOpcode() != ISD::CopyToReg) 47 return; 48 49 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 50 if (TargetRegisterInfo::isVirtualRegister(Reg)) 51 return; 52 53 unsigned ResNo = User->getOperand(2).getResNo(); 54 if (Def->isMachineOpcode()) { 55 const TargetInstrDesc &II = TII->get(Def->getMachineOpcode()); 56 if (ResNo >= II.getNumDefs() && 57 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) { 58 PhysReg = Reg; 59 const TargetRegisterClass *RC = 60 TRI->getPhysicalRegisterRegClass(Reg, Def->getValueType(ResNo)); 61 Cost = RC->getCopyCost(); 62 } 63 } 64} 65 66void ScheduleDAGSDNodes::BuildSchedUnits() { 67 // During scheduling, the NodeId field of SDNode is used to map SDNodes 68 // to their associated SUnits by holding SUnits table indices. A value 69 // of -1 means the SDNode does not yet have an associated SUnit. 70 unsigned NumNodes = 0; 71 for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(), 72 E = DAG->allnodes_end(); NI != E; ++NI) { 73 NI->setNodeId(-1); 74 ++NumNodes; 75 } 76 77 // Reserve entries in the vector for each of the SUnits we are creating. This 78 // ensure that reallocation of the vector won't happen, so SUnit*'s won't get 79 // invalidated. 80 // FIXME: Multiply by 2 because we may clone nodes during scheduling. 81 // This is a temporary workaround. 82 SUnits.reserve(NumNodes * 2); 83 84 // Check to see if the scheduler cares about latencies. 85 bool UnitLatencies = ForceUnitLatencies(); 86 87 for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(), 88 E = DAG->allnodes_end(); NI != E; ++NI) { 89 if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate. 90 continue; 91 92 // If this node has already been processed, stop now. 93 if (NI->getNodeId() != -1) continue; 94 95 SUnit *NodeSUnit = NewSUnit(NI); 96 97 // See if anything is flagged to this node, if so, add them to flagged 98 // nodes. Nodes can have at most one flag input and one flag output. Flags 99 // are required the be the last operand and result of a node. 100 101 // Scan up to find flagged preds. 102 SDNode *N = NI; 103 if (N->getNumOperands() && 104 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) { 105 do { 106 N = N->getOperand(N->getNumOperands()-1).getNode(); 107 assert(N->getNodeId() == -1 && "Node already inserted!"); 108 N->setNodeId(NodeSUnit->NodeNum); 109 } while (N->getNumOperands() && 110 N->getOperand(N->getNumOperands()-1).getValueType()== MVT::Flag); 111 } 112 113 // Scan down to find any flagged succs. 114 N = NI; 115 while (N->getValueType(N->getNumValues()-1) == MVT::Flag) { 116 SDValue FlagVal(N, N->getNumValues()-1); 117 118 // There are either zero or one users of the Flag result. 119 bool HasFlagUse = false; 120 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); 121 UI != E; ++UI) 122 if (FlagVal.isOperandOf(*UI)) { 123 HasFlagUse = true; 124 assert(N->getNodeId() == -1 && "Node already inserted!"); 125 N->setNodeId(NodeSUnit->NodeNum); 126 N = *UI; 127 break; 128 } 129 if (!HasFlagUse) break; 130 } 131 132 // If there are flag operands involved, N is now the bottom-most node 133 // of the sequence of nodes that are flagged together. 134 // Update the SUnit. 135 NodeSUnit->setNode(N); 136 assert(N->getNodeId() == -1 && "Node already inserted!"); 137 N->setNodeId(NodeSUnit->NodeNum); 138 139 // Assign the Latency field of NodeSUnit using target-provided information. 140 if (UnitLatencies) 141 NodeSUnit->Latency = 1; 142 else 143 ComputeLatency(NodeSUnit); 144 } 145} 146 147void ScheduleDAGSDNodes::AddSchedEdges() { 148 // Pass 2: add the preds, succs, etc. 149 for (unsigned su = 0, e = SUnits.size(); su != e; ++su) { 150 SUnit *SU = &SUnits[su]; 151 SDNode *MainNode = SU->getNode(); 152 153 if (MainNode->isMachineOpcode()) { 154 unsigned Opc = MainNode->getMachineOpcode(); 155 const TargetInstrDesc &TID = TII->get(Opc); 156 for (unsigned i = 0; i != TID.getNumOperands(); ++i) { 157 if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) { 158 SU->isTwoAddress = true; 159 break; 160 } 161 } 162 if (TID.isCommutable()) 163 SU->isCommutable = true; 164 } 165 166 // Find all predecessors and successors of the group. 167 for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode()) { 168 if (N->isMachineOpcode() && 169 TII->get(N->getMachineOpcode()).getImplicitDefs() && 170 CountResults(N) > TII->get(N->getMachineOpcode()).getNumDefs()) 171 SU->hasPhysRegDefs = true; 172 173 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 174 SDNode *OpN = N->getOperand(i).getNode(); 175 if (isPassiveNode(OpN)) continue; // Not scheduled. 176 SUnit *OpSU = &SUnits[OpN->getNodeId()]; 177 assert(OpSU && "Node has no SUnit!"); 178 if (OpSU == SU) continue; // In the same group. 179 180 MVT OpVT = N->getOperand(i).getValueType(); 181 assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!"); 182 bool isChain = OpVT == MVT::Other; 183 184 unsigned PhysReg = 0; 185 int Cost = 1; 186 // Determine if this is a physical register dependency. 187 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost); 188 assert((PhysReg == 0 || !isChain) && 189 "Chain dependence via physreg data?"); 190 // FIXME: See ScheduleDAGSDNodes::EmitCopyFromReg. For now, scheduler 191 // emits a copy from the physical register to a virtual register unless 192 // it requires a cross class copy (cost < 0). That means we are only 193 // treating "expensive to copy" register dependency as physical register 194 // dependency. This may change in the future though. 195 if (Cost >= 0) 196 PhysReg = 0; 197 SU->addPred(SDep(OpSU, isChain ? SDep::Order : SDep::Data, 198 OpSU->Latency, PhysReg)); 199 } 200 } 201 } 202} 203 204/// BuildSchedGraph - Build the SUnit graph from the selection dag that we 205/// are input. This SUnit graph is similar to the SelectionDAG, but 206/// excludes nodes that aren't interesting to scheduling, and represents 207/// flagged together nodes with a single SUnit. 208void ScheduleDAGSDNodes::BuildSchedGraph() { 209 // Populate the SUnits array. 210 BuildSchedUnits(); 211 // Compute all the scheduling dependencies between nodes. 212 AddSchedEdges(); 213} 214 215void ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) { 216 const InstrItineraryData &InstrItins = TM.getInstrItineraryData(); 217 218 // Compute the latency for the node. We use the sum of the latencies for 219 // all nodes flagged together into this SUnit. 220 SU->Latency = 0; 221 bool SawMachineOpcode = false; 222 for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode()) 223 if (N->isMachineOpcode()) { 224 SawMachineOpcode = true; 225 SU->Latency += 226 InstrItins.getLatency(TII->get(N->getMachineOpcode()).getSchedClass()); 227 } 228} 229 230/// CountResults - The results of target nodes have register or immediate 231/// operands first, then an optional chain, and optional flag operands (which do 232/// not go into the resulting MachineInstr). 233unsigned ScheduleDAGSDNodes::CountResults(SDNode *Node) { 234 unsigned N = Node->getNumValues(); 235 while (N && Node->getValueType(N - 1) == MVT::Flag) 236 --N; 237 if (N && Node->getValueType(N - 1) == MVT::Other) 238 --N; // Skip over chain result. 239 return N; 240} 241 242/// CountOperands - The inputs to target nodes have any actual inputs first, 243/// followed by special operands that describe memory references, then an 244/// optional chain operand, then an optional flag operand. Compute the number 245/// of actual operands that will go into the resulting MachineInstr. 246unsigned ScheduleDAGSDNodes::CountOperands(SDNode *Node) { 247 unsigned N = ComputeMemOperandsEnd(Node); 248 while (N && isa<MemOperandSDNode>(Node->getOperand(N - 1).getNode())) 249 --N; // Ignore MEMOPERAND nodes 250 return N; 251} 252 253/// ComputeMemOperandsEnd - Find the index one past the last MemOperandSDNode 254/// operand 255unsigned ScheduleDAGSDNodes::ComputeMemOperandsEnd(SDNode *Node) { 256 unsigned N = Node->getNumOperands(); 257 while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag) 258 --N; 259 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) 260 --N; // Ignore chain if it exists. 261 return N; 262} 263 264 265void ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const { 266 if (!SU->getNode()) { 267 cerr << "PHYS REG COPY\n"; 268 return; 269 } 270 271 SU->getNode()->dump(DAG); 272 cerr << "\n"; 273 SmallVector<SDNode *, 4> FlaggedNodes; 274 for (SDNode *N = SU->getNode()->getFlaggedNode(); N; N = N->getFlaggedNode()) 275 FlaggedNodes.push_back(N); 276 while (!FlaggedNodes.empty()) { 277 cerr << " "; 278 FlaggedNodes.back()->dump(DAG); 279 cerr << "\n"; 280 FlaggedNodes.pop_back(); 281 } 282} 283